Blame - include/linux/mfd/wm8994/registers.h - android_kernel_oneplus_sm8150

Mark Brown

1c4d3b70

2010-01-29 18:20:28 +0000

[diff] [blame]

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/*

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* include/linux/mfd/wm8994/registers.h -- Register definitions for WM8994

*

*

* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>

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*

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* This program is free software; you can redistribute it and/or modify it

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* under the terms of the GNU General Public License as published by the

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* Free Software Foundation; either version 2 of the License, or (at your

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* option) any later version.

*

*/

#ifndef __MFD_WM8994_REGISTERS_H__

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#define __MFD_WM8994_REGISTERS_H__

/*

* Register values.

*/

#define WM8994_SOFTWARE_RESET 0x00

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#define WM8994_POWER_MANAGEMENT_1 0x01

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#define WM8994_POWER_MANAGEMENT_2 0x02

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#define WM8994_POWER_MANAGEMENT_3 0x03

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#define WM8994_POWER_MANAGEMENT_4 0x04

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#define WM8994_POWER_MANAGEMENT_5 0x05

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#define WM8994_POWER_MANAGEMENT_6 0x06

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#define WM8994_INPUT_MIXER_1 0x15

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#define WM8994_LEFT_LINE_INPUT_1_2_VOLUME 0x18

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#define WM8994_LEFT_LINE_INPUT_3_4_VOLUME 0x19

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#define WM8994_RIGHT_LINE_INPUT_1_2_VOLUME 0x1A

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#define WM8994_RIGHT_LINE_INPUT_3_4_VOLUME 0x1B

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#define WM8994_LEFT_OUTPUT_VOLUME 0x1C

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#define WM8994_RIGHT_OUTPUT_VOLUME 0x1D

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#define WM8994_LINE_OUTPUTS_VOLUME 0x1E

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#define WM8994_HPOUT2_VOLUME 0x1F

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#define WM8994_LEFT_OPGA_VOLUME 0x20

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#define WM8994_RIGHT_OPGA_VOLUME 0x21

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#define WM8994_SPKMIXL_ATTENUATION 0x22

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#define WM8994_SPKMIXR_ATTENUATION 0x23

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#define WM8994_SPKOUT_MIXERS 0x24

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#define WM8994_CLASSD 0x25

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#define WM8994_SPEAKER_VOLUME_LEFT 0x26

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#define WM8994_SPEAKER_VOLUME_RIGHT 0x27

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#define WM8994_INPUT_MIXER_2 0x28

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#define WM8994_INPUT_MIXER_3 0x29

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#define WM8994_INPUT_MIXER_4 0x2A

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#define WM8994_INPUT_MIXER_5 0x2B

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#define WM8994_INPUT_MIXER_6 0x2C

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#define WM8994_OUTPUT_MIXER_1 0x2D

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#define WM8994_OUTPUT_MIXER_2 0x2E

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#define WM8994_OUTPUT_MIXER_3 0x2F

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#define WM8994_OUTPUT_MIXER_4 0x30

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#define WM8994_OUTPUT_MIXER_5 0x31

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#define WM8994_OUTPUT_MIXER_6 0x32

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#define WM8994_HPOUT2_MIXER 0x33

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#define WM8994_LINE_MIXER_1 0x34

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#define WM8994_LINE_MIXER_2 0x35

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#define WM8994_SPEAKER_MIXER 0x36

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#define WM8994_ADDITIONAL_CONTROL 0x37

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#define WM8994_ANTIPOP_1 0x38

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#define WM8994_ANTIPOP_2 0x39

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#define WM8994_MICBIAS 0x3A

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#define WM8994_LDO_1 0x3B

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#define WM8994_LDO_2 0x3C

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#define WM8994_CHARGE_PUMP_1 0x4C

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#define WM8994_CLASS_W_1 0x51

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#define WM8994_DC_SERVO_1 0x54

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#define WM8994_DC_SERVO_2 0x55

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#define WM8994_DC_SERVO_4 0x57

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#define WM8994_DC_SERVO_READBACK 0x58

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#define WM8994_ANALOGUE_HP_1 0x60

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#define WM8994_CHIP_REVISION 0x100

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#define WM8994_CONTROL_INTERFACE 0x101

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#define WM8994_WRITE_SEQUENCER_CTRL_1 0x110

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#define WM8994_WRITE_SEQUENCER_CTRL_2 0x111

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#define WM8994_AIF1_CLOCKING_1 0x200

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#define WM8994_AIF1_CLOCKING_2 0x201

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#define WM8994_AIF2_CLOCKING_1 0x204

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#define WM8994_AIF2_CLOCKING_2 0x205

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#define WM8994_CLOCKING_1 0x208

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#define WM8994_CLOCKING_2 0x209

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#define WM8994_AIF1_RATE 0x210

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#define WM8994_AIF2_RATE 0x211

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#define WM8994_RATE_STATUS 0x212

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#define WM8994_FLL1_CONTROL_1 0x220

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#define WM8994_FLL1_CONTROL_2 0x221

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#define WM8994_FLL1_CONTROL_3 0x222

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#define WM8994_FLL1_CONTROL_4 0x223

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#define WM8994_FLL1_CONTROL_5 0x224

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#define WM8994_FLL2_CONTROL_1 0x240

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#define WM8994_FLL2_CONTROL_2 0x241

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#define WM8994_FLL2_CONTROL_3 0x242

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#define WM8994_FLL2_CONTROL_4 0x243

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#define WM8994_FLL2_CONTROL_5 0x244

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#define WM8994_AIF1_CONTROL_1 0x300

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#define WM8994_AIF1_CONTROL_2 0x301

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#define WM8994_AIF1_MASTER_SLAVE 0x302

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#define WM8994_AIF1_BCLK 0x303

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#define WM8994_AIF1ADC_LRCLK 0x304

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#define WM8994_AIF1DAC_LRCLK 0x305

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#define WM8994_AIF1DAC_DATA 0x306

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#define WM8994_AIF1ADC_DATA 0x307

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#define WM8994_AIF2_CONTROL_1 0x310

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#define WM8994_AIF2_CONTROL_2 0x311

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#define WM8994_AIF2_MASTER_SLAVE 0x312

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#define WM8994_AIF2_BCLK 0x313

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#define WM8994_AIF2ADC_LRCLK 0x314

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#define WM8994_AIF2DAC_LRCLK 0x315

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#define WM8994_AIF2DAC_DATA 0x316

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#define WM8994_AIF2ADC_DATA 0x317

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[diff] [blame]

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#define WM8958_AIF3_CONTROL_1 0x320

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#define WM8958_AIF3_CONTROL_2 0x321

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#define WM8958_AIF3DAC_DATA 0x322

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#define WM8958_AIF3ADC_DATA 0x323

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1c4d3b70

2010-01-29 18:20:28 +0000

[diff] [blame]

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#define WM8994_AIF1_ADC1_LEFT_VOLUME 0x400

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#define WM8994_AIF1_ADC1_RIGHT_VOLUME 0x401

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#define WM8994_AIF1_DAC1_LEFT_VOLUME 0x402

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#define WM8994_AIF1_DAC1_RIGHT_VOLUME 0x403

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#define WM8994_AIF1_ADC2_LEFT_VOLUME 0x404

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#define WM8994_AIF1_ADC2_RIGHT_VOLUME 0x405

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#define WM8994_AIF1_DAC2_LEFT_VOLUME 0x406

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#define WM8994_AIF1_DAC2_RIGHT_VOLUME 0x407

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#define WM8994_AIF1_ADC1_FILTERS 0x410

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#define WM8994_AIF1_ADC2_FILTERS 0x411

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#define WM8994_AIF1_DAC1_FILTERS_1 0x420

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#define WM8994_AIF1_DAC1_FILTERS_2 0x421

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#define WM8994_AIF1_DAC2_FILTERS_1 0x422

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#define WM8994_AIF1_DAC2_FILTERS_2 0x423

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#define WM8994_AIF1_DRC1_1 0x440

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#define WM8994_AIF1_DRC1_2 0x441

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#define WM8994_AIF1_DRC1_3 0x442

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#define WM8994_AIF1_DRC1_4 0x443

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#define WM8994_AIF1_DRC1_5 0x444

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#define WM8994_AIF1_DRC2_1 0x450

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#define WM8994_AIF1_DRC2_2 0x451

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#define WM8994_AIF1_DRC2_3 0x452

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#define WM8994_AIF1_DRC2_4 0x453

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#define WM8994_AIF1_DRC2_5 0x454

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#define WM8994_AIF1_DAC1_EQ_GAINS_1 0x480

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#define WM8994_AIF1_DAC1_EQ_GAINS_2 0x481

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#define WM8994_AIF1_DAC1_EQ_BAND_1_A 0x482

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#define WM8994_AIF1_DAC1_EQ_BAND_1_B 0x483

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#define WM8994_AIF1_DAC1_EQ_BAND_1_PG 0x484

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#define WM8994_AIF1_DAC1_EQ_BAND_2_A 0x485

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#define WM8994_AIF1_DAC1_EQ_BAND_2_B 0x486

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#define WM8994_AIF1_DAC1_EQ_BAND_2_C 0x487

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#define WM8994_AIF1_DAC1_EQ_BAND_2_PG 0x488

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#define WM8994_AIF1_DAC1_EQ_BAND_3_A 0x489

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#define WM8994_AIF1_DAC1_EQ_BAND_3_B 0x48A

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#define WM8994_AIF1_DAC1_EQ_BAND_3_C 0x48B

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#define WM8994_AIF1_DAC1_EQ_BAND_3_PG 0x48C

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#define WM8994_AIF1_DAC1_EQ_BAND_4_A 0x48D

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#define WM8994_AIF1_DAC1_EQ_BAND_4_B 0x48E

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#define WM8994_AIF1_DAC1_EQ_BAND_4_C 0x48F

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#define WM8994_AIF1_DAC1_EQ_BAND_4_PG 0x490

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#define WM8994_AIF1_DAC1_EQ_BAND_5_A 0x491

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#define WM8994_AIF1_DAC1_EQ_BAND_5_B 0x492

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#define WM8994_AIF1_DAC1_EQ_BAND_5_PG 0x493

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#define WM8994_AIF1_DAC2_EQ_GAINS_1 0x4A0

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#define WM8994_AIF1_DAC2_EQ_GAINS_2 0x4A1

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#define WM8994_AIF1_DAC2_EQ_BAND_1_A 0x4A2

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#define WM8994_AIF1_DAC2_EQ_BAND_1_B 0x4A3

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#define WM8994_AIF1_DAC2_EQ_BAND_1_PG 0x4A4

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#define WM8994_AIF1_DAC2_EQ_BAND_2_A 0x4A5

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#define WM8994_AIF1_DAC2_EQ_BAND_2_B 0x4A6

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#define WM8994_AIF1_DAC2_EQ_BAND_2_C 0x4A7

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#define WM8994_AIF1_DAC2_EQ_BAND_2_PG 0x4A8

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#define WM8994_AIF1_DAC2_EQ_BAND_3_A 0x4A9

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#define WM8994_AIF1_DAC2_EQ_BAND_3_B 0x4AA

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#define WM8994_AIF1_DAC2_EQ_BAND_3_C 0x4AB

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#define WM8994_AIF1_DAC2_EQ_BAND_3_PG 0x4AC

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#define WM8994_AIF1_DAC2_EQ_BAND_4_A 0x4AD

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#define WM8994_AIF1_DAC2_EQ_BAND_4_B 0x4AE

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#define WM8994_AIF1_DAC2_EQ_BAND_4_C 0x4AF

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#define WM8994_AIF1_DAC2_EQ_BAND_4_PG 0x4B0

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#define WM8994_AIF1_DAC2_EQ_BAND_5_A 0x4B1

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#define WM8994_AIF1_DAC2_EQ_BAND_5_B 0x4B2

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#define WM8994_AIF1_DAC2_EQ_BAND_5_PG 0x4B3

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#define WM8994_AIF2_ADC_LEFT_VOLUME 0x500

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#define WM8994_AIF2_ADC_RIGHT_VOLUME 0x501

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#define WM8994_AIF2_DAC_LEFT_VOLUME 0x502

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#define WM8994_AIF2_DAC_RIGHT_VOLUME 0x503

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#define WM8994_AIF2_ADC_FILTERS 0x510

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#define WM8994_AIF2_DAC_FILTERS_1 0x520

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#define WM8994_AIF2_DAC_FILTERS_2 0x521

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#define WM8994_AIF2_DRC_1 0x540

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#define WM8994_AIF2_DRC_2 0x541

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#define WM8994_AIF2_DRC_3 0x542

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#define WM8994_AIF2_DRC_4 0x543

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#define WM8994_AIF2_DRC_5 0x544

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#define WM8994_AIF2_EQ_GAINS_1 0x580

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#define WM8994_AIF2_EQ_GAINS_2 0x581

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#define WM8994_AIF2_EQ_BAND_1_A 0x582

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#define WM8994_AIF2_EQ_BAND_1_B 0x583

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#define WM8994_AIF2_EQ_BAND_1_PG 0x584

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#define WM8994_AIF2_EQ_BAND_2_A 0x585

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#define WM8994_AIF2_EQ_BAND_2_B 0x586

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#define WM8994_AIF2_EQ_BAND_2_C 0x587

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#define WM8994_AIF2_EQ_BAND_2_PG 0x588

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#define WM8994_AIF2_EQ_BAND_3_A 0x589

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#define WM8994_AIF2_EQ_BAND_3_B 0x58A

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#define WM8994_AIF2_EQ_BAND_3_C 0x58B

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#define WM8994_AIF2_EQ_BAND_3_PG 0x58C

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#define WM8994_AIF2_EQ_BAND_4_A 0x58D

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#define WM8994_AIF2_EQ_BAND_4_B 0x58E

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#define WM8994_AIF2_EQ_BAND_4_C 0x58F

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#define WM8994_AIF2_EQ_BAND_4_PG 0x590

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#define WM8994_AIF2_EQ_BAND_5_A 0x591

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#define WM8994_AIF2_EQ_BAND_5_B 0x592

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#define WM8994_AIF2_EQ_BAND_5_PG 0x593

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#define WM8994_DAC1_MIXER_VOLUMES 0x600

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#define WM8994_DAC1_LEFT_MIXER_ROUTING 0x601

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#define WM8994_DAC1_RIGHT_MIXER_ROUTING 0x602

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#define WM8994_DAC2_MIXER_VOLUMES 0x603

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#define WM8994_DAC2_LEFT_MIXER_ROUTING 0x604

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#define WM8994_DAC2_RIGHT_MIXER_ROUTING 0x605

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#define WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING 0x606

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#define WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING 0x607

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#define WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING 0x608

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#define WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING 0x609

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#define WM8994_DAC1_LEFT_VOLUME 0x610

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#define WM8994_DAC1_RIGHT_VOLUME 0x611

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#define WM8994_DAC2_LEFT_VOLUME 0x612

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#define WM8994_DAC2_RIGHT_VOLUME 0x613

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#define WM8994_DAC_SOFTMUTE 0x614

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#define WM8994_OVERSAMPLING 0x620

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#define WM8994_SIDETONE 0x621

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#define WM8994_GPIO_1 0x700

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#define WM8994_GPIO_2 0x701

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#define WM8994_GPIO_3 0x702

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#define WM8994_GPIO_4 0x703

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#define WM8994_GPIO_5 0x704

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#define WM8994_GPIO_6 0x705

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#define WM8994_GPIO_7 0x706

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#define WM8994_GPIO_8 0x707

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#define WM8994_GPIO_9 0x708

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#define WM8994_GPIO_10 0x709

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#define WM8994_GPIO_11 0x70A

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#define WM8994_PULL_CONTROL_1 0x720

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#define WM8994_PULL_CONTROL_2 0x721

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#define WM8994_INTERRUPT_STATUS_1 0x730

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#define WM8994_INTERRUPT_STATUS_2 0x731

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#define WM8994_INTERRUPT_RAW_STATUS_2 0x732

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#define WM8994_INTERRUPT_STATUS_1_MASK 0x738

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#define WM8994_INTERRUPT_STATUS_2_MASK 0x739

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#define WM8994_INTERRUPT_CONTROL 0x740

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#define WM8994_IRQ_DEBOUNCE 0x748

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d6addcc

2010-11-26 15:21:08 +0000

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#define WM8958_DSP2_PROGRAM 0x900

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#define WM8958_DSP2_CONFIG 0x901

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#define WM8958_DSP2_MAGICNUM 0xA00

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#define WM8958_DSP2_RELEASEYEAR 0xA01

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#define WM8958_DSP2_RELEASEMONTHDAY 0xA02

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#define WM8958_DSP2_RELEASETIME 0xA03

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#define WM8958_DSP2_VERMAJMIN 0xA04

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#define WM8958_DSP2_VERBUILD 0xA05

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#define WM8958_DSP2_EXECCONTROL 0xA0D

Mark Brown

1c4d3b70

2010-01-29 18:20:28 +0000

[diff] [blame]

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#define WM8994_WRITE_SEQUENCER_0 0x3000

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#define WM8994_WRITE_SEQUENCER_1 0x3001

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#define WM8994_WRITE_SEQUENCER_2 0x3002

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#define WM8994_WRITE_SEQUENCER_3 0x3003

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#define WM8994_WRITE_SEQUENCER_4 0x3004

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#define WM8994_WRITE_SEQUENCER_5 0x3005

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#define WM8994_WRITE_SEQUENCER_6 0x3006

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#define WM8994_WRITE_SEQUENCER_7 0x3007

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#define WM8994_WRITE_SEQUENCER_8 0x3008

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#define WM8994_WRITE_SEQUENCER_9 0x3009

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#define WM8994_WRITE_SEQUENCER_10 0x300A

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#define WM8994_WRITE_SEQUENCER_11 0x300B

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#define WM8994_WRITE_SEQUENCER_12 0x300C

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#define WM8994_WRITE_SEQUENCER_13 0x300D

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#define WM8994_WRITE_SEQUENCER_14 0x300E

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#define WM8994_WRITE_SEQUENCER_15 0x300F

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#define WM8994_WRITE_SEQUENCER_16 0x3010

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#define WM8994_WRITE_SEQUENCER_17 0x3011

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#define WM8994_WRITE_SEQUENCER_18 0x3012

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#define WM8994_WRITE_SEQUENCER_19 0x3013

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#define WM8994_WRITE_SEQUENCER_20 0x3014

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#define WM8994_WRITE_SEQUENCER_21 0x3015

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#define WM8994_WRITE_SEQUENCER_22 0x3016

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#define WM8994_WRITE_SEQUENCER_23 0x3017

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#define WM8994_WRITE_SEQUENCER_24 0x3018

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#define WM8994_WRITE_SEQUENCER_25 0x3019

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#define WM8994_WRITE_SEQUENCER_26 0x301A

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#define WM8994_WRITE_SEQUENCER_27 0x301B

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#define WM8994_WRITE_SEQUENCER_28 0x301C

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#define WM8994_WRITE_SEQUENCER_29 0x301D

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#define WM8994_WRITE_SEQUENCER_30 0x301E

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#define WM8994_WRITE_SEQUENCER_31 0x301F

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#define WM8994_WRITE_SEQUENCER_32 0x3020

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#define WM8994_WRITE_SEQUENCER_33 0x3021

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#define WM8994_WRITE_SEQUENCER_34 0x3022

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#define WM8994_WRITE_SEQUENCER_35 0x3023

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#define WM8994_WRITE_SEQUENCER_36 0x3024

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#define WM8994_WRITE_SEQUENCER_37 0x3025

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#define WM8994_WRITE_SEQUENCER_38 0x3026

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#define WM8994_WRITE_SEQUENCER_39 0x3027

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#define WM8994_WRITE_SEQUENCER_40 0x3028

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#define WM8994_WRITE_SEQUENCER_41 0x3029

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#define WM8994_WRITE_SEQUENCER_42 0x302A

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#define WM8994_WRITE_SEQUENCER_43 0x302B

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#define WM8994_WRITE_SEQUENCER_44 0x302C

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#define WM8994_WRITE_SEQUENCER_45 0x302D

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#define WM8994_WRITE_SEQUENCER_46 0x302E

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#define WM8994_WRITE_SEQUENCER_47 0x302F

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#define WM8994_WRITE_SEQUENCER_48 0x3030

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#define WM8994_WRITE_SEQUENCER_49 0x3031

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#define WM8994_WRITE_SEQUENCER_50 0x3032

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#define WM8994_WRITE_SEQUENCER_51 0x3033

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#define WM8994_WRITE_SEQUENCER_52 0x3034

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#define WM8994_WRITE_SEQUENCER_53 0x3035

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#define WM8994_WRITE_SEQUENCER_54 0x3036

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#define WM8994_WRITE_SEQUENCER_55 0x3037

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#define WM8994_WRITE_SEQUENCER_56 0x3038

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#define WM8994_WRITE_SEQUENCER_57 0x3039

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#define WM8994_WRITE_SEQUENCER_58 0x303A

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#define WM8994_WRITE_SEQUENCER_59 0x303B

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#define WM8994_WRITE_SEQUENCER_60 0x303C

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#define WM8994_WRITE_SEQUENCER_61 0x303D

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#define WM8994_WRITE_SEQUENCER_62 0x303E

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#define WM8994_WRITE_SEQUENCER_63 0x303F

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#define WM8994_WRITE_SEQUENCER_64 0x3040

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#define WM8994_WRITE_SEQUENCER_65 0x3041

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#define WM8994_WRITE_SEQUENCER_66 0x3042

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#define WM8994_WRITE_SEQUENCER_67 0x3043

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#define WM8994_WRITE_SEQUENCER_68 0x3044

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#define WM8994_WRITE_SEQUENCER_69 0x3045

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#define WM8994_WRITE_SEQUENCER_70 0x3046

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#define WM8994_WRITE_SEQUENCER_71 0x3047

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#define WM8994_WRITE_SEQUENCER_72 0x3048

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#define WM8994_WRITE_SEQUENCER_73 0x3049

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#define WM8994_WRITE_SEQUENCER_74 0x304A

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#define WM8994_WRITE_SEQUENCER_75 0x304B

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#define WM8994_WRITE_SEQUENCER_76 0x304C

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#define WM8994_WRITE_SEQUENCER_77 0x304D

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#define WM8994_WRITE_SEQUENCER_78 0x304E

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#define WM8994_WRITE_SEQUENCER_79 0x304F

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#define WM8994_WRITE_SEQUENCER_80 0x3050

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#define WM8994_WRITE_SEQUENCER_81 0x3051

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#define WM8994_WRITE_SEQUENCER_82 0x3052

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#define WM8994_WRITE_SEQUENCER_83 0x3053

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#define WM8994_WRITE_SEQUENCER_84 0x3054

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#define WM8994_WRITE_SEQUENCER_85 0x3055

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#define WM8994_WRITE_SEQUENCER_86 0x3056

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#define WM8994_WRITE_SEQUENCER_87 0x3057

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#define WM8994_WRITE_SEQUENCER_88 0x3058

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#define WM8994_WRITE_SEQUENCER_89 0x3059

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#define WM8994_WRITE_SEQUENCER_90 0x305A

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#define WM8994_WRITE_SEQUENCER_91 0x305B

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#define WM8994_WRITE_SEQUENCER_92 0x305C

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#define WM8994_WRITE_SEQUENCER_93 0x305D

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#define WM8994_WRITE_SEQUENCER_94 0x305E

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#define WM8994_WRITE_SEQUENCER_95 0x305F

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#define WM8994_WRITE_SEQUENCER_96 0x3060

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#define WM8994_WRITE_SEQUENCER_97 0x3061

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#define WM8994_WRITE_SEQUENCER_98 0x3062

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#define WM8994_WRITE_SEQUENCER_99 0x3063

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#define WM8994_WRITE_SEQUENCER_100 0x3064

359

#define WM8994_WRITE_SEQUENCER_101 0x3065

360

#define WM8994_WRITE_SEQUENCER_102 0x3066

361

#define WM8994_WRITE_SEQUENCER_103 0x3067

362

#define WM8994_WRITE_SEQUENCER_104 0x3068

363

#define WM8994_WRITE_SEQUENCER_105 0x3069

364

#define WM8994_WRITE_SEQUENCER_106 0x306A

365

#define WM8994_WRITE_SEQUENCER_107 0x306B

366

#define WM8994_WRITE_SEQUENCER_108 0x306C

367

#define WM8994_WRITE_SEQUENCER_109 0x306D

368

#define WM8994_WRITE_SEQUENCER_110 0x306E

369

#define WM8994_WRITE_SEQUENCER_111 0x306F

370

#define WM8994_WRITE_SEQUENCER_112 0x3070

371

#define WM8994_WRITE_SEQUENCER_113 0x3071

372

#define WM8994_WRITE_SEQUENCER_114 0x3072

373

#define WM8994_WRITE_SEQUENCER_115 0x3073

374

#define WM8994_WRITE_SEQUENCER_116 0x3074

375

#define WM8994_WRITE_SEQUENCER_117 0x3075

376

#define WM8994_WRITE_SEQUENCER_118 0x3076

377

#define WM8994_WRITE_SEQUENCER_119 0x3077

378

#define WM8994_WRITE_SEQUENCER_120 0x3078

379

#define WM8994_WRITE_SEQUENCER_121 0x3079

380

#define WM8994_WRITE_SEQUENCER_122 0x307A

381

#define WM8994_WRITE_SEQUENCER_123 0x307B

382

#define WM8994_WRITE_SEQUENCER_124 0x307C

383

#define WM8994_WRITE_SEQUENCER_125 0x307D

384

#define WM8994_WRITE_SEQUENCER_126 0x307E

385

#define WM8994_WRITE_SEQUENCER_127 0x307F

386

#define WM8994_WRITE_SEQUENCER_128 0x3080

387

#define WM8994_WRITE_SEQUENCER_129 0x3081

388

#define WM8994_WRITE_SEQUENCER_130 0x3082

389

#define WM8994_WRITE_SEQUENCER_131 0x3083

390

#define WM8994_WRITE_SEQUENCER_132 0x3084

391

#define WM8994_WRITE_SEQUENCER_133 0x3085

392

#define WM8994_WRITE_SEQUENCER_134 0x3086

393

#define WM8994_WRITE_SEQUENCER_135 0x3087

394

#define WM8994_WRITE_SEQUENCER_136 0x3088

395

#define WM8994_WRITE_SEQUENCER_137 0x3089

396

#define WM8994_WRITE_SEQUENCER_138 0x308A

397

#define WM8994_WRITE_SEQUENCER_139 0x308B

398

#define WM8994_WRITE_SEQUENCER_140 0x308C

399

#define WM8994_WRITE_SEQUENCER_141 0x308D

400

#define WM8994_WRITE_SEQUENCER_142 0x308E

401

#define WM8994_WRITE_SEQUENCER_143 0x308F

402

#define WM8994_WRITE_SEQUENCER_144 0x3090

403

#define WM8994_WRITE_SEQUENCER_145 0x3091

404

#define WM8994_WRITE_SEQUENCER_146 0x3092

405

#define WM8994_WRITE_SEQUENCER_147 0x3093

406

#define WM8994_WRITE_SEQUENCER_148 0x3094

407

#define WM8994_WRITE_SEQUENCER_149 0x3095

408

#define WM8994_WRITE_SEQUENCER_150 0x3096

409

#define WM8994_WRITE_SEQUENCER_151 0x3097

410

#define WM8994_WRITE_SEQUENCER_152 0x3098

411

#define WM8994_WRITE_SEQUENCER_153 0x3099

412

#define WM8994_WRITE_SEQUENCER_154 0x309A

413

#define WM8994_WRITE_SEQUENCER_155 0x309B

414

#define WM8994_WRITE_SEQUENCER_156 0x309C

415

#define WM8994_WRITE_SEQUENCER_157 0x309D

416

#define WM8994_WRITE_SEQUENCER_158 0x309E

417

#define WM8994_WRITE_SEQUENCER_159 0x309F

418

#define WM8994_WRITE_SEQUENCER_160 0x30A0

419

#define WM8994_WRITE_SEQUENCER_161 0x30A1

420

#define WM8994_WRITE_SEQUENCER_162 0x30A2

421

#define WM8994_WRITE_SEQUENCER_163 0x30A3

422

#define WM8994_WRITE_SEQUENCER_164 0x30A4

423

#define WM8994_WRITE_SEQUENCER_165 0x30A5

424

#define WM8994_WRITE_SEQUENCER_166 0x30A6

425

#define WM8994_WRITE_SEQUENCER_167 0x30A7

426

#define WM8994_WRITE_SEQUENCER_168 0x30A8

427

#define WM8994_WRITE_SEQUENCER_169 0x30A9

428

#define WM8994_WRITE_SEQUENCER_170 0x30AA

429

#define WM8994_WRITE_SEQUENCER_171 0x30AB

430

#define WM8994_WRITE_SEQUENCER_172 0x30AC

431

#define WM8994_WRITE_SEQUENCER_173 0x30AD

432

#define WM8994_WRITE_SEQUENCER_174 0x30AE

433

#define WM8994_WRITE_SEQUENCER_175 0x30AF

434

#define WM8994_WRITE_SEQUENCER_176 0x30B0

435

#define WM8994_WRITE_SEQUENCER_177 0x30B1

436

#define WM8994_WRITE_SEQUENCER_178 0x30B2

437

#define WM8994_WRITE_SEQUENCER_179 0x30B3

438

#define WM8994_WRITE_SEQUENCER_180 0x30B4

439

#define WM8994_WRITE_SEQUENCER_181 0x30B5

440

#define WM8994_WRITE_SEQUENCER_182 0x30B6

441

#define WM8994_WRITE_SEQUENCER_183 0x30B7

442

#define WM8994_WRITE_SEQUENCER_184 0x30B8

443

#define WM8994_WRITE_SEQUENCER_185 0x30B9

444

#define WM8994_WRITE_SEQUENCER_186 0x30BA

445

#define WM8994_WRITE_SEQUENCER_187 0x30BB

446

#define WM8994_WRITE_SEQUENCER_188 0x30BC

447

#define WM8994_WRITE_SEQUENCER_189 0x30BD

448

#define WM8994_WRITE_SEQUENCER_190 0x30BE

449

#define WM8994_WRITE_SEQUENCER_191 0x30BF

450

#define WM8994_WRITE_SEQUENCER_192 0x30C0

451

#define WM8994_WRITE_SEQUENCER_193 0x30C1

452

#define WM8994_WRITE_SEQUENCER_194 0x30C2

453

#define WM8994_WRITE_SEQUENCER_195 0x30C3

454

#define WM8994_WRITE_SEQUENCER_196 0x30C4

455

#define WM8994_WRITE_SEQUENCER_197 0x30C5

456

#define WM8994_WRITE_SEQUENCER_198 0x30C6

457

#define WM8994_WRITE_SEQUENCER_199 0x30C7

458

#define WM8994_WRITE_SEQUENCER_200 0x30C8

459

#define WM8994_WRITE_SEQUENCER_201 0x30C9

460

#define WM8994_WRITE_SEQUENCER_202 0x30CA

461

#define WM8994_WRITE_SEQUENCER_203 0x30CB

462

#define WM8994_WRITE_SEQUENCER_204 0x30CC

463

#define WM8994_WRITE_SEQUENCER_205 0x30CD

464

#define WM8994_WRITE_SEQUENCER_206 0x30CE

465

#define WM8994_WRITE_SEQUENCER_207 0x30CF

466

#define WM8994_WRITE_SEQUENCER_208 0x30D0

467

#define WM8994_WRITE_SEQUENCER_209 0x30D1

468

#define WM8994_WRITE_SEQUENCER_210 0x30D2

469

#define WM8994_WRITE_SEQUENCER_211 0x30D3

470

#define WM8994_WRITE_SEQUENCER_212 0x30D4

471

#define WM8994_WRITE_SEQUENCER_213 0x30D5

472

#define WM8994_WRITE_SEQUENCER_214 0x30D6

473

#define WM8994_WRITE_SEQUENCER_215 0x30D7

474

#define WM8994_WRITE_SEQUENCER_216 0x30D8

475

#define WM8994_WRITE_SEQUENCER_217 0x30D9

476

#define WM8994_WRITE_SEQUENCER_218 0x30DA

477

#define WM8994_WRITE_SEQUENCER_219 0x30DB

478

#define WM8994_WRITE_SEQUENCER_220 0x30DC

479

#define WM8994_WRITE_SEQUENCER_221 0x30DD

480

#define WM8994_WRITE_SEQUENCER_222 0x30DE

481

#define WM8994_WRITE_SEQUENCER_223 0x30DF

482

#define WM8994_WRITE_SEQUENCER_224 0x30E0

483

#define WM8994_WRITE_SEQUENCER_225 0x30E1

484

#define WM8994_WRITE_SEQUENCER_226 0x30E2

485

#define WM8994_WRITE_SEQUENCER_227 0x30E3

486

#define WM8994_WRITE_SEQUENCER_228 0x30E4

487

#define WM8994_WRITE_SEQUENCER_229 0x30E5

488

#define WM8994_WRITE_SEQUENCER_230 0x30E6

489

#define WM8994_WRITE_SEQUENCER_231 0x30E7

490

#define WM8994_WRITE_SEQUENCER_232 0x30E8

491

#define WM8994_WRITE_SEQUENCER_233 0x30E9

492

#define WM8994_WRITE_SEQUENCER_234 0x30EA

493

#define WM8994_WRITE_SEQUENCER_235 0x30EB

494

#define WM8994_WRITE_SEQUENCER_236 0x30EC

495

#define WM8994_WRITE_SEQUENCER_237 0x30ED

496

#define WM8994_WRITE_SEQUENCER_238 0x30EE

497

#define WM8994_WRITE_SEQUENCER_239 0x30EF

498

#define WM8994_WRITE_SEQUENCER_240 0x30F0

499

#define WM8994_WRITE_SEQUENCER_241 0x30F1

500

#define WM8994_WRITE_SEQUENCER_242 0x30F2

501

#define WM8994_WRITE_SEQUENCER_243 0x30F3

502

#define WM8994_WRITE_SEQUENCER_244 0x30F4

503

#define WM8994_WRITE_SEQUENCER_245 0x30F5

504

#define WM8994_WRITE_SEQUENCER_246 0x30F6

505

#define WM8994_WRITE_SEQUENCER_247 0x30F7

506

#define WM8994_WRITE_SEQUENCER_248 0x30F8

507

#define WM8994_WRITE_SEQUENCER_249 0x30F9

508

#define WM8994_WRITE_SEQUENCER_250 0x30FA

509

#define WM8994_WRITE_SEQUENCER_251 0x30FB

510

#define WM8994_WRITE_SEQUENCER_252 0x30FC

511

#define WM8994_WRITE_SEQUENCER_253 0x30FD

512

#define WM8994_WRITE_SEQUENCER_254 0x30FE

513

#define WM8994_WRITE_SEQUENCER_255 0x30FF

514

#define WM8994_WRITE_SEQUENCER_256 0x3100

515

#define WM8994_WRITE_SEQUENCER_257 0x3101

516

#define WM8994_WRITE_SEQUENCER_258 0x3102

517

#define WM8994_WRITE_SEQUENCER_259 0x3103

518

#define WM8994_WRITE_SEQUENCER_260 0x3104

519

#define WM8994_WRITE_SEQUENCER_261 0x3105

520

#define WM8994_WRITE_SEQUENCER_262 0x3106

521

#define WM8994_WRITE_SEQUENCER_263 0x3107

522

#define WM8994_WRITE_SEQUENCER_264 0x3108

523

#define WM8994_WRITE_SEQUENCER_265 0x3109

524

#define WM8994_WRITE_SEQUENCER_266 0x310A

525

#define WM8994_WRITE_SEQUENCER_267 0x310B

526

#define WM8994_WRITE_SEQUENCER_268 0x310C

527

#define WM8994_WRITE_SEQUENCER_269 0x310D

528

#define WM8994_WRITE_SEQUENCER_270 0x310E

529

#define WM8994_WRITE_SEQUENCER_271 0x310F

530

#define WM8994_WRITE_SEQUENCER_272 0x3110

531

#define WM8994_WRITE_SEQUENCER_273 0x3111

532

#define WM8994_WRITE_SEQUENCER_274 0x3112

533

#define WM8994_WRITE_SEQUENCER_275 0x3113

534

#define WM8994_WRITE_SEQUENCER_276 0x3114

535

#define WM8994_WRITE_SEQUENCER_277 0x3115

536

#define WM8994_WRITE_SEQUENCER_278 0x3116

537

#define WM8994_WRITE_SEQUENCER_279 0x3117

538

#define WM8994_WRITE_SEQUENCER_280 0x3118

539

#define WM8994_WRITE_SEQUENCER_281 0x3119

540

#define WM8994_WRITE_SEQUENCER_282 0x311A

541

#define WM8994_WRITE_SEQUENCER_283 0x311B

542

#define WM8994_WRITE_SEQUENCER_284 0x311C

543

#define WM8994_WRITE_SEQUENCER_285 0x311D

544

#define WM8994_WRITE_SEQUENCER_286 0x311E

545

#define WM8994_WRITE_SEQUENCER_287 0x311F

546

#define WM8994_WRITE_SEQUENCER_288 0x3120

547

#define WM8994_WRITE_SEQUENCER_289 0x3121

548

#define WM8994_WRITE_SEQUENCER_290 0x3122

549

#define WM8994_WRITE_SEQUENCER_291 0x3123

550

#define WM8994_WRITE_SEQUENCER_292 0x3124

551

#define WM8994_WRITE_SEQUENCER_293 0x3125

552

#define WM8994_WRITE_SEQUENCER_294 0x3126

553

#define WM8994_WRITE_SEQUENCER_295 0x3127

554

#define WM8994_WRITE_SEQUENCER_296 0x3128

555

#define WM8994_WRITE_SEQUENCER_297 0x3129

556

#define WM8994_WRITE_SEQUENCER_298 0x312A

557

#define WM8994_WRITE_SEQUENCER_299 0x312B

558

#define WM8994_WRITE_SEQUENCER_300 0x312C

559

#define WM8994_WRITE_SEQUENCER_301 0x312D

560

#define WM8994_WRITE_SEQUENCER_302 0x312E

561

#define WM8994_WRITE_SEQUENCER_303 0x312F

562

#define WM8994_WRITE_SEQUENCER_304 0x3130

563

#define WM8994_WRITE_SEQUENCER_305 0x3131

564

#define WM8994_WRITE_SEQUENCER_306 0x3132

565

#define WM8994_WRITE_SEQUENCER_307 0x3133

566

#define WM8994_WRITE_SEQUENCER_308 0x3134

567

#define WM8994_WRITE_SEQUENCER_309 0x3135

568

#define WM8994_WRITE_SEQUENCER_310 0x3136

569

#define WM8994_WRITE_SEQUENCER_311 0x3137

570

#define WM8994_WRITE_SEQUENCER_312 0x3138

571

#define WM8994_WRITE_SEQUENCER_313 0x3139

572

#define WM8994_WRITE_SEQUENCER_314 0x313A

573

#define WM8994_WRITE_SEQUENCER_315 0x313B

574

#define WM8994_WRITE_SEQUENCER_316 0x313C

575

#define WM8994_WRITE_SEQUENCER_317 0x313D

576

#define WM8994_WRITE_SEQUENCER_318 0x313E

577

#define WM8994_WRITE_SEQUENCER_319 0x313F

578

#define WM8994_WRITE_SEQUENCER_320 0x3140

579

#define WM8994_WRITE_SEQUENCER_321 0x3141

580

#define WM8994_WRITE_SEQUENCER_322 0x3142

581

#define WM8994_WRITE_SEQUENCER_323 0x3143

582

#define WM8994_WRITE_SEQUENCER_324 0x3144

583

#define WM8994_WRITE_SEQUENCER_325 0x3145

584

#define WM8994_WRITE_SEQUENCER_326 0x3146

585

#define WM8994_WRITE_SEQUENCER_327 0x3147

586

#define WM8994_WRITE_SEQUENCER_328 0x3148

587

#define WM8994_WRITE_SEQUENCER_329 0x3149

588

#define WM8994_WRITE_SEQUENCER_330 0x314A

589

#define WM8994_WRITE_SEQUENCER_331 0x314B

590

#define WM8994_WRITE_SEQUENCER_332 0x314C

591

#define WM8994_WRITE_SEQUENCER_333 0x314D

592

#define WM8994_WRITE_SEQUENCER_334 0x314E

593

#define WM8994_WRITE_SEQUENCER_335 0x314F

594

#define WM8994_WRITE_SEQUENCER_336 0x3150

595

#define WM8994_WRITE_SEQUENCER_337 0x3151

596

#define WM8994_WRITE_SEQUENCER_338 0x3152

597

#define WM8994_WRITE_SEQUENCER_339 0x3153

598

#define WM8994_WRITE_SEQUENCER_340 0x3154

599

#define WM8994_WRITE_SEQUENCER_341 0x3155

600

#define WM8994_WRITE_SEQUENCER_342 0x3156

601

#define WM8994_WRITE_SEQUENCER_343 0x3157

602

#define WM8994_WRITE_SEQUENCER_344 0x3158

603

#define WM8994_WRITE_SEQUENCER_345 0x3159

604

#define WM8994_WRITE_SEQUENCER_346 0x315A

605

#define WM8994_WRITE_SEQUENCER_347 0x315B

606

#define WM8994_WRITE_SEQUENCER_348 0x315C

607

#define WM8994_WRITE_SEQUENCER_349 0x315D

608

#define WM8994_WRITE_SEQUENCER_350 0x315E

609

#define WM8994_WRITE_SEQUENCER_351 0x315F

610

#define WM8994_WRITE_SEQUENCER_352 0x3160

611

#define WM8994_WRITE_SEQUENCER_353 0x3161

612

#define WM8994_WRITE_SEQUENCER_354 0x3162

613

#define WM8994_WRITE_SEQUENCER_355 0x3163

614

#define WM8994_WRITE_SEQUENCER_356 0x3164

615

#define WM8994_WRITE_SEQUENCER_357 0x3165

616

#define WM8994_WRITE_SEQUENCER_358 0x3166

617

#define WM8994_WRITE_SEQUENCER_359 0x3167

618

#define WM8994_WRITE_SEQUENCER_360 0x3168

619

#define WM8994_WRITE_SEQUENCER_361 0x3169

620

#define WM8994_WRITE_SEQUENCER_362 0x316A

621

#define WM8994_WRITE_SEQUENCER_363 0x316B

622

#define WM8994_WRITE_SEQUENCER_364 0x316C

623

#define WM8994_WRITE_SEQUENCER_365 0x316D

624

#define WM8994_WRITE_SEQUENCER_366 0x316E

625

#define WM8994_WRITE_SEQUENCER_367 0x316F

626

#define WM8994_WRITE_SEQUENCER_368 0x3170

627

#define WM8994_WRITE_SEQUENCER_369 0x3171

628

#define WM8994_WRITE_SEQUENCER_370 0x3172

629

#define WM8994_WRITE_SEQUENCER_371 0x3173

630

#define WM8994_WRITE_SEQUENCER_372 0x3174

631

#define WM8994_WRITE_SEQUENCER_373 0x3175

632

#define WM8994_WRITE_SEQUENCER_374 0x3176

633

#define WM8994_WRITE_SEQUENCER_375 0x3177

634

#define WM8994_WRITE_SEQUENCER_376 0x3178

635

#define WM8994_WRITE_SEQUENCER_377 0x3179

636

#define WM8994_WRITE_SEQUENCER_378 0x317A

637

#define WM8994_WRITE_SEQUENCER_379 0x317B

638

#define WM8994_WRITE_SEQUENCER_380 0x317C

639

#define WM8994_WRITE_SEQUENCER_381 0x317D

640

#define WM8994_WRITE_SEQUENCER_382 0x317E

641

#define WM8994_WRITE_SEQUENCER_383 0x317F

642

#define WM8994_WRITE_SEQUENCER_384 0x3180

643

#define WM8994_WRITE_SEQUENCER_385 0x3181

644

#define WM8994_WRITE_SEQUENCER_386 0x3182

645

#define WM8994_WRITE_SEQUENCER_387 0x3183

646

#define WM8994_WRITE_SEQUENCER_388 0x3184

647

#define WM8994_WRITE_SEQUENCER_389 0x3185

648

#define WM8994_WRITE_SEQUENCER_390 0x3186

649

#define WM8994_WRITE_SEQUENCER_391 0x3187

650

#define WM8994_WRITE_SEQUENCER_392 0x3188

651

#define WM8994_WRITE_SEQUENCER_393 0x3189

652

#define WM8994_WRITE_SEQUENCER_394 0x318A

653

#define WM8994_WRITE_SEQUENCER_395 0x318B

654

#define WM8994_WRITE_SEQUENCER_396 0x318C

655

#define WM8994_WRITE_SEQUENCER_397 0x318D

656

#define WM8994_WRITE_SEQUENCER_398 0x318E

657

#define WM8994_WRITE_SEQUENCER_399 0x318F

658

#define WM8994_WRITE_SEQUENCER_400 0x3190

659

#define WM8994_WRITE_SEQUENCER_401 0x3191

660

#define WM8994_WRITE_SEQUENCER_402 0x3192

661

#define WM8994_WRITE_SEQUENCER_403 0x3193

662

#define WM8994_WRITE_SEQUENCER_404 0x3194

663

#define WM8994_WRITE_SEQUENCER_405 0x3195

664

#define WM8994_WRITE_SEQUENCER_406 0x3196

665

#define WM8994_WRITE_SEQUENCER_407 0x3197

666

#define WM8994_WRITE_SEQUENCER_408 0x3198

667

#define WM8994_WRITE_SEQUENCER_409 0x3199

668

#define WM8994_WRITE_SEQUENCER_410 0x319A

669

#define WM8994_WRITE_SEQUENCER_411 0x319B

670

#define WM8994_WRITE_SEQUENCER_412 0x319C

671

#define WM8994_WRITE_SEQUENCER_413 0x319D

672

#define WM8994_WRITE_SEQUENCER_414 0x319E

673

#define WM8994_WRITE_SEQUENCER_415 0x319F

674

#define WM8994_WRITE_SEQUENCER_416 0x31A0

675

#define WM8994_WRITE_SEQUENCER_417 0x31A1

676

#define WM8994_WRITE_SEQUENCER_418 0x31A2

677

#define WM8994_WRITE_SEQUENCER_419 0x31A3

678

#define WM8994_WRITE_SEQUENCER_420 0x31A4

679

#define WM8994_WRITE_SEQUENCER_421 0x31A5

680

#define WM8994_WRITE_SEQUENCER_422 0x31A6

681

#define WM8994_WRITE_SEQUENCER_423 0x31A7

682

#define WM8994_WRITE_SEQUENCER_424 0x31A8

683

#define WM8994_WRITE_SEQUENCER_425 0x31A9

684

#define WM8994_WRITE_SEQUENCER_426 0x31AA

685

#define WM8994_WRITE_SEQUENCER_427 0x31AB

686

#define WM8994_WRITE_SEQUENCER_428 0x31AC

687

#define WM8994_WRITE_SEQUENCER_429 0x31AD

688

#define WM8994_WRITE_SEQUENCER_430 0x31AE

689

#define WM8994_WRITE_SEQUENCER_431 0x31AF

690

#define WM8994_WRITE_SEQUENCER_432 0x31B0

691

#define WM8994_WRITE_SEQUENCER_433 0x31B1

692

#define WM8994_WRITE_SEQUENCER_434 0x31B2

693

#define WM8994_WRITE_SEQUENCER_435 0x31B3

694

#define WM8994_WRITE_SEQUENCER_436 0x31B4

695

#define WM8994_WRITE_SEQUENCER_437 0x31B5

696

#define WM8994_WRITE_SEQUENCER_438 0x31B6

697

#define WM8994_WRITE_SEQUENCER_439 0x31B7

698

#define WM8994_WRITE_SEQUENCER_440 0x31B8

699

#define WM8994_WRITE_SEQUENCER_441 0x31B9

700

#define WM8994_WRITE_SEQUENCER_442 0x31BA

701

#define WM8994_WRITE_SEQUENCER_443 0x31BB

702

#define WM8994_WRITE_SEQUENCER_444 0x31BC

703

#define WM8994_WRITE_SEQUENCER_445 0x31BD

704

#define WM8994_WRITE_SEQUENCER_446 0x31BE

705

#define WM8994_WRITE_SEQUENCER_447 0x31BF

706

#define WM8994_WRITE_SEQUENCER_448 0x31C0

707

#define WM8994_WRITE_SEQUENCER_449 0x31C1

708

#define WM8994_WRITE_SEQUENCER_450 0x31C2

709

#define WM8994_WRITE_SEQUENCER_451 0x31C3

710

#define WM8994_WRITE_SEQUENCER_452 0x31C4

711

#define WM8994_WRITE_SEQUENCER_453 0x31C5

712

#define WM8994_WRITE_SEQUENCER_454 0x31C6

713

#define WM8994_WRITE_SEQUENCER_455 0x31C7

714

#define WM8994_WRITE_SEQUENCER_456 0x31C8

715

#define WM8994_WRITE_SEQUENCER_457 0x31C9

716

#define WM8994_WRITE_SEQUENCER_458 0x31CA

717

#define WM8994_WRITE_SEQUENCER_459 0x31CB

718

#define WM8994_WRITE_SEQUENCER_460 0x31CC

719

#define WM8994_WRITE_SEQUENCER_461 0x31CD

720

#define WM8994_WRITE_SEQUENCER_462 0x31CE

721

#define WM8994_WRITE_SEQUENCER_463 0x31CF

722

#define WM8994_WRITE_SEQUENCER_464 0x31D0

723

#define WM8994_WRITE_SEQUENCER_465 0x31D1

724

#define WM8994_WRITE_SEQUENCER_466 0x31D2

725

#define WM8994_WRITE_SEQUENCER_467 0x31D3

726

#define WM8994_WRITE_SEQUENCER_468 0x31D4

727

#define WM8994_WRITE_SEQUENCER_469 0x31D5

728

#define WM8994_WRITE_SEQUENCER_470 0x31D6

729

#define WM8994_WRITE_SEQUENCER_471 0x31D7

730

#define WM8994_WRITE_SEQUENCER_472 0x31D8

731

#define WM8994_WRITE_SEQUENCER_473 0x31D9

732

#define WM8994_WRITE_SEQUENCER_474 0x31DA

733

#define WM8994_WRITE_SEQUENCER_475 0x31DB

734

#define WM8994_WRITE_SEQUENCER_476 0x31DC

735

#define WM8994_WRITE_SEQUENCER_477 0x31DD

736

#define WM8994_WRITE_SEQUENCER_478 0x31DE

737

#define WM8994_WRITE_SEQUENCER_479 0x31DF

738

#define WM8994_WRITE_SEQUENCER_480 0x31E0

739

#define WM8994_WRITE_SEQUENCER_481 0x31E1

740

#define WM8994_WRITE_SEQUENCER_482 0x31E2

741

#define WM8994_WRITE_SEQUENCER_483 0x31E3

742

#define WM8994_WRITE_SEQUENCER_484 0x31E4

743

#define WM8994_WRITE_SEQUENCER_485 0x31E5

744

#define WM8994_WRITE_SEQUENCER_486 0x31E6

745

#define WM8994_WRITE_SEQUENCER_487 0x31E7

746

#define WM8994_WRITE_SEQUENCER_488 0x31E8

747

#define WM8994_WRITE_SEQUENCER_489 0x31E9

748

#define WM8994_WRITE_SEQUENCER_490 0x31EA

749

#define WM8994_WRITE_SEQUENCER_491 0x31EB

750

#define WM8994_WRITE_SEQUENCER_492 0x31EC

751

#define WM8994_WRITE_SEQUENCER_493 0x31ED

752

#define WM8994_WRITE_SEQUENCER_494 0x31EE

753

#define WM8994_WRITE_SEQUENCER_495 0x31EF

754

#define WM8994_WRITE_SEQUENCER_496 0x31F0

755

#define WM8994_WRITE_SEQUENCER_497 0x31F1

756

#define WM8994_WRITE_SEQUENCER_498 0x31F2

757

#define WM8994_WRITE_SEQUENCER_499 0x31F3

758

#define WM8994_WRITE_SEQUENCER_500 0x31F4

759

#define WM8994_WRITE_SEQUENCER_501 0x31F5

760

#define WM8994_WRITE_SEQUENCER_502 0x31F6

761

#define WM8994_WRITE_SEQUENCER_503 0x31F7

762

#define WM8994_WRITE_SEQUENCER_504 0x31F8

763

#define WM8994_WRITE_SEQUENCER_505 0x31F9

764

#define WM8994_WRITE_SEQUENCER_506 0x31FA

765

#define WM8994_WRITE_SEQUENCER_507 0x31FB

766

#define WM8994_WRITE_SEQUENCER_508 0x31FC

767

#define WM8994_WRITE_SEQUENCER_509 0x31FD

768

#define WM8994_WRITE_SEQUENCER_510 0x31FE

769

#define WM8994_WRITE_SEQUENCER_511 0x31FF

770

771

#define WM8994_REGISTER_COUNT 736

772

#define WM8994_MAX_REGISTER 0x31FF

773

#define WM8994_MAX_CACHED_REGISTER 0x749

/*

* Field Definitions.

*/

/*

* R0 (0x00) - Software Reset

781

*/

782

#define WM8994_SW_RESET_MASK 0xFFFF /* SW_RESET - [15:0] */

783

#define WM8994_SW_RESET_SHIFT 0 /* SW_RESET - [15:0] */

784

#define WM8994_SW_RESET_WIDTH 16 /* SW_RESET - [15:0] */

785

786

/*

787

* R1 (0x01) - Power Management (1)

788

*/

789

#define WM8994_SPKOUTR_ENA 0x2000 /* SPKOUTR_ENA */

790

#define WM8994_SPKOUTR_ENA_MASK 0x2000 /* SPKOUTR_ENA */

791

#define WM8994_SPKOUTR_ENA_SHIFT 13 /* SPKOUTR_ENA */

792

#define WM8994_SPKOUTR_ENA_WIDTH 1 /* SPKOUTR_ENA */

793

#define WM8994_SPKOUTL_ENA 0x1000 /* SPKOUTL_ENA */

794

#define WM8994_SPKOUTL_ENA_MASK 0x1000 /* SPKOUTL_ENA */

795

#define WM8994_SPKOUTL_ENA_SHIFT 12 /* SPKOUTL_ENA */

796

#define WM8994_SPKOUTL_ENA_WIDTH 1 /* SPKOUTL_ENA */

797

#define WM8994_HPOUT2_ENA 0x0800 /* HPOUT2_ENA */

798

#define WM8994_HPOUT2_ENA_MASK 0x0800 /* HPOUT2_ENA */

799

#define WM8994_HPOUT2_ENA_SHIFT 11 /* HPOUT2_ENA */

800

#define WM8994_HPOUT2_ENA_WIDTH 1 /* HPOUT2_ENA */

801

#define WM8994_HPOUT1L_ENA 0x0200 /* HPOUT1L_ENA */

802

#define WM8994_HPOUT1L_ENA_MASK 0x0200 /* HPOUT1L_ENA */

803

#define WM8994_HPOUT1L_ENA_SHIFT 9 /* HPOUT1L_ENA */

804

#define WM8994_HPOUT1L_ENA_WIDTH 1 /* HPOUT1L_ENA */

805

#define WM8994_HPOUT1R_ENA 0x0100 /* HPOUT1R_ENA */

806

#define WM8994_HPOUT1R_ENA_MASK 0x0100 /* HPOUT1R_ENA */

807

#define WM8994_HPOUT1R_ENA_SHIFT 8 /* HPOUT1R_ENA */

808

#define WM8994_HPOUT1R_ENA_WIDTH 1 /* HPOUT1R_ENA */

809

#define WM8994_MICB2_ENA 0x0020 /* MICB2_ENA */

810

#define WM8994_MICB2_ENA_MASK 0x0020 /* MICB2_ENA */

811

#define WM8994_MICB2_ENA_SHIFT 5 /* MICB2_ENA */

812

#define WM8994_MICB2_ENA_WIDTH 1 /* MICB2_ENA */

813

#define WM8994_MICB1_ENA 0x0010 /* MICB1_ENA */

814

#define WM8994_MICB1_ENA_MASK 0x0010 /* MICB1_ENA */

815

#define WM8994_MICB1_ENA_SHIFT 4 /* MICB1_ENA */

816

#define WM8994_MICB1_ENA_WIDTH 1 /* MICB1_ENA */

817

#define WM8994_VMID_SEL_MASK 0x0006 /* VMID_SEL - [2:1] */

818

#define WM8994_VMID_SEL_SHIFT 1 /* VMID_SEL - [2:1] */

819

#define WM8994_VMID_SEL_WIDTH 2 /* VMID_SEL - [2:1] */

820

#define WM8994_BIAS_ENA 0x0001 /* BIAS_ENA */

821

#define WM8994_BIAS_ENA_MASK 0x0001 /* BIAS_ENA */

822

#define WM8994_BIAS_ENA_SHIFT 0 /* BIAS_ENA */

823

#define WM8994_BIAS_ENA_WIDTH 1 /* BIAS_ENA */

824

825

/*

826

* R2 (0x02) - Power Management (2)

827

*/

828

#define WM8994_TSHUT_ENA 0x4000 /* TSHUT_ENA */

829

#define WM8994_TSHUT_ENA_MASK 0x4000 /* TSHUT_ENA */

830

#define WM8994_TSHUT_ENA_SHIFT 14 /* TSHUT_ENA */

831

#define WM8994_TSHUT_ENA_WIDTH 1 /* TSHUT_ENA */

832

#define WM8994_TSHUT_OPDIS 0x2000 /* TSHUT_OPDIS */

833

#define WM8994_TSHUT_OPDIS_MASK 0x2000 /* TSHUT_OPDIS */

834

#define WM8994_TSHUT_OPDIS_SHIFT 13 /* TSHUT_OPDIS */

835

#define WM8994_TSHUT_OPDIS_WIDTH 1 /* TSHUT_OPDIS */

836

#define WM8994_OPCLK_ENA 0x0800 /* OPCLK_ENA */

837

#define WM8994_OPCLK_ENA_MASK 0x0800 /* OPCLK_ENA */

838

#define WM8994_OPCLK_ENA_SHIFT 11 /* OPCLK_ENA */

839

#define WM8994_OPCLK_ENA_WIDTH 1 /* OPCLK_ENA */

840

#define WM8994_MIXINL_ENA 0x0200 /* MIXINL_ENA */

841

#define WM8994_MIXINL_ENA_MASK 0x0200 /* MIXINL_ENA */

842

#define WM8994_MIXINL_ENA_SHIFT 9 /* MIXINL_ENA */

843

#define WM8994_MIXINL_ENA_WIDTH 1 /* MIXINL_ENA */

844

#define WM8994_MIXINR_ENA 0x0100 /* MIXINR_ENA */

845

#define WM8994_MIXINR_ENA_MASK 0x0100 /* MIXINR_ENA */

846

#define WM8994_MIXINR_ENA_SHIFT 8 /* MIXINR_ENA */

847

#define WM8994_MIXINR_ENA_WIDTH 1 /* MIXINR_ENA */

848

#define WM8994_IN2L_ENA 0x0080 /* IN2L_ENA */

849

#define WM8994_IN2L_ENA_MASK 0x0080 /* IN2L_ENA */

850

#define WM8994_IN2L_ENA_SHIFT 7 /* IN2L_ENA */

851

#define WM8994_IN2L_ENA_WIDTH 1 /* IN2L_ENA */

852

#define WM8994_IN1L_ENA 0x0040 /* IN1L_ENA */

853

#define WM8994_IN1L_ENA_MASK 0x0040 /* IN1L_ENA */

854

#define WM8994_IN1L_ENA_SHIFT 6 /* IN1L_ENA */

855

#define WM8994_IN1L_ENA_WIDTH 1 /* IN1L_ENA */

856

#define WM8994_IN2R_ENA 0x0020 /* IN2R_ENA */

857

#define WM8994_IN2R_ENA_MASK 0x0020 /* IN2R_ENA */

858

#define WM8994_IN2R_ENA_SHIFT 5 /* IN2R_ENA */

859

#define WM8994_IN2R_ENA_WIDTH 1 /* IN2R_ENA */

860

#define WM8994_IN1R_ENA 0x0010 /* IN1R_ENA */

861

#define WM8994_IN1R_ENA_MASK 0x0010 /* IN1R_ENA */

862

#define WM8994_IN1R_ENA_SHIFT 4 /* IN1R_ENA */

863

#define WM8994_IN1R_ENA_WIDTH 1 /* IN1R_ENA */

864

865

/*

866

* R3 (0x03) - Power Management (3)

867

*/

868

#define WM8994_LINEOUT1N_ENA 0x2000 /* LINEOUT1N_ENA */

869

#define WM8994_LINEOUT1N_ENA_MASK 0x2000 /* LINEOUT1N_ENA */

870

#define WM8994_LINEOUT1N_ENA_SHIFT 13 /* LINEOUT1N_ENA */

871

#define WM8994_LINEOUT1N_ENA_WIDTH 1 /* LINEOUT1N_ENA */

872

#define WM8994_LINEOUT1P_ENA 0x1000 /* LINEOUT1P_ENA */

873

#define WM8994_LINEOUT1P_ENA_MASK 0x1000 /* LINEOUT1P_ENA */

874

#define WM8994_LINEOUT1P_ENA_SHIFT 12 /* LINEOUT1P_ENA */

875

#define WM8994_LINEOUT1P_ENA_WIDTH 1 /* LINEOUT1P_ENA */

876

#define WM8994_LINEOUT2N_ENA 0x0800 /* LINEOUT2N_ENA */

877

#define WM8994_LINEOUT2N_ENA_MASK 0x0800 /* LINEOUT2N_ENA */

878

#define WM8994_LINEOUT2N_ENA_SHIFT 11 /* LINEOUT2N_ENA */

879

#define WM8994_LINEOUT2N_ENA_WIDTH 1 /* LINEOUT2N_ENA */

880

#define WM8994_LINEOUT2P_ENA 0x0400 /* LINEOUT2P_ENA */

881

#define WM8994_LINEOUT2P_ENA_MASK 0x0400 /* LINEOUT2P_ENA */

882

#define WM8994_LINEOUT2P_ENA_SHIFT 10 /* LINEOUT2P_ENA */

883

#define WM8994_LINEOUT2P_ENA_WIDTH 1 /* LINEOUT2P_ENA */

884

#define WM8994_SPKRVOL_ENA 0x0200 /* SPKRVOL_ENA */

885

#define WM8994_SPKRVOL_ENA_MASK 0x0200 /* SPKRVOL_ENA */

886

#define WM8994_SPKRVOL_ENA_SHIFT 9 /* SPKRVOL_ENA */

887

#define WM8994_SPKRVOL_ENA_WIDTH 1 /* SPKRVOL_ENA */

888

#define WM8994_SPKLVOL_ENA 0x0100 /* SPKLVOL_ENA */

889

#define WM8994_SPKLVOL_ENA_MASK 0x0100 /* SPKLVOL_ENA */

890

#define WM8994_SPKLVOL_ENA_SHIFT 8 /* SPKLVOL_ENA */

891

#define WM8994_SPKLVOL_ENA_WIDTH 1 /* SPKLVOL_ENA */

892

#define WM8994_MIXOUTLVOL_ENA 0x0080 /* MIXOUTLVOL_ENA */

893

#define WM8994_MIXOUTLVOL_ENA_MASK 0x0080 /* MIXOUTLVOL_ENA */

894

#define WM8994_MIXOUTLVOL_ENA_SHIFT 7 /* MIXOUTLVOL_ENA */

895

#define WM8994_MIXOUTLVOL_ENA_WIDTH 1 /* MIXOUTLVOL_ENA */

896

#define WM8994_MIXOUTRVOL_ENA 0x0040 /* MIXOUTRVOL_ENA */

897

#define WM8994_MIXOUTRVOL_ENA_MASK 0x0040 /* MIXOUTRVOL_ENA */

898

#define WM8994_MIXOUTRVOL_ENA_SHIFT 6 /* MIXOUTRVOL_ENA */

899

#define WM8994_MIXOUTRVOL_ENA_WIDTH 1 /* MIXOUTRVOL_ENA */

900

#define WM8994_MIXOUTL_ENA 0x0020 /* MIXOUTL_ENA */

901

#define WM8994_MIXOUTL_ENA_MASK 0x0020 /* MIXOUTL_ENA */

902

#define WM8994_MIXOUTL_ENA_SHIFT 5 /* MIXOUTL_ENA */

903

#define WM8994_MIXOUTL_ENA_WIDTH 1 /* MIXOUTL_ENA */

904

#define WM8994_MIXOUTR_ENA 0x0010 /* MIXOUTR_ENA */

905

#define WM8994_MIXOUTR_ENA_MASK 0x0010 /* MIXOUTR_ENA */

906

#define WM8994_MIXOUTR_ENA_SHIFT 4 /* MIXOUTR_ENA */

907

#define WM8994_MIXOUTR_ENA_WIDTH 1 /* MIXOUTR_ENA */

908

909

/*

910

* R4 (0x04) - Power Management (4)

911

*/

912

#define WM8994_AIF2ADCL_ENA 0x2000 /* AIF2ADCL_ENA */

913

#define WM8994_AIF2ADCL_ENA_MASK 0x2000 /* AIF2ADCL_ENA */

914

#define WM8994_AIF2ADCL_ENA_SHIFT 13 /* AIF2ADCL_ENA */

915

#define WM8994_AIF2ADCL_ENA_WIDTH 1 /* AIF2ADCL_ENA */

916

#define WM8994_AIF2ADCR_ENA 0x1000 /* AIF2ADCR_ENA */

917

#define WM8994_AIF2ADCR_ENA_MASK 0x1000 /* AIF2ADCR_ENA */

918

#define WM8994_AIF2ADCR_ENA_SHIFT 12 /* AIF2ADCR_ENA */

919

#define WM8994_AIF2ADCR_ENA_WIDTH 1 /* AIF2ADCR_ENA */

920

#define WM8994_AIF1ADC2L_ENA 0x0800 /* AIF1ADC2L_ENA */

921

#define WM8994_AIF1ADC2L_ENA_MASK 0x0800 /* AIF1ADC2L_ENA */

922

#define WM8994_AIF1ADC2L_ENA_SHIFT 11 /* AIF1ADC2L_ENA */

923

#define WM8994_AIF1ADC2L_ENA_WIDTH 1 /* AIF1ADC2L_ENA */

924

#define WM8994_AIF1ADC2R_ENA 0x0400 /* AIF1ADC2R_ENA */

925

#define WM8994_AIF1ADC2R_ENA_MASK 0x0400 /* AIF1ADC2R_ENA */

926

#define WM8994_AIF1ADC2R_ENA_SHIFT 10 /* AIF1ADC2R_ENA */

927

#define WM8994_AIF1ADC2R_ENA_WIDTH 1 /* AIF1ADC2R_ENA */

928

#define WM8994_AIF1ADC1L_ENA 0x0200 /* AIF1ADC1L_ENA */

929

#define WM8994_AIF1ADC1L_ENA_MASK 0x0200 /* AIF1ADC1L_ENA */

930

#define WM8994_AIF1ADC1L_ENA_SHIFT 9 /* AIF1ADC1L_ENA */

931

#define WM8994_AIF1ADC1L_ENA_WIDTH 1 /* AIF1ADC1L_ENA */

932

#define WM8994_AIF1ADC1R_ENA 0x0100 /* AIF1ADC1R_ENA */

933

#define WM8994_AIF1ADC1R_ENA_MASK 0x0100 /* AIF1ADC1R_ENA */

934

#define WM8994_AIF1ADC1R_ENA_SHIFT 8 /* AIF1ADC1R_ENA */

935

#define WM8994_AIF1ADC1R_ENA_WIDTH 1 /* AIF1ADC1R_ENA */

936

#define WM8994_DMIC2L_ENA 0x0020 /* DMIC2L_ENA */

937

#define WM8994_DMIC2L_ENA_MASK 0x0020 /* DMIC2L_ENA */

938

#define WM8994_DMIC2L_ENA_SHIFT 5 /* DMIC2L_ENA */

939

#define WM8994_DMIC2L_ENA_WIDTH 1 /* DMIC2L_ENA */

940

#define WM8994_DMIC2R_ENA 0x0010 /* DMIC2R_ENA */

941

#define WM8994_DMIC2R_ENA_MASK 0x0010 /* DMIC2R_ENA */

942

#define WM8994_DMIC2R_ENA_SHIFT 4 /* DMIC2R_ENA */

943

#define WM8994_DMIC2R_ENA_WIDTH 1 /* DMIC2R_ENA */

944

#define WM8994_DMIC1L_ENA 0x0008 /* DMIC1L_ENA */

945

#define WM8994_DMIC1L_ENA_MASK 0x0008 /* DMIC1L_ENA */

946

#define WM8994_DMIC1L_ENA_SHIFT 3 /* DMIC1L_ENA */

947

#define WM8994_DMIC1L_ENA_WIDTH 1 /* DMIC1L_ENA */

948

#define WM8994_DMIC1R_ENA 0x0004 /* DMIC1R_ENA */

949

#define WM8994_DMIC1R_ENA_MASK 0x0004 /* DMIC1R_ENA */

950

#define WM8994_DMIC1R_ENA_SHIFT 2 /* DMIC1R_ENA */

951

#define WM8994_DMIC1R_ENA_WIDTH 1 /* DMIC1R_ENA */

952

#define WM8994_ADCL_ENA 0x0002 /* ADCL_ENA */

953

#define WM8994_ADCL_ENA_MASK 0x0002 /* ADCL_ENA */

954

#define WM8994_ADCL_ENA_SHIFT 1 /* ADCL_ENA */

955

#define WM8994_ADCL_ENA_WIDTH 1 /* ADCL_ENA */

956

#define WM8994_ADCR_ENA 0x0001 /* ADCR_ENA */

957

#define WM8994_ADCR_ENA_MASK 0x0001 /* ADCR_ENA */

958

#define WM8994_ADCR_ENA_SHIFT 0 /* ADCR_ENA */

959

#define WM8994_ADCR_ENA_WIDTH 1 /* ADCR_ENA */

960

961

/*

962

* R5 (0x05) - Power Management (5)

963

*/

964

#define WM8994_AIF2DACL_ENA 0x2000 /* AIF2DACL_ENA */

965

#define WM8994_AIF2DACL_ENA_MASK 0x2000 /* AIF2DACL_ENA */

966

#define WM8994_AIF2DACL_ENA_SHIFT 13 /* AIF2DACL_ENA */

967

#define WM8994_AIF2DACL_ENA_WIDTH 1 /* AIF2DACL_ENA */

968

#define WM8994_AIF2DACR_ENA 0x1000 /* AIF2DACR_ENA */

969

#define WM8994_AIF2DACR_ENA_MASK 0x1000 /* AIF2DACR_ENA */

970

#define WM8994_AIF2DACR_ENA_SHIFT 12 /* AIF2DACR_ENA */

971

#define WM8994_AIF2DACR_ENA_WIDTH 1 /* AIF2DACR_ENA */

972

#define WM8994_AIF1DAC2L_ENA 0x0800 /* AIF1DAC2L_ENA */

973

#define WM8994_AIF1DAC2L_ENA_MASK 0x0800 /* AIF1DAC2L_ENA */

974

#define WM8994_AIF1DAC2L_ENA_SHIFT 11 /* AIF1DAC2L_ENA */

975

#define WM8994_AIF1DAC2L_ENA_WIDTH 1 /* AIF1DAC2L_ENA */

976

#define WM8994_AIF1DAC2R_ENA 0x0400 /* AIF1DAC2R_ENA */

977

#define WM8994_AIF1DAC2R_ENA_MASK 0x0400 /* AIF1DAC2R_ENA */

978

#define WM8994_AIF1DAC2R_ENA_SHIFT 10 /* AIF1DAC2R_ENA */

979

#define WM8994_AIF1DAC2R_ENA_WIDTH 1 /* AIF1DAC2R_ENA */

980

#define WM8994_AIF1DAC1L_ENA 0x0200 /* AIF1DAC1L_ENA */

981

#define WM8994_AIF1DAC1L_ENA_MASK 0x0200 /* AIF1DAC1L_ENA */

982

#define WM8994_AIF1DAC1L_ENA_SHIFT 9 /* AIF1DAC1L_ENA */

983

#define WM8994_AIF1DAC1L_ENA_WIDTH 1 /* AIF1DAC1L_ENA */

984

#define WM8994_AIF1DAC1R_ENA 0x0100 /* AIF1DAC1R_ENA */

985

#define WM8994_AIF1DAC1R_ENA_MASK 0x0100 /* AIF1DAC1R_ENA */

986

#define WM8994_AIF1DAC1R_ENA_SHIFT 8 /* AIF1DAC1R_ENA */

987

#define WM8994_AIF1DAC1R_ENA_WIDTH 1 /* AIF1DAC1R_ENA */

988

#define WM8994_DAC2L_ENA 0x0008 /* DAC2L_ENA */

989

#define WM8994_DAC2L_ENA_MASK 0x0008 /* DAC2L_ENA */

990

#define WM8994_DAC2L_ENA_SHIFT 3 /* DAC2L_ENA */

991

#define WM8994_DAC2L_ENA_WIDTH 1 /* DAC2L_ENA */

992

#define WM8994_DAC2R_ENA 0x0004 /* DAC2R_ENA */

993

#define WM8994_DAC2R_ENA_MASK 0x0004 /* DAC2R_ENA */

994

#define WM8994_DAC2R_ENA_SHIFT 2 /* DAC2R_ENA */

995

#define WM8994_DAC2R_ENA_WIDTH 1 /* DAC2R_ENA */

996

#define WM8994_DAC1L_ENA 0x0002 /* DAC1L_ENA */

997

#define WM8994_DAC1L_ENA_MASK 0x0002 /* DAC1L_ENA */

998

#define WM8994_DAC1L_ENA_SHIFT 1 /* DAC1L_ENA */

999

#define WM8994_DAC1L_ENA_WIDTH 1 /* DAC1L_ENA */

1000

#define WM8994_DAC1R_ENA 0x0001 /* DAC1R_ENA */

1001

#define WM8994_DAC1R_ENA_MASK 0x0001 /* DAC1R_ENA */

1002

#define WM8994_DAC1R_ENA_SHIFT 0 /* DAC1R_ENA */

1003

#define WM8994_DAC1R_ENA_WIDTH 1 /* DAC1R_ENA */

1004

1005

/*

1006

* R6 (0x06) - Power Management (6)

1007

*/

Mark Brown

c4431df

2010-11-26 15:21:07 +0000

[diff] [blame]

1008

#define WM8958_AIF3ADC_SRC_MASK 0x0600 /* AIF3ADC_SRC - [10:9] */

1009

#define WM8958_AIF3ADC_SRC_SHIFT 9 /* AIF3ADC_SRC - [10:9] */

1010

#define WM8958_AIF3ADC_SRC_WIDTH 2 /* AIF3ADC_SRC - [10:9] */

1011

#define WM8958_AIF2DAC_SRC_MASK 0x0180 /* AIF2DAC_SRC - [8:7] */

1012

#define WM8958_AIF2DAC_SRC_SHIFT 7 /* AIF2DAC_SRC - [8:7] */

1013

#define WM8958_AIF2DAC_SRC_WIDTH 2 /* AIF2DAC_SRC - [8:7] */

Mark Brown

1c4d3b70

2010-01-29 18:20:28 +0000

[diff] [blame]

1014

#define WM8994_AIF3_TRI 0x0020 /* AIF3_TRI */

1015

#define WM8994_AIF3_TRI_MASK 0x0020 /* AIF3_TRI */

1016

#define WM8994_AIF3_TRI_SHIFT 5 /* AIF3_TRI */

1017

#define WM8994_AIF3_TRI_WIDTH 1 /* AIF3_TRI */

1018

#define WM8994_AIF3_ADCDAT_SRC_MASK 0x0018 /* AIF3_ADCDAT_SRC - [4:3] */

1019

#define WM8994_AIF3_ADCDAT_SRC_SHIFT 3 /* AIF3_ADCDAT_SRC - [4:3] */

1020

#define WM8994_AIF3_ADCDAT_SRC_WIDTH 2 /* AIF3_ADCDAT_SRC - [4:3] */

1021

#define WM8994_AIF2_ADCDAT_SRC 0x0004 /* AIF2_ADCDAT_SRC */

1022

#define WM8994_AIF2_ADCDAT_SRC_MASK 0x0004 /* AIF2_ADCDAT_SRC */

1023

#define WM8994_AIF2_ADCDAT_SRC_SHIFT 2 /* AIF2_ADCDAT_SRC */

1024

#define WM8994_AIF2_ADCDAT_SRC_WIDTH 1 /* AIF2_ADCDAT_SRC */

1025

#define WM8994_AIF2_DACDAT_SRC 0x0002 /* AIF2_DACDAT_SRC */

1026

#define WM8994_AIF2_DACDAT_SRC_MASK 0x0002 /* AIF2_DACDAT_SRC */

1027

#define WM8994_AIF2_DACDAT_SRC_SHIFT 1 /* AIF2_DACDAT_SRC */

1028

#define WM8994_AIF2_DACDAT_SRC_WIDTH 1 /* AIF2_DACDAT_SRC */

1029

#define WM8994_AIF1_DACDAT_SRC 0x0001 /* AIF1_DACDAT_SRC */

1030

#define WM8994_AIF1_DACDAT_SRC_MASK 0x0001 /* AIF1_DACDAT_SRC */

1031

#define WM8994_AIF1_DACDAT_SRC_SHIFT 0 /* AIF1_DACDAT_SRC */

1032

#define WM8994_AIF1_DACDAT_SRC_WIDTH 1 /* AIF1_DACDAT_SRC */

1033

1034

/*

1035

* R21 (0x15) - Input Mixer (1)

1036

*/

1037

#define WM8994_IN1RP_MIXINR_BOOST 0x0100 /* IN1RP_MIXINR_BOOST */

1038

#define WM8994_IN1RP_MIXINR_BOOST_MASK 0x0100 /* IN1RP_MIXINR_BOOST */

1039

#define WM8994_IN1RP_MIXINR_BOOST_SHIFT 8 /* IN1RP_MIXINR_BOOST */

1040

#define WM8994_IN1RP_MIXINR_BOOST_WIDTH 1 /* IN1RP_MIXINR_BOOST */

1041

#define WM8994_IN1LP_MIXINL_BOOST 0x0080 /* IN1LP_MIXINL_BOOST */

1042

#define WM8994_IN1LP_MIXINL_BOOST_MASK 0x0080 /* IN1LP_MIXINL_BOOST */

1043

#define WM8994_IN1LP_MIXINL_BOOST_SHIFT 7 /* IN1LP_MIXINL_BOOST */

1044

#define WM8994_IN1LP_MIXINL_BOOST_WIDTH 1 /* IN1LP_MIXINL_BOOST */

1045

#define WM8994_INPUTS_CLAMP 0x0040 /* INPUTS_CLAMP */

1046

#define WM8994_INPUTS_CLAMP_MASK 0x0040 /* INPUTS_CLAMP */

1047

#define WM8994_INPUTS_CLAMP_SHIFT 6 /* INPUTS_CLAMP */

1048

#define WM8994_INPUTS_CLAMP_WIDTH 1 /* INPUTS_CLAMP */

1049

1050

/*

1051

* R24 (0x18) - Left Line Input 1&2 Volume

1052

*/

1053

#define WM8994_IN1_VU 0x0100 /* IN1_VU */

1054

#define WM8994_IN1_VU_MASK 0x0100 /* IN1_VU */

1055

#define WM8994_IN1_VU_SHIFT 8 /* IN1_VU */

1056

#define WM8994_IN1_VU_WIDTH 1 /* IN1_VU */

1057

#define WM8994_IN1L_MUTE 0x0080 /* IN1L_MUTE */

1058

#define WM8994_IN1L_MUTE_MASK 0x0080 /* IN1L_MUTE */

1059

#define WM8994_IN1L_MUTE_SHIFT 7 /* IN1L_MUTE */

1060

#define WM8994_IN1L_MUTE_WIDTH 1 /* IN1L_MUTE */

1061

#define WM8994_IN1L_ZC 0x0040 /* IN1L_ZC */

1062

#define WM8994_IN1L_ZC_MASK 0x0040 /* IN1L_ZC */

1063

#define WM8994_IN1L_ZC_SHIFT 6 /* IN1L_ZC */

1064

#define WM8994_IN1L_ZC_WIDTH 1 /* IN1L_ZC */

1065

#define WM8994_IN1L_VOL_MASK 0x001F /* IN1L_VOL - [4:0] */

1066

#define WM8994_IN1L_VOL_SHIFT 0 /* IN1L_VOL - [4:0] */

1067

#define WM8994_IN1L_VOL_WIDTH 5 /* IN1L_VOL - [4:0] */

1068

1069

/*

1070

* R25 (0x19) - Left Line Input 3&4 Volume

1071

*/

1072

#define WM8994_IN2_VU 0x0100 /* IN2_VU */

1073

#define WM8994_IN2_VU_MASK 0x0100 /* IN2_VU */

1074

#define WM8994_IN2_VU_SHIFT 8 /* IN2_VU */

1075

#define WM8994_IN2_VU_WIDTH 1 /* IN2_VU */

1076

#define WM8994_IN2L_MUTE 0x0080 /* IN2L_MUTE */

1077

#define WM8994_IN2L_MUTE_MASK 0x0080 /* IN2L_MUTE */

1078

#define WM8994_IN2L_MUTE_SHIFT 7 /* IN2L_MUTE */

1079

#define WM8994_IN2L_MUTE_WIDTH 1 /* IN2L_MUTE */

1080

#define WM8994_IN2L_ZC 0x0040 /* IN2L_ZC */

1081

#define WM8994_IN2L_ZC_MASK 0x0040 /* IN2L_ZC */

1082

#define WM8994_IN2L_ZC_SHIFT 6 /* IN2L_ZC */

1083

#define WM8994_IN2L_ZC_WIDTH 1 /* IN2L_ZC */

1084

#define WM8994_IN2L_VOL_MASK 0x001F /* IN2L_VOL - [4:0] */

1085

#define WM8994_IN2L_VOL_SHIFT 0 /* IN2L_VOL - [4:0] */

1086

#define WM8994_IN2L_VOL_WIDTH 5 /* IN2L_VOL - [4:0] */

1087

1088

/*

1089

* R26 (0x1A) - Right Line Input 1&2 Volume

1090

*/

1091

#define WM8994_IN1_VU 0x0100 /* IN1_VU */

1092

#define WM8994_IN1_VU_MASK 0x0100 /* IN1_VU */

1093

#define WM8994_IN1_VU_SHIFT 8 /* IN1_VU */

1094

#define WM8994_IN1_VU_WIDTH 1 /* IN1_VU */

1095

#define WM8994_IN1R_MUTE 0x0080 /* IN1R_MUTE */

1096

#define WM8994_IN1R_MUTE_MASK 0x0080 /* IN1R_MUTE */

1097

#define WM8994_IN1R_MUTE_SHIFT 7 /* IN1R_MUTE */

1098

#define WM8994_IN1R_MUTE_WIDTH 1 /* IN1R_MUTE */

1099

#define WM8994_IN1R_ZC 0x0040 /* IN1R_ZC */

1100

#define WM8994_IN1R_ZC_MASK 0x0040 /* IN1R_ZC */

1101

#define WM8994_IN1R_ZC_SHIFT 6 /* IN1R_ZC */

1102

#define WM8994_IN1R_ZC_WIDTH 1 /* IN1R_ZC */

1103

#define WM8994_IN1R_VOL_MASK 0x001F /* IN1R_VOL - [4:0] */

1104

#define WM8994_IN1R_VOL_SHIFT 0 /* IN1R_VOL - [4:0] */

1105

#define WM8994_IN1R_VOL_WIDTH 5 /* IN1R_VOL - [4:0] */

1106

1107

/*

1108

* R27 (0x1B) - Right Line Input 3&4 Volume

1109

*/

1110

#define WM8994_IN2_VU 0x0100 /* IN2_VU */

1111

#define WM8994_IN2_VU_MASK 0x0100 /* IN2_VU */

1112

#define WM8994_IN2_VU_SHIFT 8 /* IN2_VU */

1113

#define WM8994_IN2_VU_WIDTH 1 /* IN2_VU */

1114

#define WM8994_IN2R_MUTE 0x0080 /* IN2R_MUTE */

1115

#define WM8994_IN2R_MUTE_MASK 0x0080 /* IN2R_MUTE */

1116

#define WM8994_IN2R_MUTE_SHIFT 7 /* IN2R_MUTE */

1117

#define WM8994_IN2R_MUTE_WIDTH 1 /* IN2R_MUTE */

1118

#define WM8994_IN2R_ZC 0x0040 /* IN2R_ZC */

1119

#define WM8994_IN2R_ZC_MASK 0x0040 /* IN2R_ZC */

1120

#define WM8994_IN2R_ZC_SHIFT 6 /* IN2R_ZC */

1121

#define WM8994_IN2R_ZC_WIDTH 1 /* IN2R_ZC */

1122

#define WM8994_IN2R_VOL_MASK 0x001F /* IN2R_VOL - [4:0] */

1123

#define WM8994_IN2R_VOL_SHIFT 0 /* IN2R_VOL - [4:0] */

1124

#define WM8994_IN2R_VOL_WIDTH 5 /* IN2R_VOL - [4:0] */

1125

1126

/*

1127

* R28 (0x1C) - Left Output Volume

1128

*/

1129

#define WM8994_HPOUT1_VU 0x0100 /* HPOUT1_VU */

1130

#define WM8994_HPOUT1_VU_MASK 0x0100 /* HPOUT1_VU */

1131

#define WM8994_HPOUT1_VU_SHIFT 8 /* HPOUT1_VU */

1132

#define WM8994_HPOUT1_VU_WIDTH 1 /* HPOUT1_VU */

1133

#define WM8994_HPOUT1L_ZC 0x0080 /* HPOUT1L_ZC */

1134

#define WM8994_HPOUT1L_ZC_MASK 0x0080 /* HPOUT1L_ZC */

1135

#define WM8994_HPOUT1L_ZC_SHIFT 7 /* HPOUT1L_ZC */

1136

#define WM8994_HPOUT1L_ZC_WIDTH 1 /* HPOUT1L_ZC */

1137

#define WM8994_HPOUT1L_MUTE_N 0x0040 /* HPOUT1L_MUTE_N */

1138

#define WM8994_HPOUT1L_MUTE_N_MASK 0x0040 /* HPOUT1L_MUTE_N */

1139

#define WM8994_HPOUT1L_MUTE_N_SHIFT 6 /* HPOUT1L_MUTE_N */

1140

#define WM8994_HPOUT1L_MUTE_N_WIDTH 1 /* HPOUT1L_MUTE_N */

1141

#define WM8994_HPOUT1L_VOL_MASK 0x003F /* HPOUT1L_VOL - [5:0] */

1142

#define WM8994_HPOUT1L_VOL_SHIFT 0 /* HPOUT1L_VOL - [5:0] */

1143

#define WM8994_HPOUT1L_VOL_WIDTH 6 /* HPOUT1L_VOL - [5:0] */

1144

1145

/*

1146

* R29 (0x1D) - Right Output Volume

1147

*/

1148

#define WM8994_HPOUT1_VU 0x0100 /* HPOUT1_VU */

1149

#define WM8994_HPOUT1_VU_MASK 0x0100 /* HPOUT1_VU */

1150

#define WM8994_HPOUT1_VU_SHIFT 8 /* HPOUT1_VU */

1151

#define WM8994_HPOUT1_VU_WIDTH 1 /* HPOUT1_VU */

1152

#define WM8994_HPOUT1R_ZC 0x0080 /* HPOUT1R_ZC */

1153

#define WM8994_HPOUT1R_ZC_MASK 0x0080 /* HPOUT1R_ZC */

1154

#define WM8994_HPOUT1R_ZC_SHIFT 7 /* HPOUT1R_ZC */

1155

#define WM8994_HPOUT1R_ZC_WIDTH 1 /* HPOUT1R_ZC */

1156

#define WM8994_HPOUT1R_MUTE_N 0x0040 /* HPOUT1R_MUTE_N */

1157

#define WM8994_HPOUT1R_MUTE_N_MASK 0x0040 /* HPOUT1R_MUTE_N */

1158

#define WM8994_HPOUT1R_MUTE_N_SHIFT 6 /* HPOUT1R_MUTE_N */

1159

#define WM8994_HPOUT1R_MUTE_N_WIDTH 1 /* HPOUT1R_MUTE_N */

1160

#define WM8994_HPOUT1R_VOL_MASK 0x003F /* HPOUT1R_VOL - [5:0] */

1161

#define WM8994_HPOUT1R_VOL_SHIFT 0 /* HPOUT1R_VOL - [5:0] */

1162

#define WM8994_HPOUT1R_VOL_WIDTH 6 /* HPOUT1R_VOL - [5:0] */

1163

1164

/*

1165

* R30 (0x1E) - Line Outputs Volume

1166

*/

1167

#define WM8994_LINEOUT1N_MUTE 0x0040 /* LINEOUT1N_MUTE */

1168

#define WM8994_LINEOUT1N_MUTE_MASK 0x0040 /* LINEOUT1N_MUTE */

1169

#define WM8994_LINEOUT1N_MUTE_SHIFT 6 /* LINEOUT1N_MUTE */

1170

#define WM8994_LINEOUT1N_MUTE_WIDTH 1 /* LINEOUT1N_MUTE */

1171

#define WM8994_LINEOUT1P_MUTE 0x0020 /* LINEOUT1P_MUTE */

1172

#define WM8994_LINEOUT1P_MUTE_MASK 0x0020 /* LINEOUT1P_MUTE */

1173

#define WM8994_LINEOUT1P_MUTE_SHIFT 5 /* LINEOUT1P_MUTE */

1174

#define WM8994_LINEOUT1P_MUTE_WIDTH 1 /* LINEOUT1P_MUTE */

1175

#define WM8994_LINEOUT1_VOL 0x0010 /* LINEOUT1_VOL */

1176

#define WM8994_LINEOUT1_VOL_MASK 0x0010 /* LINEOUT1_VOL */

1177

#define WM8994_LINEOUT1_VOL_SHIFT 4 /* LINEOUT1_VOL */

1178

#define WM8994_LINEOUT1_VOL_WIDTH 1 /* LINEOUT1_VOL */

1179

#define WM8994_LINEOUT2N_MUTE 0x0004 /* LINEOUT2N_MUTE */

1180

#define WM8994_LINEOUT2N_MUTE_MASK 0x0004 /* LINEOUT2N_MUTE */

1181

#define WM8994_LINEOUT2N_MUTE_SHIFT 2 /* LINEOUT2N_MUTE */

1182

#define WM8994_LINEOUT2N_MUTE_WIDTH 1 /* LINEOUT2N_MUTE */

1183

#define WM8994_LINEOUT2P_MUTE 0x0002 /* LINEOUT2P_MUTE */

1184

#define WM8994_LINEOUT2P_MUTE_MASK 0x0002 /* LINEOUT2P_MUTE */

1185

#define WM8994_LINEOUT2P_MUTE_SHIFT 1 /* LINEOUT2P_MUTE */

1186

#define WM8994_LINEOUT2P_MUTE_WIDTH 1 /* LINEOUT2P_MUTE */

1187

#define WM8994_LINEOUT2_VOL 0x0001 /* LINEOUT2_VOL */

1188

#define WM8994_LINEOUT2_VOL_MASK 0x0001 /* LINEOUT2_VOL */

1189

#define WM8994_LINEOUT2_VOL_SHIFT 0 /* LINEOUT2_VOL */

1190

#define WM8994_LINEOUT2_VOL_WIDTH 1 /* LINEOUT2_VOL */

1191

1192

/*

1193

* R31 (0x1F) - HPOUT2 Volume

1194

*/

1195

#define WM8994_HPOUT2_MUTE 0x0020 /* HPOUT2_MUTE */

1196

#define WM8994_HPOUT2_MUTE_MASK 0x0020 /* HPOUT2_MUTE */

1197

#define WM8994_HPOUT2_MUTE_SHIFT 5 /* HPOUT2_MUTE */

1198

#define WM8994_HPOUT2_MUTE_WIDTH 1 /* HPOUT2_MUTE */

1199

#define WM8994_HPOUT2_VOL 0x0010 /* HPOUT2_VOL */

1200

#define WM8994_HPOUT2_VOL_MASK 0x0010 /* HPOUT2_VOL */

1201

#define WM8994_HPOUT2_VOL_SHIFT 4 /* HPOUT2_VOL */

1202

#define WM8994_HPOUT2_VOL_WIDTH 1 /* HPOUT2_VOL */

1203

1204

/*

1205

* R32 (0x20) - Left OPGA Volume

1206

*/

1207

#define WM8994_MIXOUT_VU 0x0100 /* MIXOUT_VU */

1208

#define WM8994_MIXOUT_VU_MASK 0x0100 /* MIXOUT_VU */

1209

#define WM8994_MIXOUT_VU_SHIFT 8 /* MIXOUT_VU */

1210

#define WM8994_MIXOUT_VU_WIDTH 1 /* MIXOUT_VU */

1211

#define WM8994_MIXOUTL_ZC 0x0080 /* MIXOUTL_ZC */

1212

#define WM8994_MIXOUTL_ZC_MASK 0x0080 /* MIXOUTL_ZC */

1213

#define WM8994_MIXOUTL_ZC_SHIFT 7 /* MIXOUTL_ZC */

1214

#define WM8994_MIXOUTL_ZC_WIDTH 1 /* MIXOUTL_ZC */

1215

#define WM8994_MIXOUTL_MUTE_N 0x0040 /* MIXOUTL_MUTE_N */

1216

#define WM8994_MIXOUTL_MUTE_N_MASK 0x0040 /* MIXOUTL_MUTE_N */

1217

#define WM8994_MIXOUTL_MUTE_N_SHIFT 6 /* MIXOUTL_MUTE_N */

1218

#define WM8994_MIXOUTL_MUTE_N_WIDTH 1 /* MIXOUTL_MUTE_N */

1219

#define WM8994_MIXOUTL_VOL_MASK 0x003F /* MIXOUTL_VOL - [5:0] */

1220

#define WM8994_MIXOUTL_VOL_SHIFT 0 /* MIXOUTL_VOL - [5:0] */

1221

#define WM8994_MIXOUTL_VOL_WIDTH 6 /* MIXOUTL_VOL - [5:0] */

1222

1223

/*

1224

* R33 (0x21) - Right OPGA Volume

1225

*/

1226

#define WM8994_MIXOUT_VU 0x0100 /* MIXOUT_VU */

1227

#define WM8994_MIXOUT_VU_MASK 0x0100 /* MIXOUT_VU */

1228

#define WM8994_MIXOUT_VU_SHIFT 8 /* MIXOUT_VU */

1229

#define WM8994_MIXOUT_VU_WIDTH 1 /* MIXOUT_VU */

1230

#define WM8994_MIXOUTR_ZC 0x0080 /* MIXOUTR_ZC */

1231

#define WM8994_MIXOUTR_ZC_MASK 0x0080 /* MIXOUTR_ZC */

1232

#define WM8994_MIXOUTR_ZC_SHIFT 7 /* MIXOUTR_ZC */

1233

#define WM8994_MIXOUTR_ZC_WIDTH 1 /* MIXOUTR_ZC */

1234

#define WM8994_MIXOUTR_MUTE_N 0x0040 /* MIXOUTR_MUTE_N */

1235

#define WM8994_MIXOUTR_MUTE_N_MASK 0x0040 /* MIXOUTR_MUTE_N */

1236

#define WM8994_MIXOUTR_MUTE_N_SHIFT 6 /* MIXOUTR_MUTE_N */

1237

#define WM8994_MIXOUTR_MUTE_N_WIDTH 1 /* MIXOUTR_MUTE_N */

1238

#define WM8994_MIXOUTR_VOL_MASK 0x003F /* MIXOUTR_VOL - [5:0] */

1239

#define WM8994_MIXOUTR_VOL_SHIFT 0 /* MIXOUTR_VOL - [5:0] */

1240

#define WM8994_MIXOUTR_VOL_WIDTH 6 /* MIXOUTR_VOL - [5:0] */

1241

1242

/*

1243

* R34 (0x22) - SPKMIXL Attenuation

1244

*/

1245

#define WM8994_DAC2L_SPKMIXL_VOL 0x0040 /* DAC2L_SPKMIXL_VOL */

1246

#define WM8994_DAC2L_SPKMIXL_VOL_MASK 0x0040 /* DAC2L_SPKMIXL_VOL */

1247

#define WM8994_DAC2L_SPKMIXL_VOL_SHIFT 6 /* DAC2L_SPKMIXL_VOL */

1248

#define WM8994_DAC2L_SPKMIXL_VOL_WIDTH 1 /* DAC2L_SPKMIXL_VOL */

1249

#define WM8994_MIXINL_SPKMIXL_VOL 0x0020 /* MIXINL_SPKMIXL_VOL */

1250

#define WM8994_MIXINL_SPKMIXL_VOL_MASK 0x0020 /* MIXINL_SPKMIXL_VOL */

1251

#define WM8994_MIXINL_SPKMIXL_VOL_SHIFT 5 /* MIXINL_SPKMIXL_VOL */

1252

#define WM8994_MIXINL_SPKMIXL_VOL_WIDTH 1 /* MIXINL_SPKMIXL_VOL */

1253

#define WM8994_IN1LP_SPKMIXL_VOL 0x0010 /* IN1LP_SPKMIXL_VOL */

1254

#define WM8994_IN1LP_SPKMIXL_VOL_MASK 0x0010 /* IN1LP_SPKMIXL_VOL */

1255

#define WM8994_IN1LP_SPKMIXL_VOL_SHIFT 4 /* IN1LP_SPKMIXL_VOL */

1256

#define WM8994_IN1LP_SPKMIXL_VOL_WIDTH 1 /* IN1LP_SPKMIXL_VOL */

1257

#define WM8994_MIXOUTL_SPKMIXL_VOL 0x0008 /* MIXOUTL_SPKMIXL_VOL */

1258

#define WM8994_MIXOUTL_SPKMIXL_VOL_MASK 0x0008 /* MIXOUTL_SPKMIXL_VOL */

1259

#define WM8994_MIXOUTL_SPKMIXL_VOL_SHIFT 3 /* MIXOUTL_SPKMIXL_VOL */

1260

#define WM8994_MIXOUTL_SPKMIXL_VOL_WIDTH 1 /* MIXOUTL_SPKMIXL_VOL */

1261

#define WM8994_DAC1L_SPKMIXL_VOL 0x0004 /* DAC1L_SPKMIXL_VOL */

1262

#define WM8994_DAC1L_SPKMIXL_VOL_MASK 0x0004 /* DAC1L_SPKMIXL_VOL */

1263

#define WM8994_DAC1L_SPKMIXL_VOL_SHIFT 2 /* DAC1L_SPKMIXL_VOL */

1264

#define WM8994_DAC1L_SPKMIXL_VOL_WIDTH 1 /* DAC1L_SPKMIXL_VOL */

1265

#define WM8994_SPKMIXL_VOL_MASK 0x0003 /* SPKMIXL_VOL - [1:0] */

1266

#define WM8994_SPKMIXL_VOL_SHIFT 0 /* SPKMIXL_VOL - [1:0] */

1267

#define WM8994_SPKMIXL_VOL_WIDTH 2 /* SPKMIXL_VOL - [1:0] */

1268

1269

/*

1270

* R35 (0x23) - SPKMIXR Attenuation

1271

*/

1272

#define WM8994_SPKOUT_CLASSAB 0x0100 /* SPKOUT_CLASSAB */

1273

#define WM8994_SPKOUT_CLASSAB_MASK 0x0100 /* SPKOUT_CLASSAB */

1274

#define WM8994_SPKOUT_CLASSAB_SHIFT 8 /* SPKOUT_CLASSAB */

1275

#define WM8994_SPKOUT_CLASSAB_WIDTH 1 /* SPKOUT_CLASSAB */

1276

#define WM8994_DAC2R_SPKMIXR_VOL 0x0040 /* DAC2R_SPKMIXR_VOL */

1277

#define WM8994_DAC2R_SPKMIXR_VOL_MASK 0x0040 /* DAC2R_SPKMIXR_VOL */

1278

#define WM8994_DAC2R_SPKMIXR_VOL_SHIFT 6 /* DAC2R_SPKMIXR_VOL */

1279

#define WM8994_DAC2R_SPKMIXR_VOL_WIDTH 1 /* DAC2R_SPKMIXR_VOL */

1280

#define WM8994_MIXINR_SPKMIXR_VOL 0x0020 /* MIXINR_SPKMIXR_VOL */

1281

#define WM8994_MIXINR_SPKMIXR_VOL_MASK 0x0020 /* MIXINR_SPKMIXR_VOL */

1282

#define WM8994_MIXINR_SPKMIXR_VOL_SHIFT 5 /* MIXINR_SPKMIXR_VOL */

1283

#define WM8994_MIXINR_SPKMIXR_VOL_WIDTH 1 /* MIXINR_SPKMIXR_VOL */

1284

#define WM8994_IN1RP_SPKMIXR_VOL 0x0010 /* IN1RP_SPKMIXR_VOL */

1285

#define WM8994_IN1RP_SPKMIXR_VOL_MASK 0x0010 /* IN1RP_SPKMIXR_VOL */

1286

#define WM8994_IN1RP_SPKMIXR_VOL_SHIFT 4 /* IN1RP_SPKMIXR_VOL */

1287

#define WM8994_IN1RP_SPKMIXR_VOL_WIDTH 1 /* IN1RP_SPKMIXR_VOL */

1288

#define WM8994_MIXOUTR_SPKMIXR_VOL 0x0008 /* MIXOUTR_SPKMIXR_VOL */

1289

#define WM8994_MIXOUTR_SPKMIXR_VOL_MASK 0x0008 /* MIXOUTR_SPKMIXR_VOL */

1290

#define WM8994_MIXOUTR_SPKMIXR_VOL_SHIFT 3 /* MIXOUTR_SPKMIXR_VOL */

1291

#define WM8994_MIXOUTR_SPKMIXR_VOL_WIDTH 1 /* MIXOUTR_SPKMIXR_VOL */

1292

#define WM8994_DAC1R_SPKMIXR_VOL 0x0004 /* DAC1R_SPKMIXR_VOL */

1293

#define WM8994_DAC1R_SPKMIXR_VOL_MASK 0x0004 /* DAC1R_SPKMIXR_VOL */

1294

#define WM8994_DAC1R_SPKMIXR_VOL_SHIFT 2 /* DAC1R_SPKMIXR_VOL */

1295

#define WM8994_DAC1R_SPKMIXR_VOL_WIDTH 1 /* DAC1R_SPKMIXR_VOL */

1296

#define WM8994_SPKMIXR_VOL_MASK 0x0003 /* SPKMIXR_VOL - [1:0] */

1297

#define WM8994_SPKMIXR_VOL_SHIFT 0 /* SPKMIXR_VOL - [1:0] */

1298

#define WM8994_SPKMIXR_VOL_WIDTH 2 /* SPKMIXR_VOL - [1:0] */

1299

1300

/*

1301

* R36 (0x24) - SPKOUT Mixers

1302

*/

1303

#define WM8994_IN2LRP_TO_SPKOUTL 0x0020 /* IN2LRP_TO_SPKOUTL */

1304

#define WM8994_IN2LRP_TO_SPKOUTL_MASK 0x0020 /* IN2LRP_TO_SPKOUTL */

1305

#define WM8994_IN2LRP_TO_SPKOUTL_SHIFT 5 /* IN2LRP_TO_SPKOUTL */

1306

#define WM8994_IN2LRP_TO_SPKOUTL_WIDTH 1 /* IN2LRP_TO_SPKOUTL */

1307

#define WM8994_SPKMIXL_TO_SPKOUTL 0x0010 /* SPKMIXL_TO_SPKOUTL */

1308

#define WM8994_SPKMIXL_TO_SPKOUTL_MASK 0x0010 /* SPKMIXL_TO_SPKOUTL */

1309

#define WM8994_SPKMIXL_TO_SPKOUTL_SHIFT 4 /* SPKMIXL_TO_SPKOUTL */

1310

#define WM8994_SPKMIXL_TO_SPKOUTL_WIDTH 1 /* SPKMIXL_TO_SPKOUTL */

1311

#define WM8994_SPKMIXR_TO_SPKOUTL 0x0008 /* SPKMIXR_TO_SPKOUTL */

1312

#define WM8994_SPKMIXR_TO_SPKOUTL_MASK 0x0008 /* SPKMIXR_TO_SPKOUTL */

1313

#define WM8994_SPKMIXR_TO_SPKOUTL_SHIFT 3 /* SPKMIXR_TO_SPKOUTL */

1314

#define WM8994_SPKMIXR_TO_SPKOUTL_WIDTH 1 /* SPKMIXR_TO_SPKOUTL */

1315

#define WM8994_IN2LRP_TO_SPKOUTR 0x0004 /* IN2LRP_TO_SPKOUTR */

1316

#define WM8994_IN2LRP_TO_SPKOUTR_MASK 0x0004 /* IN2LRP_TO_SPKOUTR */

1317

#define WM8994_IN2LRP_TO_SPKOUTR_SHIFT 2 /* IN2LRP_TO_SPKOUTR */

1318

#define WM8994_IN2LRP_TO_SPKOUTR_WIDTH 1 /* IN2LRP_TO_SPKOUTR */

1319

#define WM8994_SPKMIXL_TO_SPKOUTR 0x0002 /* SPKMIXL_TO_SPKOUTR */

1320

#define WM8994_SPKMIXL_TO_SPKOUTR_MASK 0x0002 /* SPKMIXL_TO_SPKOUTR */

1321

#define WM8994_SPKMIXL_TO_SPKOUTR_SHIFT 1 /* SPKMIXL_TO_SPKOUTR */

1322

#define WM8994_SPKMIXL_TO_SPKOUTR_WIDTH 1 /* SPKMIXL_TO_SPKOUTR */

1323

#define WM8994_SPKMIXR_TO_SPKOUTR 0x0001 /* SPKMIXR_TO_SPKOUTR */

1324

#define WM8994_SPKMIXR_TO_SPKOUTR_MASK 0x0001 /* SPKMIXR_TO_SPKOUTR */

1325

#define WM8994_SPKMIXR_TO_SPKOUTR_SHIFT 0 /* SPKMIXR_TO_SPKOUTR */

1326

#define WM8994_SPKMIXR_TO_SPKOUTR_WIDTH 1 /* SPKMIXR_TO_SPKOUTR */

1327

1328

/*

1329

* R37 (0x25) - ClassD

1330

*/

1331

#define WM8994_SPKOUTL_BOOST_MASK 0x0038 /* SPKOUTL_BOOST - [5:3] */

1332

#define WM8994_SPKOUTL_BOOST_SHIFT 3 /* SPKOUTL_BOOST - [5:3] */

1333

#define WM8994_SPKOUTL_BOOST_WIDTH 3 /* SPKOUTL_BOOST - [5:3] */

1334

#define WM8994_SPKOUTR_BOOST_MASK 0x0007 /* SPKOUTR_BOOST - [2:0] */

1335

#define WM8994_SPKOUTR_BOOST_SHIFT 0 /* SPKOUTR_BOOST - [2:0] */

1336

#define WM8994_SPKOUTR_BOOST_WIDTH 3 /* SPKOUTR_BOOST - [2:0] */

1337

1338

/*

1339

* R38 (0x26) - Speaker Volume Left

1340

*/

1341

#define WM8994_SPKOUT_VU 0x0100 /* SPKOUT_VU */

1342

#define WM8994_SPKOUT_VU_MASK 0x0100 /* SPKOUT_VU */

1343

#define WM8994_SPKOUT_VU_SHIFT 8 /* SPKOUT_VU */

1344

#define WM8994_SPKOUT_VU_WIDTH 1 /* SPKOUT_VU */

1345

#define WM8994_SPKOUTL_ZC 0x0080 /* SPKOUTL_ZC */

1346

#define WM8994_SPKOUTL_ZC_MASK 0x0080 /* SPKOUTL_ZC */

1347

#define WM8994_SPKOUTL_ZC_SHIFT 7 /* SPKOUTL_ZC */

1348

#define WM8994_SPKOUTL_ZC_WIDTH 1 /* SPKOUTL_ZC */

1349

#define WM8994_SPKOUTL_MUTE_N 0x0040 /* SPKOUTL_MUTE_N */

1350

#define WM8994_SPKOUTL_MUTE_N_MASK 0x0040 /* SPKOUTL_MUTE_N */

1351

#define WM8994_SPKOUTL_MUTE_N_SHIFT 6 /* SPKOUTL_MUTE_N */

1352

#define WM8994_SPKOUTL_MUTE_N_WIDTH 1 /* SPKOUTL_MUTE_N */

1353

#define WM8994_SPKOUTL_VOL_MASK 0x003F /* SPKOUTL_VOL - [5:0] */

1354

#define WM8994_SPKOUTL_VOL_SHIFT 0 /* SPKOUTL_VOL - [5:0] */

1355

#define WM8994_SPKOUTL_VOL_WIDTH 6 /* SPKOUTL_VOL - [5:0] */

1356

1357

/*

1358

* R39 (0x27) - Speaker Volume Right

1359

*/

1360

#define WM8994_SPKOUT_VU 0x0100 /* SPKOUT_VU */

1361

#define WM8994_SPKOUT_VU_MASK 0x0100 /* SPKOUT_VU */

1362

#define WM8994_SPKOUT_VU_SHIFT 8 /* SPKOUT_VU */

1363

#define WM8994_SPKOUT_VU_WIDTH 1 /* SPKOUT_VU */

1364

#define WM8994_SPKOUTR_ZC 0x0080 /* SPKOUTR_ZC */

1365

#define WM8994_SPKOUTR_ZC_MASK 0x0080 /* SPKOUTR_ZC */

1366

#define WM8994_SPKOUTR_ZC_SHIFT 7 /* SPKOUTR_ZC */

1367

#define WM8994_SPKOUTR_ZC_WIDTH 1 /* SPKOUTR_ZC */

1368

#define WM8994_SPKOUTR_MUTE_N 0x0040 /* SPKOUTR_MUTE_N */

1369

#define WM8994_SPKOUTR_MUTE_N_MASK 0x0040 /* SPKOUTR_MUTE_N */

1370

#define WM8994_SPKOUTR_MUTE_N_SHIFT 6 /* SPKOUTR_MUTE_N */

1371

#define WM8994_SPKOUTR_MUTE_N_WIDTH 1 /* SPKOUTR_MUTE_N */

1372

#define WM8994_SPKOUTR_VOL_MASK 0x003F /* SPKOUTR_VOL - [5:0] */

1373

#define WM8994_SPKOUTR_VOL_SHIFT 0 /* SPKOUTR_VOL - [5:0] */

1374

#define WM8994_SPKOUTR_VOL_WIDTH 6 /* SPKOUTR_VOL - [5:0] */

1375

1376

/*

1377

* R40 (0x28) - Input Mixer (2)

1378

*/

1379

#define WM8994_IN2LP_TO_IN2L 0x0080 /* IN2LP_TO_IN2L */

1380

#define WM8994_IN2LP_TO_IN2L_MASK 0x0080 /* IN2LP_TO_IN2L */

1381

#define WM8994_IN2LP_TO_IN2L_SHIFT 7 /* IN2LP_TO_IN2L */

1382

#define WM8994_IN2LP_TO_IN2L_WIDTH 1 /* IN2LP_TO_IN2L */

1383

#define WM8994_IN2LN_TO_IN2L 0x0040 /* IN2LN_TO_IN2L */

1384

#define WM8994_IN2LN_TO_IN2L_MASK 0x0040 /* IN2LN_TO_IN2L */

1385

#define WM8994_IN2LN_TO_IN2L_SHIFT 6 /* IN2LN_TO_IN2L */

1386

#define WM8994_IN2LN_TO_IN2L_WIDTH 1 /* IN2LN_TO_IN2L */

1387

#define WM8994_IN1LP_TO_IN1L 0x0020 /* IN1LP_TO_IN1L */

1388

#define WM8994_IN1LP_TO_IN1L_MASK 0x0020 /* IN1LP_TO_IN1L */

1389

#define WM8994_IN1LP_TO_IN1L_SHIFT 5 /* IN1LP_TO_IN1L */

1390

#define WM8994_IN1LP_TO_IN1L_WIDTH 1 /* IN1LP_TO_IN1L */

1391

#define WM8994_IN1LN_TO_IN1L 0x0010 /* IN1LN_TO_IN1L */

1392

#define WM8994_IN1LN_TO_IN1L_MASK 0x0010 /* IN1LN_TO_IN1L */

1393

#define WM8994_IN1LN_TO_IN1L_SHIFT 4 /* IN1LN_TO_IN1L */

1394

#define WM8994_IN1LN_TO_IN1L_WIDTH 1 /* IN1LN_TO_IN1L */

1395

#define WM8994_IN2RP_TO_IN2R 0x0008 /* IN2RP_TO_IN2R */

1396

#define WM8994_IN2RP_TO_IN2R_MASK 0x0008 /* IN2RP_TO_IN2R */

1397

#define WM8994_IN2RP_TO_IN2R_SHIFT 3 /* IN2RP_TO_IN2R */

1398

#define WM8994_IN2RP_TO_IN2R_WIDTH 1 /* IN2RP_TO_IN2R */

1399

#define WM8994_IN2RN_TO_IN2R 0x0004 /* IN2RN_TO_IN2R */

1400

#define WM8994_IN2RN_TO_IN2R_MASK 0x0004 /* IN2RN_TO_IN2R */

1401

#define WM8994_IN2RN_TO_IN2R_SHIFT 2 /* IN2RN_TO_IN2R */

1402

#define WM8994_IN2RN_TO_IN2R_WIDTH 1 /* IN2RN_TO_IN2R */

1403

#define WM8994_IN1RP_TO_IN1R 0x0002 /* IN1RP_TO_IN1R */

1404

#define WM8994_IN1RP_TO_IN1R_MASK 0x0002 /* IN1RP_TO_IN1R */

1405

#define WM8994_IN1RP_TO_IN1R_SHIFT 1 /* IN1RP_TO_IN1R */

1406

#define WM8994_IN1RP_TO_IN1R_WIDTH 1 /* IN1RP_TO_IN1R */

1407

#define WM8994_IN1RN_TO_IN1R 0x0001 /* IN1RN_TO_IN1R */

1408

#define WM8994_IN1RN_TO_IN1R_MASK 0x0001 /* IN1RN_TO_IN1R */

1409

#define WM8994_IN1RN_TO_IN1R_SHIFT 0 /* IN1RN_TO_IN1R */

1410

#define WM8994_IN1RN_TO_IN1R_WIDTH 1 /* IN1RN_TO_IN1R */

1411

1412

/*

1413

* R41 (0x29) - Input Mixer (3)

1414

*/

1415

#define WM8994_IN2L_TO_MIXINL 0x0100 /* IN2L_TO_MIXINL */

1416

#define WM8994_IN2L_TO_MIXINL_MASK 0x0100 /* IN2L_TO_MIXINL */

1417

#define WM8994_IN2L_TO_MIXINL_SHIFT 8 /* IN2L_TO_MIXINL */

1418

#define WM8994_IN2L_TO_MIXINL_WIDTH 1 /* IN2L_TO_MIXINL */

1419

#define WM8994_IN2L_MIXINL_VOL 0x0080 /* IN2L_MIXINL_VOL */

1420

#define WM8994_IN2L_MIXINL_VOL_MASK 0x0080 /* IN2L_MIXINL_VOL */

1421

#define WM8994_IN2L_MIXINL_VOL_SHIFT 7 /* IN2L_MIXINL_VOL */

1422

#define WM8994_IN2L_MIXINL_VOL_WIDTH 1 /* IN2L_MIXINL_VOL */

1423

#define WM8994_IN1L_TO_MIXINL 0x0020 /* IN1L_TO_MIXINL */

1424

#define WM8994_IN1L_TO_MIXINL_MASK 0x0020 /* IN1L_TO_MIXINL */

1425

#define WM8994_IN1L_TO_MIXINL_SHIFT 5 /* IN1L_TO_MIXINL */

1426

#define WM8994_IN1L_TO_MIXINL_WIDTH 1 /* IN1L_TO_MIXINL */

1427

#define WM8994_IN1L_MIXINL_VOL 0x0010 /* IN1L_MIXINL_VOL */

1428

#define WM8994_IN1L_MIXINL_VOL_MASK 0x0010 /* IN1L_MIXINL_VOL */

1429

#define WM8994_IN1L_MIXINL_VOL_SHIFT 4 /* IN1L_MIXINL_VOL */

1430

#define WM8994_IN1L_MIXINL_VOL_WIDTH 1 /* IN1L_MIXINL_VOL */

1431

#define WM8994_MIXOUTL_MIXINL_VOL_MASK 0x0007 /* MIXOUTL_MIXINL_VOL - [2:0] */

1432

#define WM8994_MIXOUTL_MIXINL_VOL_SHIFT 0 /* MIXOUTL_MIXINL_VOL - [2:0] */

1433

#define WM8994_MIXOUTL_MIXINL_VOL_WIDTH 3 /* MIXOUTL_MIXINL_VOL - [2:0] */

1434

1435

/*

1436

* R42 (0x2A) - Input Mixer (4)

1437

*/

1438

#define WM8994_IN2R_TO_MIXINR 0x0100 /* IN2R_TO_MIXINR */

1439

#define WM8994_IN2R_TO_MIXINR_MASK 0x0100 /* IN2R_TO_MIXINR */

1440

#define WM8994_IN2R_TO_MIXINR_SHIFT 8 /* IN2R_TO_MIXINR */

1441

#define WM8994_IN2R_TO_MIXINR_WIDTH 1 /* IN2R_TO_MIXINR */

1442

#define WM8994_IN2R_MIXINR_VOL 0x0080 /* IN2R_MIXINR_VOL */

1443

#define WM8994_IN2R_MIXINR_VOL_MASK 0x0080 /* IN2R_MIXINR_VOL */

1444

#define WM8994_IN2R_MIXINR_VOL_SHIFT 7 /* IN2R_MIXINR_VOL */

1445

#define WM8994_IN2R_MIXINR_VOL_WIDTH 1 /* IN2R_MIXINR_VOL */

1446

#define WM8994_IN1R_TO_MIXINR 0x0020 /* IN1R_TO_MIXINR */

1447

#define WM8994_IN1R_TO_MIXINR_MASK 0x0020 /* IN1R_TO_MIXINR */

1448

#define WM8994_IN1R_TO_MIXINR_SHIFT 5 /* IN1R_TO_MIXINR */

1449

#define WM8994_IN1R_TO_MIXINR_WIDTH 1 /* IN1R_TO_MIXINR */

1450

#define WM8994_IN1R_MIXINR_VOL 0x0010 /* IN1R_MIXINR_VOL */

1451

#define WM8994_IN1R_MIXINR_VOL_MASK 0x0010 /* IN1R_MIXINR_VOL */

1452

#define WM8994_IN1R_MIXINR_VOL_SHIFT 4 /* IN1R_MIXINR_VOL */

1453

#define WM8994_IN1R_MIXINR_VOL_WIDTH 1 /* IN1R_MIXINR_VOL */

1454

#define WM8994_MIXOUTR_MIXINR_VOL_MASK 0x0007 /* MIXOUTR_MIXINR_VOL - [2:0] */

1455

#define WM8994_MIXOUTR_MIXINR_VOL_SHIFT 0 /* MIXOUTR_MIXINR_VOL - [2:0] */

1456

#define WM8994_MIXOUTR_MIXINR_VOL_WIDTH 3 /* MIXOUTR_MIXINR_VOL - [2:0] */

1457

1458

/*

1459

* R43 (0x2B) - Input Mixer (5)

1460

*/

1461

#define WM8994_IN1LP_MIXINL_VOL_MASK 0x01C0 /* IN1LP_MIXINL_VOL - [8:6] */

1462

#define WM8994_IN1LP_MIXINL_VOL_SHIFT 6 /* IN1LP_MIXINL_VOL - [8:6] */

1463

#define WM8994_IN1LP_MIXINL_VOL_WIDTH 3 /* IN1LP_MIXINL_VOL - [8:6] */

1464

#define WM8994_IN2LRP_MIXINL_VOL_MASK 0x0007 /* IN2LRP_MIXINL_VOL - [2:0] */

1465

#define WM8994_IN2LRP_MIXINL_VOL_SHIFT 0 /* IN2LRP_MIXINL_VOL - [2:0] */

1466

#define WM8994_IN2LRP_MIXINL_VOL_WIDTH 3 /* IN2LRP_MIXINL_VOL - [2:0] */

1467

1468

/*

1469

* R44 (0x2C) - Input Mixer (6)

1470

*/

1471

#define WM8994_IN1RP_MIXINR_VOL_MASK 0x01C0 /* IN1RP_MIXINR_VOL - [8:6] */

1472

#define WM8994_IN1RP_MIXINR_VOL_SHIFT 6 /* IN1RP_MIXINR_VOL - [8:6] */

1473

#define WM8994_IN1RP_MIXINR_VOL_WIDTH 3 /* IN1RP_MIXINR_VOL - [8:6] */

1474

#define WM8994_IN2LRP_MIXINR_VOL_MASK 0x0007 /* IN2LRP_MIXINR_VOL - [2:0] */

1475

#define WM8994_IN2LRP_MIXINR_VOL_SHIFT 0 /* IN2LRP_MIXINR_VOL - [2:0] */

1476

#define WM8994_IN2LRP_MIXINR_VOL_WIDTH 3 /* IN2LRP_MIXINR_VOL - [2:0] */

1477

1478

/*

1479

* R45 (0x2D) - Output Mixer (1)

1480

*/

1481

#define WM8994_DAC1L_TO_HPOUT1L 0x0100 /* DAC1L_TO_HPOUT1L */

1482

#define WM8994_DAC1L_TO_HPOUT1L_MASK 0x0100 /* DAC1L_TO_HPOUT1L */

1483

#define WM8994_DAC1L_TO_HPOUT1L_SHIFT 8 /* DAC1L_TO_HPOUT1L */

1484

#define WM8994_DAC1L_TO_HPOUT1L_WIDTH 1 /* DAC1L_TO_HPOUT1L */

1485

#define WM8994_MIXINR_TO_MIXOUTL 0x0080 /* MIXINR_TO_MIXOUTL */

1486

#define WM8994_MIXINR_TO_MIXOUTL_MASK 0x0080 /* MIXINR_TO_MIXOUTL */

1487

#define WM8994_MIXINR_TO_MIXOUTL_SHIFT 7 /* MIXINR_TO_MIXOUTL */

1488

#define WM8994_MIXINR_TO_MIXOUTL_WIDTH 1 /* MIXINR_TO_MIXOUTL */

1489

#define WM8994_MIXINL_TO_MIXOUTL 0x0040 /* MIXINL_TO_MIXOUTL */

1490

#define WM8994_MIXINL_TO_MIXOUTL_MASK 0x0040 /* MIXINL_TO_MIXOUTL */

1491

#define WM8994_MIXINL_TO_MIXOUTL_SHIFT 6 /* MIXINL_TO_MIXOUTL */

1492

#define WM8994_MIXINL_TO_MIXOUTL_WIDTH 1 /* MIXINL_TO_MIXOUTL */

1493

#define WM8994_IN2RN_TO_MIXOUTL 0x0020 /* IN2RN_TO_MIXOUTL */

1494

#define WM8994_IN2RN_TO_MIXOUTL_MASK 0x0020 /* IN2RN_TO_MIXOUTL */

1495

#define WM8994_IN2RN_TO_MIXOUTL_SHIFT 5 /* IN2RN_TO_MIXOUTL */

1496

#define WM8994_IN2RN_TO_MIXOUTL_WIDTH 1 /* IN2RN_TO_MIXOUTL */

1497

#define WM8994_IN2LN_TO_MIXOUTL 0x0010 /* IN2LN_TO_MIXOUTL */

1498

#define WM8994_IN2LN_TO_MIXOUTL_MASK 0x0010 /* IN2LN_TO_MIXOUTL */

1499

#define WM8994_IN2LN_TO_MIXOUTL_SHIFT 4 /* IN2LN_TO_MIXOUTL */

1500

#define WM8994_IN2LN_TO_MIXOUTL_WIDTH 1 /* IN2LN_TO_MIXOUTL */

1501

#define WM8994_IN1R_TO_MIXOUTL 0x0008 /* IN1R_TO_MIXOUTL */

1502

#define WM8994_IN1R_TO_MIXOUTL_MASK 0x0008 /* IN1R_TO_MIXOUTL */

1503

#define WM8994_IN1R_TO_MIXOUTL_SHIFT 3 /* IN1R_TO_MIXOUTL */

1504

#define WM8994_IN1R_TO_MIXOUTL_WIDTH 1 /* IN1R_TO_MIXOUTL */

1505

#define WM8994_IN1L_TO_MIXOUTL 0x0004 /* IN1L_TO_MIXOUTL */

1506

#define WM8994_IN1L_TO_MIXOUTL_MASK 0x0004 /* IN1L_TO_MIXOUTL */

1507

#define WM8994_IN1L_TO_MIXOUTL_SHIFT 2 /* IN1L_TO_MIXOUTL */

1508

#define WM8994_IN1L_TO_MIXOUTL_WIDTH 1 /* IN1L_TO_MIXOUTL */

1509

#define WM8994_IN2LP_TO_MIXOUTL 0x0002 /* IN2LP_TO_MIXOUTL */

1510

#define WM8994_IN2LP_TO_MIXOUTL_MASK 0x0002 /* IN2LP_TO_MIXOUTL */

1511

#define WM8994_IN2LP_TO_MIXOUTL_SHIFT 1 /* IN2LP_TO_MIXOUTL */

1512

#define WM8994_IN2LP_TO_MIXOUTL_WIDTH 1 /* IN2LP_TO_MIXOUTL */

1513

#define WM8994_DAC1L_TO_MIXOUTL 0x0001 /* DAC1L_TO_MIXOUTL */

1514

#define WM8994_DAC1L_TO_MIXOUTL_MASK 0x0001 /* DAC1L_TO_MIXOUTL */

1515

#define WM8994_DAC1L_TO_MIXOUTL_SHIFT 0 /* DAC1L_TO_MIXOUTL */

1516

#define WM8994_DAC1L_TO_MIXOUTL_WIDTH 1 /* DAC1L_TO_MIXOUTL */

1517

1518

/*

1519

* R46 (0x2E) - Output Mixer (2)

1520

*/

1521

#define WM8994_DAC1R_TO_HPOUT1R 0x0100 /* DAC1R_TO_HPOUT1R */

1522

#define WM8994_DAC1R_TO_HPOUT1R_MASK 0x0100 /* DAC1R_TO_HPOUT1R */

1523

#define WM8994_DAC1R_TO_HPOUT1R_SHIFT 8 /* DAC1R_TO_HPOUT1R */

1524

#define WM8994_DAC1R_TO_HPOUT1R_WIDTH 1 /* DAC1R_TO_HPOUT1R */

1525

#define WM8994_MIXINL_TO_MIXOUTR 0x0080 /* MIXINL_TO_MIXOUTR */

1526

#define WM8994_MIXINL_TO_MIXOUTR_MASK 0x0080 /* MIXINL_TO_MIXOUTR */

1527

#define WM8994_MIXINL_TO_MIXOUTR_SHIFT 7 /* MIXINL_TO_MIXOUTR */

1528

#define WM8994_MIXINL_TO_MIXOUTR_WIDTH 1 /* MIXINL_TO_MIXOUTR */

1529

#define WM8994_MIXINR_TO_MIXOUTR 0x0040 /* MIXINR_TO_MIXOUTR */

1530

#define WM8994_MIXINR_TO_MIXOUTR_MASK 0x0040 /* MIXINR_TO_MIXOUTR */

1531

#define WM8994_MIXINR_TO_MIXOUTR_SHIFT 6 /* MIXINR_TO_MIXOUTR */

1532

#define WM8994_MIXINR_TO_MIXOUTR_WIDTH 1 /* MIXINR_TO_MIXOUTR */

1533

#define WM8994_IN2LN_TO_MIXOUTR 0x0020 /* IN2LN_TO_MIXOUTR */

1534

#define WM8994_IN2LN_TO_MIXOUTR_MASK 0x0020 /* IN2LN_TO_MIXOUTR */

1535

#define WM8994_IN2LN_TO_MIXOUTR_SHIFT 5 /* IN2LN_TO_MIXOUTR */

1536

#define WM8994_IN2LN_TO_MIXOUTR_WIDTH 1 /* IN2LN_TO_MIXOUTR */

1537

#define WM8994_IN2RN_TO_MIXOUTR 0x0010 /* IN2RN_TO_MIXOUTR */

1538

#define WM8994_IN2RN_TO_MIXOUTR_MASK 0x0010 /* IN2RN_TO_MIXOUTR */

1539

#define WM8994_IN2RN_TO_MIXOUTR_SHIFT 4 /* IN2RN_TO_MIXOUTR */

1540

#define WM8994_IN2RN_TO_MIXOUTR_WIDTH 1 /* IN2RN_TO_MIXOUTR */

1541

#define WM8994_IN1L_TO_MIXOUTR 0x0008 /* IN1L_TO_MIXOUTR */

1542

#define WM8994_IN1L_TO_MIXOUTR_MASK 0x0008 /* IN1L_TO_MIXOUTR */

1543

#define WM8994_IN1L_TO_MIXOUTR_SHIFT 3 /* IN1L_TO_MIXOUTR */

1544

#define WM8994_IN1L_TO_MIXOUTR_WIDTH 1 /* IN1L_TO_MIXOUTR */

1545

#define WM8994_IN1R_TO_MIXOUTR 0x0004 /* IN1R_TO_MIXOUTR */

1546

#define WM8994_IN1R_TO_MIXOUTR_MASK 0x0004 /* IN1R_TO_MIXOUTR */

1547

#define WM8994_IN1R_TO_MIXOUTR_SHIFT 2 /* IN1R_TO_MIXOUTR */

1548

#define WM8994_IN1R_TO_MIXOUTR_WIDTH 1 /* IN1R_TO_MIXOUTR */

1549

#define WM8994_IN2RP_TO_MIXOUTR 0x0002 /* IN2RP_TO_MIXOUTR */

1550

#define WM8994_IN2RP_TO_MIXOUTR_MASK 0x0002 /* IN2RP_TO_MIXOUTR */

1551

#define WM8994_IN2RP_TO_MIXOUTR_SHIFT 1 /* IN2RP_TO_MIXOUTR */

1552

#define WM8994_IN2RP_TO_MIXOUTR_WIDTH 1 /* IN2RP_TO_MIXOUTR */

1553

#define WM8994_DAC1R_TO_MIXOUTR 0x0001 /* DAC1R_TO_MIXOUTR */

1554

#define WM8994_DAC1R_TO_MIXOUTR_MASK 0x0001 /* DAC1R_TO_MIXOUTR */

1555

#define WM8994_DAC1R_TO_MIXOUTR_SHIFT 0 /* DAC1R_TO_MIXOUTR */

1556

#define WM8994_DAC1R_TO_MIXOUTR_WIDTH 1 /* DAC1R_TO_MIXOUTR */

1557

1558

/*

1559

* R47 (0x2F) - Output Mixer (3)

1560

*/

1561

#define WM8994_IN2LP_MIXOUTL_VOL_MASK 0x0E00 /* IN2LP_MIXOUTL_VOL - [11:9] */

1562

#define WM8994_IN2LP_MIXOUTL_VOL_SHIFT 9 /* IN2LP_MIXOUTL_VOL - [11:9] */

1563

#define WM8994_IN2LP_MIXOUTL_VOL_WIDTH 3 /* IN2LP_MIXOUTL_VOL - [11:9] */

1564

#define WM8994_IN2LN_MIXOUTL_VOL_MASK 0x01C0 /* IN2LN_MIXOUTL_VOL - [8:6] */

1565

#define WM8994_IN2LN_MIXOUTL_VOL_SHIFT 6 /* IN2LN_MIXOUTL_VOL - [8:6] */

1566

#define WM8994_IN2LN_MIXOUTL_VOL_WIDTH 3 /* IN2LN_MIXOUTL_VOL - [8:6] */

1567

#define WM8994_IN1R_MIXOUTL_VOL_MASK 0x0038 /* IN1R_MIXOUTL_VOL - [5:3] */

1568

#define WM8994_IN1R_MIXOUTL_VOL_SHIFT 3 /* IN1R_MIXOUTL_VOL - [5:3] */

1569

#define WM8994_IN1R_MIXOUTL_VOL_WIDTH 3 /* IN1R_MIXOUTL_VOL - [5:3] */

1570

#define WM8994_IN1L_MIXOUTL_VOL_MASK 0x0007 /* IN1L_MIXOUTL_VOL - [2:0] */

1571

#define WM8994_IN1L_MIXOUTL_VOL_SHIFT 0 /* IN1L_MIXOUTL_VOL - [2:0] */

1572

#define WM8994_IN1L_MIXOUTL_VOL_WIDTH 3 /* IN1L_MIXOUTL_VOL - [2:0] */

1573

1574

/*

1575

* R48 (0x30) - Output Mixer (4)

1576

*/

1577

#define WM8994_IN2RP_MIXOUTR_VOL_MASK 0x0E00 /* IN2RP_MIXOUTR_VOL - [11:9] */

1578

#define WM8994_IN2RP_MIXOUTR_VOL_SHIFT 9 /* IN2RP_MIXOUTR_VOL - [11:9] */

1579

#define WM8994_IN2RP_MIXOUTR_VOL_WIDTH 3 /* IN2RP_MIXOUTR_VOL - [11:9] */

1580

#define WM8994_IN2RN_MIXOUTR_VOL_MASK 0x01C0 /* IN2RN_MIXOUTR_VOL - [8:6] */

1581

#define WM8994_IN2RN_MIXOUTR_VOL_SHIFT 6 /* IN2RN_MIXOUTR_VOL - [8:6] */

1582

#define WM8994_IN2RN_MIXOUTR_VOL_WIDTH 3 /* IN2RN_MIXOUTR_VOL - [8:6] */

1583

#define WM8994_IN1L_MIXOUTR_VOL_MASK 0x0038 /* IN1L_MIXOUTR_VOL - [5:3] */

1584

#define WM8994_IN1L_MIXOUTR_VOL_SHIFT 3 /* IN1L_MIXOUTR_VOL - [5:3] */

1585

#define WM8994_IN1L_MIXOUTR_VOL_WIDTH 3 /* IN1L_MIXOUTR_VOL - [5:3] */

1586

#define WM8994_IN1R_MIXOUTR_VOL_MASK 0x0007 /* IN1R_MIXOUTR_VOL - [2:0] */

1587

#define WM8994_IN1R_MIXOUTR_VOL_SHIFT 0 /* IN1R_MIXOUTR_VOL - [2:0] */

1588

#define WM8994_IN1R_MIXOUTR_VOL_WIDTH 3 /* IN1R_MIXOUTR_VOL - [2:0] */

1589

1590

/*

1591

* R49 (0x31) - Output Mixer (5)

1592

*/

1593

#define WM8994_DAC1L_MIXOUTL_VOL_MASK 0x0E00 /* DAC1L_MIXOUTL_VOL - [11:9] */

1594

#define WM8994_DAC1L_MIXOUTL_VOL_SHIFT 9 /* DAC1L_MIXOUTL_VOL - [11:9] */

1595

#define WM8994_DAC1L_MIXOUTL_VOL_WIDTH 3 /* DAC1L_MIXOUTL_VOL - [11:9] */

1596

#define WM8994_IN2RN_MIXOUTL_VOL_MASK 0x01C0 /* IN2RN_MIXOUTL_VOL - [8:6] */

1597

#define WM8994_IN2RN_MIXOUTL_VOL_SHIFT 6 /* IN2RN_MIXOUTL_VOL - [8:6] */

1598

#define WM8994_IN2RN_MIXOUTL_VOL_WIDTH 3 /* IN2RN_MIXOUTL_VOL - [8:6] */

1599

#define WM8994_MIXINR_MIXOUTL_VOL_MASK 0x0038 /* MIXINR_MIXOUTL_VOL - [5:3] */

1600

#define WM8994_MIXINR_MIXOUTL_VOL_SHIFT 3 /* MIXINR_MIXOUTL_VOL - [5:3] */

1601

#define WM8994_MIXINR_MIXOUTL_VOL_WIDTH 3 /* MIXINR_MIXOUTL_VOL - [5:3] */

1602

#define WM8994_MIXINL_MIXOUTL_VOL_MASK 0x0007 /* MIXINL_MIXOUTL_VOL - [2:0] */

1603

#define WM8994_MIXINL_MIXOUTL_VOL_SHIFT 0 /* MIXINL_MIXOUTL_VOL - [2:0] */

1604

#define WM8994_MIXINL_MIXOUTL_VOL_WIDTH 3 /* MIXINL_MIXOUTL_VOL - [2:0] */

1605

1606

/*

1607

* R50 (0x32) - Output Mixer (6)

1608

*/

1609

#define WM8994_DAC1R_MIXOUTR_VOL_MASK 0x0E00 /* DAC1R_MIXOUTR_VOL - [11:9] */

1610

#define WM8994_DAC1R_MIXOUTR_VOL_SHIFT 9 /* DAC1R_MIXOUTR_VOL - [11:9] */

1611

#define WM8994_DAC1R_MIXOUTR_VOL_WIDTH 3 /* DAC1R_MIXOUTR_VOL - [11:9] */

1612

#define WM8994_IN2LN_MIXOUTR_VOL_MASK 0x01C0 /* IN2LN_MIXOUTR_VOL - [8:6] */

1613

#define WM8994_IN2LN_MIXOUTR_VOL_SHIFT 6 /* IN2LN_MIXOUTR_VOL - [8:6] */

1614

#define WM8994_IN2LN_MIXOUTR_VOL_WIDTH 3 /* IN2LN_MIXOUTR_VOL - [8:6] */

1615

#define WM8994_MIXINL_MIXOUTR_VOL_MASK 0x0038 /* MIXINL_MIXOUTR_VOL - [5:3] */

1616

#define WM8994_MIXINL_MIXOUTR_VOL_SHIFT 3 /* MIXINL_MIXOUTR_VOL - [5:3] */

1617

#define WM8994_MIXINL_MIXOUTR_VOL_WIDTH 3 /* MIXINL_MIXOUTR_VOL - [5:3] */

1618

#define WM8994_MIXINR_MIXOUTR_VOL_MASK 0x0007 /* MIXINR_MIXOUTR_VOL - [2:0] */

1619

#define WM8994_MIXINR_MIXOUTR_VOL_SHIFT 0 /* MIXINR_MIXOUTR_VOL - [2:0] */

1620

#define WM8994_MIXINR_MIXOUTR_VOL_WIDTH 3 /* MIXINR_MIXOUTR_VOL - [2:0] */

1621

1622

/*

1623

* R51 (0x33) - HPOUT2 Mixer

1624

*/

1625

#define WM8994_IN2LRP_TO_HPOUT2 0x0020 /* IN2LRP_TO_HPOUT2 */

1626

#define WM8994_IN2LRP_TO_HPOUT2_MASK 0x0020 /* IN2LRP_TO_HPOUT2 */

1627

#define WM8994_IN2LRP_TO_HPOUT2_SHIFT 5 /* IN2LRP_TO_HPOUT2 */

1628

#define WM8994_IN2LRP_TO_HPOUT2_WIDTH 1 /* IN2LRP_TO_HPOUT2 */

1629

#define WM8994_MIXOUTLVOL_TO_HPOUT2 0x0010 /* MIXOUTLVOL_TO_HPOUT2 */

1630

#define WM8994_MIXOUTLVOL_TO_HPOUT2_MASK 0x0010 /* MIXOUTLVOL_TO_HPOUT2 */

1631

#define WM8994_MIXOUTLVOL_TO_HPOUT2_SHIFT 4 /* MIXOUTLVOL_TO_HPOUT2 */

1632

#define WM8994_MIXOUTLVOL_TO_HPOUT2_WIDTH 1 /* MIXOUTLVOL_TO_HPOUT2 */

1633

#define WM8994_MIXOUTRVOL_TO_HPOUT2 0x0008 /* MIXOUTRVOL_TO_HPOUT2 */

1634

#define WM8994_MIXOUTRVOL_TO_HPOUT2_MASK 0x0008 /* MIXOUTRVOL_TO_HPOUT2 */

1635

#define WM8994_MIXOUTRVOL_TO_HPOUT2_SHIFT 3 /* MIXOUTRVOL_TO_HPOUT2 */

1636

#define WM8994_MIXOUTRVOL_TO_HPOUT2_WIDTH 1 /* MIXOUTRVOL_TO_HPOUT2 */

1637

1638

/*

1639

* R52 (0x34) - Line Mixer (1)

1640

*/

1641

#define WM8994_MIXOUTL_TO_LINEOUT1N 0x0040 /* MIXOUTL_TO_LINEOUT1N */

1642

#define WM8994_MIXOUTL_TO_LINEOUT1N_MASK 0x0040 /* MIXOUTL_TO_LINEOUT1N */

1643

#define WM8994_MIXOUTL_TO_LINEOUT1N_SHIFT 6 /* MIXOUTL_TO_LINEOUT1N */

1644

#define WM8994_MIXOUTL_TO_LINEOUT1N_WIDTH 1 /* MIXOUTL_TO_LINEOUT1N */

1645

#define WM8994_MIXOUTR_TO_LINEOUT1N 0x0020 /* MIXOUTR_TO_LINEOUT1N */

1646

#define WM8994_MIXOUTR_TO_LINEOUT1N_MASK 0x0020 /* MIXOUTR_TO_LINEOUT1N */

1647

#define WM8994_MIXOUTR_TO_LINEOUT1N_SHIFT 5 /* MIXOUTR_TO_LINEOUT1N */

1648

#define WM8994_MIXOUTR_TO_LINEOUT1N_WIDTH 1 /* MIXOUTR_TO_LINEOUT1N */

1649

#define WM8994_LINEOUT1_MODE 0x0010 /* LINEOUT1_MODE */

1650

#define WM8994_LINEOUT1_MODE_MASK 0x0010 /* LINEOUT1_MODE */

1651

#define WM8994_LINEOUT1_MODE_SHIFT 4 /* LINEOUT1_MODE */

1652

#define WM8994_LINEOUT1_MODE_WIDTH 1 /* LINEOUT1_MODE */

1653

#define WM8994_IN1R_TO_LINEOUT1P 0x0004 /* IN1R_TO_LINEOUT1P */

1654

#define WM8994_IN1R_TO_LINEOUT1P_MASK 0x0004 /* IN1R_TO_LINEOUT1P */

1655

#define WM8994_IN1R_TO_LINEOUT1P_SHIFT 2 /* IN1R_TO_LINEOUT1P */

1656

#define WM8994_IN1R_TO_LINEOUT1P_WIDTH 1 /* IN1R_TO_LINEOUT1P */

1657

#define WM8994_IN1L_TO_LINEOUT1P 0x0002 /* IN1L_TO_LINEOUT1P */

1658

#define WM8994_IN1L_TO_LINEOUT1P_MASK 0x0002 /* IN1L_TO_LINEOUT1P */

1659

#define WM8994_IN1L_TO_LINEOUT1P_SHIFT 1 /* IN1L_TO_LINEOUT1P */

1660

#define WM8994_IN1L_TO_LINEOUT1P_WIDTH 1 /* IN1L_TO_LINEOUT1P */

1661

#define WM8994_MIXOUTL_TO_LINEOUT1P 0x0001 /* MIXOUTL_TO_LINEOUT1P */

1662

#define WM8994_MIXOUTL_TO_LINEOUT1P_MASK 0x0001 /* MIXOUTL_TO_LINEOUT1P */

1663

#define WM8994_MIXOUTL_TO_LINEOUT1P_SHIFT 0 /* MIXOUTL_TO_LINEOUT1P */

1664

#define WM8994_MIXOUTL_TO_LINEOUT1P_WIDTH 1 /* MIXOUTL_TO_LINEOUT1P */

1665

1666

/*

1667

* R53 (0x35) - Line Mixer (2)

1668

*/

1669

#define WM8994_MIXOUTR_TO_LINEOUT2N 0x0040 /* MIXOUTR_TO_LINEOUT2N */

1670

#define WM8994_MIXOUTR_TO_LINEOUT2N_MASK 0x0040 /* MIXOUTR_TO_LINEOUT2N */

1671

#define WM8994_MIXOUTR_TO_LINEOUT2N_SHIFT 6 /* MIXOUTR_TO_LINEOUT2N */

1672

#define WM8994_MIXOUTR_TO_LINEOUT2N_WIDTH 1 /* MIXOUTR_TO_LINEOUT2N */

1673

#define WM8994_MIXOUTL_TO_LINEOUT2N 0x0020 /* MIXOUTL_TO_LINEOUT2N */

1674

#define WM8994_MIXOUTL_TO_LINEOUT2N_MASK 0x0020 /* MIXOUTL_TO_LINEOUT2N */

1675

#define WM8994_MIXOUTL_TO_LINEOUT2N_SHIFT 5 /* MIXOUTL_TO_LINEOUT2N */

1676

#define WM8994_MIXOUTL_TO_LINEOUT2N_WIDTH 1 /* MIXOUTL_TO_LINEOUT2N */

1677

#define WM8994_LINEOUT2_MODE 0x0010 /* LINEOUT2_MODE */

1678

#define WM8994_LINEOUT2_MODE_MASK 0x0010 /* LINEOUT2_MODE */

1679

#define WM8994_LINEOUT2_MODE_SHIFT 4 /* LINEOUT2_MODE */

1680

#define WM8994_LINEOUT2_MODE_WIDTH 1 /* LINEOUT2_MODE */

1681

#define WM8994_IN1L_TO_LINEOUT2P 0x0004 /* IN1L_TO_LINEOUT2P */

1682

#define WM8994_IN1L_TO_LINEOUT2P_MASK 0x0004 /* IN1L_TO_LINEOUT2P */

1683

#define WM8994_IN1L_TO_LINEOUT2P_SHIFT 2 /* IN1L_TO_LINEOUT2P */

1684

#define WM8994_IN1L_TO_LINEOUT2P_WIDTH 1 /* IN1L_TO_LINEOUT2P */

1685

#define WM8994_IN1R_TO_LINEOUT2P 0x0002 /* IN1R_TO_LINEOUT2P */

1686

#define WM8994_IN1R_TO_LINEOUT2P_MASK 0x0002 /* IN1R_TO_LINEOUT2P */

1687

#define WM8994_IN1R_TO_LINEOUT2P_SHIFT 1 /* IN1R_TO_LINEOUT2P */

1688

#define WM8994_IN1R_TO_LINEOUT2P_WIDTH 1 /* IN1R_TO_LINEOUT2P */

1689

#define WM8994_MIXOUTR_TO_LINEOUT2P 0x0001 /* MIXOUTR_TO_LINEOUT2P */

1690

#define WM8994_MIXOUTR_TO_LINEOUT2P_MASK 0x0001 /* MIXOUTR_TO_LINEOUT2P */

1691

#define WM8994_MIXOUTR_TO_LINEOUT2P_SHIFT 0 /* MIXOUTR_TO_LINEOUT2P */

1692

#define WM8994_MIXOUTR_TO_LINEOUT2P_WIDTH 1 /* MIXOUTR_TO_LINEOUT2P */

1693

1694

/*

1695

* R54 (0x36) - Speaker Mixer

1696

*/

1697

#define WM8994_DAC2L_TO_SPKMIXL 0x0200 /* DAC2L_TO_SPKMIXL */

1698

#define WM8994_DAC2L_TO_SPKMIXL_MASK 0x0200 /* DAC2L_TO_SPKMIXL */

1699

#define WM8994_DAC2L_TO_SPKMIXL_SHIFT 9 /* DAC2L_TO_SPKMIXL */

1700

#define WM8994_DAC2L_TO_SPKMIXL_WIDTH 1 /* DAC2L_TO_SPKMIXL */

1701

#define WM8994_DAC2R_TO_SPKMIXR 0x0100 /* DAC2R_TO_SPKMIXR */

1702

#define WM8994_DAC2R_TO_SPKMIXR_MASK 0x0100 /* DAC2R_TO_SPKMIXR */

1703

#define WM8994_DAC2R_TO_SPKMIXR_SHIFT 8 /* DAC2R_TO_SPKMIXR */

1704

#define WM8994_DAC2R_TO_SPKMIXR_WIDTH 1 /* DAC2R_TO_SPKMIXR */

1705

#define WM8994_MIXINL_TO_SPKMIXL 0x0080 /* MIXINL_TO_SPKMIXL */

1706

#define WM8994_MIXINL_TO_SPKMIXL_MASK 0x0080 /* MIXINL_TO_SPKMIXL */

1707

#define WM8994_MIXINL_TO_SPKMIXL_SHIFT 7 /* MIXINL_TO_SPKMIXL */

1708

#define WM8994_MIXINL_TO_SPKMIXL_WIDTH 1 /* MIXINL_TO_SPKMIXL */

1709

#define WM8994_MIXINR_TO_SPKMIXR 0x0040 /* MIXINR_TO_SPKMIXR */

1710

#define WM8994_MIXINR_TO_SPKMIXR_MASK 0x0040 /* MIXINR_TO_SPKMIXR */

1711

#define WM8994_MIXINR_TO_SPKMIXR_SHIFT 6 /* MIXINR_TO_SPKMIXR */

1712

#define WM8994_MIXINR_TO_SPKMIXR_WIDTH 1 /* MIXINR_TO_SPKMIXR */

1713

#define WM8994_IN1LP_TO_SPKMIXL 0x0020 /* IN1LP_TO_SPKMIXL */

1714

#define WM8994_IN1LP_TO_SPKMIXL_MASK 0x0020 /* IN1LP_TO_SPKMIXL */

1715

#define WM8994_IN1LP_TO_SPKMIXL_SHIFT 5 /* IN1LP_TO_SPKMIXL */

1716

#define WM8994_IN1LP_TO_SPKMIXL_WIDTH 1 /* IN1LP_TO_SPKMIXL */

1717

#define WM8994_IN1RP_TO_SPKMIXR 0x0010 /* IN1RP_TO_SPKMIXR */

1718

#define WM8994_IN1RP_TO_SPKMIXR_MASK 0x0010 /* IN1RP_TO_SPKMIXR */

1719

#define WM8994_IN1RP_TO_SPKMIXR_SHIFT 4 /* IN1RP_TO_SPKMIXR */

1720

#define WM8994_IN1RP_TO_SPKMIXR_WIDTH 1 /* IN1RP_TO_SPKMIXR */

1721

#define WM8994_MIXOUTL_TO_SPKMIXL 0x0008 /* MIXOUTL_TO_SPKMIXL */

1722

#define WM8994_MIXOUTL_TO_SPKMIXL_MASK 0x0008 /* MIXOUTL_TO_SPKMIXL */

1723

#define WM8994_MIXOUTL_TO_SPKMIXL_SHIFT 3 /* MIXOUTL_TO_SPKMIXL */

1724

#define WM8994_MIXOUTL_TO_SPKMIXL_WIDTH 1 /* MIXOUTL_TO_SPKMIXL */

1725

#define WM8994_MIXOUTR_TO_SPKMIXR 0x0004 /* MIXOUTR_TO_SPKMIXR */

1726

#define WM8994_MIXOUTR_TO_SPKMIXR_MASK 0x0004 /* MIXOUTR_TO_SPKMIXR */

1727

#define WM8994_MIXOUTR_TO_SPKMIXR_SHIFT 2 /* MIXOUTR_TO_SPKMIXR */

1728

#define WM8994_MIXOUTR_TO_SPKMIXR_WIDTH 1 /* MIXOUTR_TO_SPKMIXR */

1729

#define WM8994_DAC1L_TO_SPKMIXL 0x0002 /* DAC1L_TO_SPKMIXL */

1730

#define WM8994_DAC1L_TO_SPKMIXL_MASK 0x0002 /* DAC1L_TO_SPKMIXL */

1731

#define WM8994_DAC1L_TO_SPKMIXL_SHIFT 1 /* DAC1L_TO_SPKMIXL */

1732

#define WM8994_DAC1L_TO_SPKMIXL_WIDTH 1 /* DAC1L_TO_SPKMIXL */

1733

#define WM8994_DAC1R_TO_SPKMIXR 0x0001 /* DAC1R_TO_SPKMIXR */

1734

#define WM8994_DAC1R_TO_SPKMIXR_MASK 0x0001 /* DAC1R_TO_SPKMIXR */

1735

#define WM8994_DAC1R_TO_SPKMIXR_SHIFT 0 /* DAC1R_TO_SPKMIXR */

1736

#define WM8994_DAC1R_TO_SPKMIXR_WIDTH 1 /* DAC1R_TO_SPKMIXR */

1737

1738

/*

1739

* R55 (0x37) - Additional Control

1740

*/

1741

#define WM8994_LINEOUT1_FB 0x0080 /* LINEOUT1_FB */

1742

#define WM8994_LINEOUT1_FB_MASK 0x0080 /* LINEOUT1_FB */

1743

#define WM8994_LINEOUT1_FB_SHIFT 7 /* LINEOUT1_FB */

1744

#define WM8994_LINEOUT1_FB_WIDTH 1 /* LINEOUT1_FB */

1745

#define WM8994_LINEOUT2_FB 0x0040 /* LINEOUT2_FB */

1746

#define WM8994_LINEOUT2_FB_MASK 0x0040 /* LINEOUT2_FB */

1747

#define WM8994_LINEOUT2_FB_SHIFT 6 /* LINEOUT2_FB */

1748

#define WM8994_LINEOUT2_FB_WIDTH 1 /* LINEOUT2_FB */

1749

#define WM8994_VROI 0x0001 /* VROI */

1750

#define WM8994_VROI_MASK 0x0001 /* VROI */

1751

#define WM8994_VROI_SHIFT 0 /* VROI */

1752

#define WM8994_VROI_WIDTH 1 /* VROI */

1753

1754

/*

1755

* R56 (0x38) - AntiPOP (1)

1756

*/

1757

#define WM8994_LINEOUT_VMID_BUF_ENA 0x0080 /* LINEOUT_VMID_BUF_ENA */

1758

#define WM8994_LINEOUT_VMID_BUF_ENA_MASK 0x0080 /* LINEOUT_VMID_BUF_ENA */

1759

#define WM8994_LINEOUT_VMID_BUF_ENA_SHIFT 7 /* LINEOUT_VMID_BUF_ENA */

1760

#define WM8994_LINEOUT_VMID_BUF_ENA_WIDTH 1 /* LINEOUT_VMID_BUF_ENA */

1761

#define WM8994_HPOUT2_IN_ENA 0x0040 /* HPOUT2_IN_ENA */

1762

#define WM8994_HPOUT2_IN_ENA_MASK 0x0040 /* HPOUT2_IN_ENA */

1763

#define WM8994_HPOUT2_IN_ENA_SHIFT 6 /* HPOUT2_IN_ENA */

1764

#define WM8994_HPOUT2_IN_ENA_WIDTH 1 /* HPOUT2_IN_ENA */

1765

#define WM8994_LINEOUT1_DISCH 0x0020 /* LINEOUT1_DISCH */

1766

#define WM8994_LINEOUT1_DISCH_MASK 0x0020 /* LINEOUT1_DISCH */

1767

#define WM8994_LINEOUT1_DISCH_SHIFT 5 /* LINEOUT1_DISCH */

1768

#define WM8994_LINEOUT1_DISCH_WIDTH 1 /* LINEOUT1_DISCH */

1769

#define WM8994_LINEOUT2_DISCH 0x0010 /* LINEOUT2_DISCH */

1770

#define WM8994_LINEOUT2_DISCH_MASK 0x0010 /* LINEOUT2_DISCH */

1771

#define WM8994_LINEOUT2_DISCH_SHIFT 4 /* LINEOUT2_DISCH */

1772

#define WM8994_LINEOUT2_DISCH_WIDTH 1 /* LINEOUT2_DISCH */

1773

1774

/*

1775

* R57 (0x39) - AntiPOP (2)

1776

*/

1777

#define WM8994_MICB2_DISCH 0x0100 /* MICB2_DISCH */

1778

#define WM8994_MICB2_DISCH_MASK 0x0100 /* MICB2_DISCH */

1779

#define WM8994_MICB2_DISCH_SHIFT 8 /* MICB2_DISCH */

1780

#define WM8994_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */

1781

#define WM8994_MICB1_DISCH 0x0080 /* MICB1_DISCH */

1782

#define WM8994_MICB1_DISCH_MASK 0x0080 /* MICB1_DISCH */

1783

#define WM8994_MICB1_DISCH_SHIFT 7 /* MICB1_DISCH */

1784

#define WM8994_MICB1_DISCH_WIDTH 1 /* MICB1_DISCH */

1785

#define WM8994_VMID_RAMP_MASK 0x0060 /* VMID_RAMP - [6:5] */

1786

#define WM8994_VMID_RAMP_SHIFT 5 /* VMID_RAMP - [6:5] */

1787

#define WM8994_VMID_RAMP_WIDTH 2 /* VMID_RAMP - [6:5] */

1788

#define WM8994_VMID_BUF_ENA 0x0008 /* VMID_BUF_ENA */

1789

#define WM8994_VMID_BUF_ENA_MASK 0x0008 /* VMID_BUF_ENA */

1790

#define WM8994_VMID_BUF_ENA_SHIFT 3 /* VMID_BUF_ENA */

1791

#define WM8994_VMID_BUF_ENA_WIDTH 1 /* VMID_BUF_ENA */

1792

#define WM8994_STARTUP_BIAS_ENA 0x0004 /* STARTUP_BIAS_ENA */

1793

#define WM8994_STARTUP_BIAS_ENA_MASK 0x0004 /* STARTUP_BIAS_ENA */

1794

#define WM8994_STARTUP_BIAS_ENA_SHIFT 2 /* STARTUP_BIAS_ENA */

1795

#define WM8994_STARTUP_BIAS_ENA_WIDTH 1 /* STARTUP_BIAS_ENA */

1796

#define WM8994_BIAS_SRC 0x0002 /* BIAS_SRC */

1797

#define WM8994_BIAS_SRC_MASK 0x0002 /* BIAS_SRC */

1798

#define WM8994_BIAS_SRC_SHIFT 1 /* BIAS_SRC */

1799

#define WM8994_BIAS_SRC_WIDTH 1 /* BIAS_SRC */

1800

#define WM8994_VMID_DISCH 0x0001 /* VMID_DISCH */

1801

#define WM8994_VMID_DISCH_MASK 0x0001 /* VMID_DISCH */

1802

#define WM8994_VMID_DISCH_SHIFT 0 /* VMID_DISCH */

1803

#define WM8994_VMID_DISCH_WIDTH 1 /* VMID_DISCH */

1804

1805

/*

1806

* R58 (0x3A) - MICBIAS

1807

*/

1808

#define WM8994_MICD_SCTHR_MASK 0x00C0 /* MICD_SCTHR - [7:6] */

1809

#define WM8994_MICD_SCTHR_SHIFT 6 /* MICD_SCTHR - [7:6] */

1810

#define WM8994_MICD_SCTHR_WIDTH 2 /* MICD_SCTHR - [7:6] */

1811

#define WM8994_MICD_THR_MASK 0x0038 /* MICD_THR - [5:3] */

1812

#define WM8994_MICD_THR_SHIFT 3 /* MICD_THR - [5:3] */

1813

#define WM8994_MICD_THR_WIDTH 3 /* MICD_THR - [5:3] */

1814

#define WM8994_MICD_ENA 0x0004 /* MICD_ENA */

1815

#define WM8994_MICD_ENA_MASK 0x0004 /* MICD_ENA */

1816

#define WM8994_MICD_ENA_SHIFT 2 /* MICD_ENA */

1817

#define WM8994_MICD_ENA_WIDTH 1 /* MICD_ENA */

1818

#define WM8994_MICB2_LVL 0x0002 /* MICB2_LVL */

1819

#define WM8994_MICB2_LVL_MASK 0x0002 /* MICB2_LVL */

1820

#define WM8994_MICB2_LVL_SHIFT 1 /* MICB2_LVL */

1821

#define WM8994_MICB2_LVL_WIDTH 1 /* MICB2_LVL */

1822

#define WM8994_MICB1_LVL 0x0001 /* MICB1_LVL */

1823

#define WM8994_MICB1_LVL_MASK 0x0001 /* MICB1_LVL */

1824

#define WM8994_MICB1_LVL_SHIFT 0 /* MICB1_LVL */

1825

#define WM8994_MICB1_LVL_WIDTH 1 /* MICB1_LVL */

/*

* R59 (0x3B) - LDO 1

*/

#define WM8994_LDO1_VSEL_MASK 0x000E /* LDO1_VSEL - [3:1] */

1831

#define WM8994_LDO1_VSEL_SHIFT 1 /* LDO1_VSEL - [3:1] */

1832

#define WM8994_LDO1_VSEL_WIDTH 3 /* LDO1_VSEL - [3:1] */

1833

#define WM8994_LDO1_DISCH 0x0001 /* LDO1_DISCH */

1834

#define WM8994_LDO1_DISCH_MASK 0x0001 /* LDO1_DISCH */

1835

#define WM8994_LDO1_DISCH_SHIFT 0 /* LDO1_DISCH */

1836

#define WM8994_LDO1_DISCH_WIDTH 1 /* LDO1_DISCH */

/*

* R60 (0x3C) - LDO 2

*/

#define WM8994_LDO2_VSEL_MASK 0x0006 /* LDO2_VSEL - [2:1] */

1842

#define WM8994_LDO2_VSEL_SHIFT 1 /* LDO2_VSEL - [2:1] */

1843

#define WM8994_LDO2_VSEL_WIDTH 2 /* LDO2_VSEL - [2:1] */

1844

#define WM8994_LDO2_DISCH 0x0001 /* LDO2_DISCH */

1845

#define WM8994_LDO2_DISCH_MASK 0x0001 /* LDO2_DISCH */

1846

#define WM8994_LDO2_DISCH_SHIFT 0 /* LDO2_DISCH */

1847

#define WM8994_LDO2_DISCH_WIDTH 1 /* LDO2_DISCH */

1848

1849

/*

1850

* R76 (0x4C) - Charge Pump (1)

1851

*/

1852

#define WM8994_CP_ENA 0x8000 /* CP_ENA */

1853

#define WM8994_CP_ENA_MASK 0x8000 /* CP_ENA */

1854

#define WM8994_CP_ENA_SHIFT 15 /* CP_ENA */

1855

#define WM8994_CP_ENA_WIDTH 1 /* CP_ENA */

1856

1857

/*

1858

* R81 (0x51) - Class W (1)

1859

*/

1860

#define WM8994_CP_DYN_SRC_SEL_MASK 0x0300 /* CP_DYN_SRC_SEL - [9:8] */

1861

#define WM8994_CP_DYN_SRC_SEL_SHIFT 8 /* CP_DYN_SRC_SEL - [9:8] */

1862

#define WM8994_CP_DYN_SRC_SEL_WIDTH 2 /* CP_DYN_SRC_SEL - [9:8] */

1863

#define WM8994_CP_DYN_PWR 0x0001 /* CP_DYN_PWR */

1864

#define WM8994_CP_DYN_PWR_MASK 0x0001 /* CP_DYN_PWR */

1865

#define WM8994_CP_DYN_PWR_SHIFT 0 /* CP_DYN_PWR */

1866

#define WM8994_CP_DYN_PWR_WIDTH 1 /* CP_DYN_PWR */

1867

1868

/*

1869

* R84 (0x54) - DC Servo (1)

1870

*/

1871

#define WM8994_DCS_TRIG_SINGLE_1 0x2000 /* DCS_TRIG_SINGLE_1 */

1872

#define WM8994_DCS_TRIG_SINGLE_1_MASK 0x2000 /* DCS_TRIG_SINGLE_1 */

1873

#define WM8994_DCS_TRIG_SINGLE_1_SHIFT 13 /* DCS_TRIG_SINGLE_1 */

1874

#define WM8994_DCS_TRIG_SINGLE_1_WIDTH 1 /* DCS_TRIG_SINGLE_1 */

1875

#define WM8994_DCS_TRIG_SINGLE_0 0x1000 /* DCS_TRIG_SINGLE_0 */

1876

#define WM8994_DCS_TRIG_SINGLE_0_MASK 0x1000 /* DCS_TRIG_SINGLE_0 */

1877

#define WM8994_DCS_TRIG_SINGLE_0_SHIFT 12 /* DCS_TRIG_SINGLE_0 */

1878

#define WM8994_DCS_TRIG_SINGLE_0_WIDTH 1 /* DCS_TRIG_SINGLE_0 */

1879

#define WM8994_DCS_TRIG_SERIES_1 0x0200 /* DCS_TRIG_SERIES_1 */

1880

#define WM8994_DCS_TRIG_SERIES_1_MASK 0x0200 /* DCS_TRIG_SERIES_1 */

1881

#define WM8994_DCS_TRIG_SERIES_1_SHIFT 9 /* DCS_TRIG_SERIES_1 */

1882

#define WM8994_DCS_TRIG_SERIES_1_WIDTH 1 /* DCS_TRIG_SERIES_1 */

1883

#define WM8994_DCS_TRIG_SERIES_0 0x0100 /* DCS_TRIG_SERIES_0 */

1884

#define WM8994_DCS_TRIG_SERIES_0_MASK 0x0100 /* DCS_TRIG_SERIES_0 */

1885

#define WM8994_DCS_TRIG_SERIES_0_SHIFT 8 /* DCS_TRIG_SERIES_0 */

1886

#define WM8994_DCS_TRIG_SERIES_0_WIDTH 1 /* DCS_TRIG_SERIES_0 */

1887

#define WM8994_DCS_TRIG_STARTUP_1 0x0020 /* DCS_TRIG_STARTUP_1 */

1888

#define WM8994_DCS_TRIG_STARTUP_1_MASK 0x0020 /* DCS_TRIG_STARTUP_1 */

1889

#define WM8994_DCS_TRIG_STARTUP_1_SHIFT 5 /* DCS_TRIG_STARTUP_1 */

1890

#define WM8994_DCS_TRIG_STARTUP_1_WIDTH 1 /* DCS_TRIG_STARTUP_1 */

1891

#define WM8994_DCS_TRIG_STARTUP_0 0x0010 /* DCS_TRIG_STARTUP_0 */

1892

#define WM8994_DCS_TRIG_STARTUP_0_MASK 0x0010 /* DCS_TRIG_STARTUP_0 */

1893

#define WM8994_DCS_TRIG_STARTUP_0_SHIFT 4 /* DCS_TRIG_STARTUP_0 */

1894

#define WM8994_DCS_TRIG_STARTUP_0_WIDTH 1 /* DCS_TRIG_STARTUP_0 */

1895

#define WM8994_DCS_TRIG_DAC_WR_1 0x0008 /* DCS_TRIG_DAC_WR_1 */

1896

#define WM8994_DCS_TRIG_DAC_WR_1_MASK 0x0008 /* DCS_TRIG_DAC_WR_1 */

1897

#define WM8994_DCS_TRIG_DAC_WR_1_SHIFT 3 /* DCS_TRIG_DAC_WR_1 */

1898

#define WM8994_DCS_TRIG_DAC_WR_1_WIDTH 1 /* DCS_TRIG_DAC_WR_1 */

1899

#define WM8994_DCS_TRIG_DAC_WR_0 0x0004 /* DCS_TRIG_DAC_WR_0 */

1900

#define WM8994_DCS_TRIG_DAC_WR_0_MASK 0x0004 /* DCS_TRIG_DAC_WR_0 */

1901

#define WM8994_DCS_TRIG_DAC_WR_0_SHIFT 2 /* DCS_TRIG_DAC_WR_0 */

1902

#define WM8994_DCS_TRIG_DAC_WR_0_WIDTH 1 /* DCS_TRIG_DAC_WR_0 */

1903

#define WM8994_DCS_ENA_CHAN_1 0x0002 /* DCS_ENA_CHAN_1 */

1904

#define WM8994_DCS_ENA_CHAN_1_MASK 0x0002 /* DCS_ENA_CHAN_1 */

1905

#define WM8994_DCS_ENA_CHAN_1_SHIFT 1 /* DCS_ENA_CHAN_1 */

1906

#define WM8994_DCS_ENA_CHAN_1_WIDTH 1 /* DCS_ENA_CHAN_1 */

1907

#define WM8994_DCS_ENA_CHAN_0 0x0001 /* DCS_ENA_CHAN_0 */

1908

#define WM8994_DCS_ENA_CHAN_0_MASK 0x0001 /* DCS_ENA_CHAN_0 */

1909

#define WM8994_DCS_ENA_CHAN_0_SHIFT 0 /* DCS_ENA_CHAN_0 */

1910

#define WM8994_DCS_ENA_CHAN_0_WIDTH 1 /* DCS_ENA_CHAN_0 */

1911

1912

/*

1913

* R85 (0x55) - DC Servo (2)

1914

*/

1915

#define WM8994_DCS_SERIES_NO_01_MASK 0x0FE0 /* DCS_SERIES_NO_01 - [11:5] */

1916

#define WM8994_DCS_SERIES_NO_01_SHIFT 5 /* DCS_SERIES_NO_01 - [11:5] */

1917

#define WM8994_DCS_SERIES_NO_01_WIDTH 7 /* DCS_SERIES_NO_01 - [11:5] */

1918

#define WM8994_DCS_TIMER_PERIOD_01_MASK 0x000F /* DCS_TIMER_PERIOD_01 - [3:0] */

1919

#define WM8994_DCS_TIMER_PERIOD_01_SHIFT 0 /* DCS_TIMER_PERIOD_01 - [3:0] */

1920

#define WM8994_DCS_TIMER_PERIOD_01_WIDTH 4 /* DCS_TIMER_PERIOD_01 - [3:0] */

1921

1922

/*

1923

* R87 (0x57) - DC Servo (4)

1924

*/

1925

#define WM8994_DCS_DAC_WR_VAL_1_MASK 0xFF00 /* DCS_DAC_WR_VAL_1 - [15:8] */

1926

#define WM8994_DCS_DAC_WR_VAL_1_SHIFT 8 /* DCS_DAC_WR_VAL_1 - [15:8] */

1927

#define WM8994_DCS_DAC_WR_VAL_1_WIDTH 8 /* DCS_DAC_WR_VAL_1 - [15:8] */

1928

#define WM8994_DCS_DAC_WR_VAL_0_MASK 0x00FF /* DCS_DAC_WR_VAL_0 - [7:0] */

1929

#define WM8994_DCS_DAC_WR_VAL_0_SHIFT 0 /* DCS_DAC_WR_VAL_0 - [7:0] */

1930

#define WM8994_DCS_DAC_WR_VAL_0_WIDTH 8 /* DCS_DAC_WR_VAL_0 - [7:0] */

1931

1932

/*

1933

* R88 (0x58) - DC Servo Readback

1934

*/

1935

#define WM8994_DCS_CAL_COMPLETE_MASK 0x0300 /* DCS_CAL_COMPLETE - [9:8] */

1936

#define WM8994_DCS_CAL_COMPLETE_SHIFT 8 /* DCS_CAL_COMPLETE - [9:8] */

1937

#define WM8994_DCS_CAL_COMPLETE_WIDTH 2 /* DCS_CAL_COMPLETE - [9:8] */

1938

#define WM8994_DCS_DAC_WR_COMPLETE_MASK 0x0030 /* DCS_DAC_WR_COMPLETE - [5:4] */

1939

#define WM8994_DCS_DAC_WR_COMPLETE_SHIFT 4 /* DCS_DAC_WR_COMPLETE - [5:4] */

1940

#define WM8994_DCS_DAC_WR_COMPLETE_WIDTH 2 /* DCS_DAC_WR_COMPLETE - [5:4] */

1941

#define WM8994_DCS_STARTUP_COMPLETE_MASK 0x0003 /* DCS_STARTUP_COMPLETE - [1:0] */

1942

#define WM8994_DCS_STARTUP_COMPLETE_SHIFT 0 /* DCS_STARTUP_COMPLETE - [1:0] */

1943

#define WM8994_DCS_STARTUP_COMPLETE_WIDTH 2 /* DCS_STARTUP_COMPLETE - [1:0] */

1944

1945

/*

1946

* R96 (0x60) - Analogue HP (1)

1947

*/

1948

#define WM8994_HPOUT1L_RMV_SHORT 0x0080 /* HPOUT1L_RMV_SHORT */

1949

#define WM8994_HPOUT1L_RMV_SHORT_MASK 0x0080 /* HPOUT1L_RMV_SHORT */

1950

#define WM8994_HPOUT1L_RMV_SHORT_SHIFT 7 /* HPOUT1L_RMV_SHORT */

1951

#define WM8994_HPOUT1L_RMV_SHORT_WIDTH 1 /* HPOUT1L_RMV_SHORT */

1952

#define WM8994_HPOUT1L_OUTP 0x0040 /* HPOUT1L_OUTP */

1953

#define WM8994_HPOUT1L_OUTP_MASK 0x0040 /* HPOUT1L_OUTP */

1954

#define WM8994_HPOUT1L_OUTP_SHIFT 6 /* HPOUT1L_OUTP */

1955

#define WM8994_HPOUT1L_OUTP_WIDTH 1 /* HPOUT1L_OUTP */

1956

#define WM8994_HPOUT1L_DLY 0x0020 /* HPOUT1L_DLY */

1957

#define WM8994_HPOUT1L_DLY_MASK 0x0020 /* HPOUT1L_DLY */

1958

#define WM8994_HPOUT1L_DLY_SHIFT 5 /* HPOUT1L_DLY */

1959

#define WM8994_HPOUT1L_DLY_WIDTH 1 /* HPOUT1L_DLY */

1960

#define WM8994_HPOUT1R_RMV_SHORT 0x0008 /* HPOUT1R_RMV_SHORT */

1961

#define WM8994_HPOUT1R_RMV_SHORT_MASK 0x0008 /* HPOUT1R_RMV_SHORT */

1962

#define WM8994_HPOUT1R_RMV_SHORT_SHIFT 3 /* HPOUT1R_RMV_SHORT */

1963

#define WM8994_HPOUT1R_RMV_SHORT_WIDTH 1 /* HPOUT1R_RMV_SHORT */

1964

#define WM8994_HPOUT1R_OUTP 0x0004 /* HPOUT1R_OUTP */

1965

#define WM8994_HPOUT1R_OUTP_MASK 0x0004 /* HPOUT1R_OUTP */

1966

#define WM8994_HPOUT1R_OUTP_SHIFT 2 /* HPOUT1R_OUTP */

1967

#define WM8994_HPOUT1R_OUTP_WIDTH 1 /* HPOUT1R_OUTP */

1968

#define WM8994_HPOUT1R_DLY 0x0002 /* HPOUT1R_DLY */

1969

#define WM8994_HPOUT1R_DLY_MASK 0x0002 /* HPOUT1R_DLY */

1970

#define WM8994_HPOUT1R_DLY_SHIFT 1 /* HPOUT1R_DLY */

1971

#define WM8994_HPOUT1R_DLY_WIDTH 1 /* HPOUT1R_DLY */

1972

1973

/*

1974

* R256 (0x100) - Chip Revision

1975

*/

1976

#define WM8994_CHIP_REV_MASK 0x000F /* CHIP_REV - [3:0] */

1977

#define WM8994_CHIP_REV_SHIFT 0 /* CHIP_REV - [3:0] */

1978

#define WM8994_CHIP_REV_WIDTH 4 /* CHIP_REV - [3:0] */

1979

1980

/*

1981

* R257 (0x101) - Control Interface

1982

*/

1983

#define WM8994_SPI_CONTRD 0x0040 /* SPI_CONTRD */

1984

#define WM8994_SPI_CONTRD_MASK 0x0040 /* SPI_CONTRD */

1985

#define WM8994_SPI_CONTRD_SHIFT 6 /* SPI_CONTRD */

1986

#define WM8994_SPI_CONTRD_WIDTH 1 /* SPI_CONTRD */

1987

#define WM8994_SPI_4WIRE 0x0020 /* SPI_4WIRE */

1988

#define WM8994_SPI_4WIRE_MASK 0x0020 /* SPI_4WIRE */

1989

#define WM8994_SPI_4WIRE_SHIFT 5 /* SPI_4WIRE */

1990

#define WM8994_SPI_4WIRE_WIDTH 1 /* SPI_4WIRE */

1991

#define WM8994_SPI_CFG 0x0010 /* SPI_CFG */

1992

#define WM8994_SPI_CFG_MASK 0x0010 /* SPI_CFG */

1993

#define WM8994_SPI_CFG_SHIFT 4 /* SPI_CFG */

1994

#define WM8994_SPI_CFG_WIDTH 1 /* SPI_CFG */

1995

#define WM8994_AUTO_INC 0x0004 /* AUTO_INC */

1996

#define WM8994_AUTO_INC_MASK 0x0004 /* AUTO_INC */

1997

#define WM8994_AUTO_INC_SHIFT 2 /* AUTO_INC */

1998

#define WM8994_AUTO_INC_WIDTH 1 /* AUTO_INC */

1999

2000

/*

2001

* R272 (0x110) - Write Sequencer Ctrl (1)

2002

*/

2003

#define WM8994_WSEQ_ENA 0x8000 /* WSEQ_ENA */

2004

#define WM8994_WSEQ_ENA_MASK 0x8000 /* WSEQ_ENA */

2005

#define WM8994_WSEQ_ENA_SHIFT 15 /* WSEQ_ENA */

2006

#define WM8994_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */

2007

#define WM8994_WSEQ_ABORT 0x0200 /* WSEQ_ABORT */

2008

#define WM8994_WSEQ_ABORT_MASK 0x0200 /* WSEQ_ABORT */

2009

#define WM8994_WSEQ_ABORT_SHIFT 9 /* WSEQ_ABORT */

2010

#define WM8994_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */

2011

#define WM8994_WSEQ_START 0x0100 /* WSEQ_START */

2012

#define WM8994_WSEQ_START_MASK 0x0100 /* WSEQ_START */

2013

#define WM8994_WSEQ_START_SHIFT 8 /* WSEQ_START */

2014

#define WM8994_WSEQ_START_WIDTH 1 /* WSEQ_START */

2015

#define WM8994_WSEQ_START_INDEX_MASK 0x007F /* WSEQ_START_INDEX - [6:0] */

2016

#define WM8994_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [6:0] */

2017

#define WM8994_WSEQ_START_INDEX_WIDTH 7 /* WSEQ_START_INDEX - [6:0] */

2018

2019

/*

2020

* R273 (0x111) - Write Sequencer Ctrl (2)

2021

*/

2022

#define WM8994_WSEQ_BUSY 0x0100 /* WSEQ_BUSY */

2023

#define WM8994_WSEQ_BUSY_MASK 0x0100 /* WSEQ_BUSY */

2024

#define WM8994_WSEQ_BUSY_SHIFT 8 /* WSEQ_BUSY */

2025

#define WM8994_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */

2026

#define WM8994_WSEQ_CURRENT_INDEX_MASK 0x007F /* WSEQ_CURRENT_INDEX - [6:0] */

2027

#define WM8994_WSEQ_CURRENT_INDEX_SHIFT 0 /* WSEQ_CURRENT_INDEX - [6:0] */

2028

#define WM8994_WSEQ_CURRENT_INDEX_WIDTH 7 /* WSEQ_CURRENT_INDEX - [6:0] */

2029

2030

/*

2031

* R512 (0x200) - AIF1 Clocking (1)

2032

*/

2033

#define WM8994_AIF1CLK_SRC_MASK 0x0018 /* AIF1CLK_SRC - [4:3] */

2034

#define WM8994_AIF1CLK_SRC_SHIFT 3 /* AIF1CLK_SRC - [4:3] */

2035

#define WM8994_AIF1CLK_SRC_WIDTH 2 /* AIF1CLK_SRC - [4:3] */

2036

#define WM8994_AIF1CLK_INV 0x0004 /* AIF1CLK_INV */

2037

#define WM8994_AIF1CLK_INV_MASK 0x0004 /* AIF1CLK_INV */

2038

#define WM8994_AIF1CLK_INV_SHIFT 2 /* AIF1CLK_INV */

2039

#define WM8994_AIF1CLK_INV_WIDTH 1 /* AIF1CLK_INV */

2040

#define WM8994_AIF1CLK_DIV 0x0002 /* AIF1CLK_DIV */

2041

#define WM8994_AIF1CLK_DIV_MASK 0x0002 /* AIF1CLK_DIV */

2042

#define WM8994_AIF1CLK_DIV_SHIFT 1 /* AIF1CLK_DIV */

2043

#define WM8994_AIF1CLK_DIV_WIDTH 1 /* AIF1CLK_DIV */

2044

#define WM8994_AIF1CLK_ENA 0x0001 /* AIF1CLK_ENA */

2045

#define WM8994_AIF1CLK_ENA_MASK 0x0001 /* AIF1CLK_ENA */

2046

#define WM8994_AIF1CLK_ENA_SHIFT 0 /* AIF1CLK_ENA */

2047

#define WM8994_AIF1CLK_ENA_WIDTH 1 /* AIF1CLK_ENA */

2048

2049

/*

2050

* R513 (0x201) - AIF1 Clocking (2)

2051

*/

2052

#define WM8994_AIF1DAC_DIV_MASK 0x0038 /* AIF1DAC_DIV - [5:3] */

2053

#define WM8994_AIF1DAC_DIV_SHIFT 3 /* AIF1DAC_DIV - [5:3] */

2054

#define WM8994_AIF1DAC_DIV_WIDTH 3 /* AIF1DAC_DIV - [5:3] */

2055

#define WM8994_AIF1ADC_DIV_MASK 0x0007 /* AIF1ADC_DIV - [2:0] */

2056

#define WM8994_AIF1ADC_DIV_SHIFT 0 /* AIF1ADC_DIV - [2:0] */

2057

#define WM8994_AIF1ADC_DIV_WIDTH 3 /* AIF1ADC_DIV - [2:0] */

2058

2059

/*

2060

* R516 (0x204) - AIF2 Clocking (1)

2061

*/

2062

#define WM8994_AIF2CLK_SRC_MASK 0x0018 /* AIF2CLK_SRC - [4:3] */

2063

#define WM8994_AIF2CLK_SRC_SHIFT 3 /* AIF2CLK_SRC - [4:3] */

2064

#define WM8994_AIF2CLK_SRC_WIDTH 2 /* AIF2CLK_SRC - [4:3] */

2065

#define WM8994_AIF2CLK_INV 0x0004 /* AIF2CLK_INV */

2066

#define WM8994_AIF2CLK_INV_MASK 0x0004 /* AIF2CLK_INV */

2067

#define WM8994_AIF2CLK_INV_SHIFT 2 /* AIF2CLK_INV */

2068

#define WM8994_AIF2CLK_INV_WIDTH 1 /* AIF2CLK_INV */

2069

#define WM8994_AIF2CLK_DIV 0x0002 /* AIF2CLK_DIV */

2070

#define WM8994_AIF2CLK_DIV_MASK 0x0002 /* AIF2CLK_DIV */

2071

#define WM8994_AIF2CLK_DIV_SHIFT 1 /* AIF2CLK_DIV */

2072

#define WM8994_AIF2CLK_DIV_WIDTH 1 /* AIF2CLK_DIV */

2073

#define WM8994_AIF2CLK_ENA 0x0001 /* AIF2CLK_ENA */

2074

#define WM8994_AIF2CLK_ENA_MASK 0x0001 /* AIF2CLK_ENA */

2075

#define WM8994_AIF2CLK_ENA_SHIFT 0 /* AIF2CLK_ENA */

2076

#define WM8994_AIF2CLK_ENA_WIDTH 1 /* AIF2CLK_ENA */

2077

2078

/*

2079

* R517 (0x205) - AIF2 Clocking (2)

2080

*/

2081

#define WM8994_AIF2DAC_DIV_MASK 0x0038 /* AIF2DAC_DIV - [5:3] */

2082

#define WM8994_AIF2DAC_DIV_SHIFT 3 /* AIF2DAC_DIV - [5:3] */

2083

#define WM8994_AIF2DAC_DIV_WIDTH 3 /* AIF2DAC_DIV - [5:3] */

2084

#define WM8994_AIF2ADC_DIV_MASK 0x0007 /* AIF2ADC_DIV - [2:0] */

2085

#define WM8994_AIF2ADC_DIV_SHIFT 0 /* AIF2ADC_DIV - [2:0] */

2086

#define WM8994_AIF2ADC_DIV_WIDTH 3 /* AIF2ADC_DIV - [2:0] */

2087

2088

/*

2089

* R520 (0x208) - Clocking (1)

2090

*/

Mark Brown

d6addcc

2010-11-26 15:21:08 +0000

[diff] [blame^]

2091

#define WM8958_DSP2CLK_ENA 0x4000 /* DSP2CLK_ENA */

2092

#define WM8958_DSP2CLK_ENA_MASK 0x4000 /* DSP2CLK_ENA */

2093

#define WM8958_DSP2CLK_ENA_SHIFT 14 /* DSP2CLK_ENA */

2094

#define WM8958_DSP2CLK_ENA_WIDTH 1 /* DSP2CLK_ENA */

2095

#define WM8958_DSP2CLK_SRC 0x1000 /* DSP2CLK_SRC */

2096

#define WM8958_DSP2CLK_SRC_MASK 0x1000 /* DSP2CLK_SRC */

2097

#define WM8958_DSP2CLK_SRC_SHIFT 12 /* DSP2CLK_SRC */

2098

#define WM8958_DSP2CLK_SRC_WIDTH 1 /* DSP2CLK_SRC */

Mark Brown

1c4d3b70

2010-01-29 18:20:28 +0000

[diff] [blame]

2099

#define WM8994_TOCLK_ENA 0x0010 /* TOCLK_ENA */

2100

#define WM8994_TOCLK_ENA_MASK 0x0010 /* TOCLK_ENA */

2101

#define WM8994_TOCLK_ENA_SHIFT 4 /* TOCLK_ENA */

2102

#define WM8994_TOCLK_ENA_WIDTH 1 /* TOCLK_ENA */

2103

#define WM8994_AIF1DSPCLK_ENA 0x0008 /* AIF1DSPCLK_ENA */

2104

#define WM8994_AIF1DSPCLK_ENA_MASK 0x0008 /* AIF1DSPCLK_ENA */

2105

#define WM8994_AIF1DSPCLK_ENA_SHIFT 3 /* AIF1DSPCLK_ENA */

2106

#define WM8994_AIF1DSPCLK_ENA_WIDTH 1 /* AIF1DSPCLK_ENA */

2107

#define WM8994_AIF2DSPCLK_ENA 0x0004 /* AIF2DSPCLK_ENA */

2108

#define WM8994_AIF2DSPCLK_ENA_MASK 0x0004 /* AIF2DSPCLK_ENA */

2109

#define WM8994_AIF2DSPCLK_ENA_SHIFT 2 /* AIF2DSPCLK_ENA */

2110

#define WM8994_AIF2DSPCLK_ENA_WIDTH 1 /* AIF2DSPCLK_ENA */

2111

#define WM8994_SYSDSPCLK_ENA 0x0002 /* SYSDSPCLK_ENA */

2112

#define WM8994_SYSDSPCLK_ENA_MASK 0x0002 /* SYSDSPCLK_ENA */

2113

#define WM8994_SYSDSPCLK_ENA_SHIFT 1 /* SYSDSPCLK_ENA */

2114

#define WM8994_SYSDSPCLK_ENA_WIDTH 1 /* SYSDSPCLK_ENA */

2115

#define WM8994_SYSCLK_SRC 0x0001 /* SYSCLK_SRC */

2116

#define WM8994_SYSCLK_SRC_MASK 0x0001 /* SYSCLK_SRC */

2117

#define WM8994_SYSCLK_SRC_SHIFT 0 /* SYSCLK_SRC */

2118

#define WM8994_SYSCLK_SRC_WIDTH 1 /* SYSCLK_SRC */

2119

2120

/*

2121

* R521 (0x209) - Clocking (2)

2122

*/

2123

#define WM8994_TOCLK_DIV_MASK 0x0700 /* TOCLK_DIV - [10:8] */

2124

#define WM8994_TOCLK_DIV_SHIFT 8 /* TOCLK_DIV - [10:8] */

2125

#define WM8994_TOCLK_DIV_WIDTH 3 /* TOCLK_DIV - [10:8] */

2126

#define WM8994_DBCLK_DIV_MASK 0x0070 /* DBCLK_DIV - [6:4] */

2127

#define WM8994_DBCLK_DIV_SHIFT 4 /* DBCLK_DIV - [6:4] */

2128

#define WM8994_DBCLK_DIV_WIDTH 3 /* DBCLK_DIV - [6:4] */

2129

#define WM8994_OPCLK_DIV_MASK 0x0007 /* OPCLK_DIV - [2:0] */

2130

#define WM8994_OPCLK_DIV_SHIFT 0 /* OPCLK_DIV - [2:0] */

2131

#define WM8994_OPCLK_DIV_WIDTH 3 /* OPCLK_DIV - [2:0] */

2132

2133

/*

2134

* R528 (0x210) - AIF1 Rate

2135

*/

2136

#define WM8994_AIF1_SR_MASK 0x00F0 /* AIF1_SR - [7:4] */

2137

#define WM8994_AIF1_SR_SHIFT 4 /* AIF1_SR - [7:4] */

2138

#define WM8994_AIF1_SR_WIDTH 4 /* AIF1_SR - [7:4] */

2139

#define WM8994_AIF1CLK_RATE_MASK 0x000F /* AIF1CLK_RATE - [3:0] */

2140

#define WM8994_AIF1CLK_RATE_SHIFT 0 /* AIF1CLK_RATE - [3:0] */

2141

#define WM8994_AIF1CLK_RATE_WIDTH 4 /* AIF1CLK_RATE - [3:0] */

2142

2143

/*

2144

* R529 (0x211) - AIF2 Rate

2145

*/

2146

#define WM8994_AIF2_SR_MASK 0x00F0 /* AIF2_SR - [7:4] */

2147

#define WM8994_AIF2_SR_SHIFT 4 /* AIF2_SR - [7:4] */

2148

#define WM8994_AIF2_SR_WIDTH 4 /* AIF2_SR - [7:4] */

2149

#define WM8994_AIF2CLK_RATE_MASK 0x000F /* AIF2CLK_RATE - [3:0] */

2150

#define WM8994_AIF2CLK_RATE_SHIFT 0 /* AIF2CLK_RATE - [3:0] */

2151

#define WM8994_AIF2CLK_RATE_WIDTH 4 /* AIF2CLK_RATE - [3:0] */

2152

2153

/*

2154

* R530 (0x212) - Rate Status

2155

*/

2156

#define WM8994_SR_ERROR_MASK 0x000F /* SR_ERROR - [3:0] */

2157

#define WM8994_SR_ERROR_SHIFT 0 /* SR_ERROR - [3:0] */

2158

#define WM8994_SR_ERROR_WIDTH 4 /* SR_ERROR - [3:0] */

2159

2160

/*

2161

* R544 (0x220) - FLL1 Control (1)

2162

*/

2163

#define WM8994_FLL1_FRAC 0x0004 /* FLL1_FRAC */

2164

#define WM8994_FLL1_FRAC_MASK 0x0004 /* FLL1_FRAC */

2165

#define WM8994_FLL1_FRAC_SHIFT 2 /* FLL1_FRAC */

2166

#define WM8994_FLL1_FRAC_WIDTH 1 /* FLL1_FRAC */

2167

#define WM8994_FLL1_OSC_ENA 0x0002 /* FLL1_OSC_ENA */

2168

#define WM8994_FLL1_OSC_ENA_MASK 0x0002 /* FLL1_OSC_ENA */

2169

#define WM8994_FLL1_OSC_ENA_SHIFT 1 /* FLL1_OSC_ENA */

2170

#define WM8994_FLL1_OSC_ENA_WIDTH 1 /* FLL1_OSC_ENA */

2171

#define WM8994_FLL1_ENA 0x0001 /* FLL1_ENA */

2172

#define WM8994_FLL1_ENA_MASK 0x0001 /* FLL1_ENA */

2173

#define WM8994_FLL1_ENA_SHIFT 0 /* FLL1_ENA */

2174

#define WM8994_FLL1_ENA_WIDTH 1 /* FLL1_ENA */

2175

2176

/*

2177

* R545 (0x221) - FLL1 Control (2)

2178

*/

2179

#define WM8994_FLL1_OUTDIV_MASK 0x3F00 /* FLL1_OUTDIV - [13:8] */

2180

#define WM8994_FLL1_OUTDIV_SHIFT 8 /* FLL1_OUTDIV - [13:8] */

2181

#define WM8994_FLL1_OUTDIV_WIDTH 6 /* FLL1_OUTDIV - [13:8] */

2182

#define WM8994_FLL1_CTRL_RATE_MASK 0x0070 /* FLL1_CTRL_RATE - [6:4] */

2183

#define WM8994_FLL1_CTRL_RATE_SHIFT 4 /* FLL1_CTRL_RATE - [6:4] */

2184

#define WM8994_FLL1_CTRL_RATE_WIDTH 3 /* FLL1_CTRL_RATE - [6:4] */

2185

#define WM8994_FLL1_FRATIO_MASK 0x0007 /* FLL1_FRATIO - [2:0] */

2186

#define WM8994_FLL1_FRATIO_SHIFT 0 /* FLL1_FRATIO - [2:0] */

2187

#define WM8994_FLL1_FRATIO_WIDTH 3 /* FLL1_FRATIO - [2:0] */

2188

2189

/*

2190

* R546 (0x222) - FLL1 Control (3)

2191

*/

2192

#define WM8994_FLL1_K_MASK 0xFFFF /* FLL1_K - [15:0] */

2193

#define WM8994_FLL1_K_SHIFT 0 /* FLL1_K - [15:0] */

2194

#define WM8994_FLL1_K_WIDTH 16 /* FLL1_K - [15:0] */

2195

2196

/*

2197

* R547 (0x223) - FLL1 Control (4)

2198

*/

2199

#define WM8994_FLL1_N_MASK 0x7FE0 /* FLL1_N - [14:5] */

2200

#define WM8994_FLL1_N_SHIFT 5 /* FLL1_N - [14:5] */

2201

#define WM8994_FLL1_N_WIDTH 10 /* FLL1_N - [14:5] */

2202

#define WM8994_FLL1_LOOP_GAIN_MASK 0x000F /* FLL1_LOOP_GAIN - [3:0] */

2203

#define WM8994_FLL1_LOOP_GAIN_SHIFT 0 /* FLL1_LOOP_GAIN - [3:0] */

2204

#define WM8994_FLL1_LOOP_GAIN_WIDTH 4 /* FLL1_LOOP_GAIN - [3:0] */

2205

2206

/*

2207

* R548 (0x224) - FLL1 Control (5)

2208

*/

2209

#define WM8994_FLL1_FRC_NCO_VAL_MASK 0x1F80 /* FLL1_FRC_NCO_VAL - [12:7] */

2210

#define WM8994_FLL1_FRC_NCO_VAL_SHIFT 7 /* FLL1_FRC_NCO_VAL - [12:7] */

2211

#define WM8994_FLL1_FRC_NCO_VAL_WIDTH 6 /* FLL1_FRC_NCO_VAL - [12:7] */

2212

#define WM8994_FLL1_FRC_NCO 0x0040 /* FLL1_FRC_NCO */

2213

#define WM8994_FLL1_FRC_NCO_MASK 0x0040 /* FLL1_FRC_NCO */

2214

#define WM8994_FLL1_FRC_NCO_SHIFT 6 /* FLL1_FRC_NCO */

2215

#define WM8994_FLL1_FRC_NCO_WIDTH 1 /* FLL1_FRC_NCO */

2216

#define WM8994_FLL1_REFCLK_DIV_MASK 0x0018 /* FLL1_REFCLK_DIV - [4:3] */

2217

#define WM8994_FLL1_REFCLK_DIV_SHIFT 3 /* FLL1_REFCLK_DIV - [4:3] */

2218

#define WM8994_FLL1_REFCLK_DIV_WIDTH 2 /* FLL1_REFCLK_DIV - [4:3] */

2219

#define WM8994_FLL1_REFCLK_SRC_MASK 0x0003 /* FLL1_REFCLK_SRC - [1:0] */

2220

#define WM8994_FLL1_REFCLK_SRC_SHIFT 0 /* FLL1_REFCLK_SRC - [1:0] */

2221

#define WM8994_FLL1_REFCLK_SRC_WIDTH 2 /* FLL1_REFCLK_SRC - [1:0] */

2222

2223

/*

2224

* R576 (0x240) - FLL2 Control (1)

2225

*/

2226

#define WM8994_FLL2_FRAC 0x0004 /* FLL2_FRAC */

2227

#define WM8994_FLL2_FRAC_MASK 0x0004 /* FLL2_FRAC */

2228

#define WM8994_FLL2_FRAC_SHIFT 2 /* FLL2_FRAC */

2229

#define WM8994_FLL2_FRAC_WIDTH 1 /* FLL2_FRAC */

2230

#define WM8994_FLL2_OSC_ENA 0x0002 /* FLL2_OSC_ENA */

2231

#define WM8994_FLL2_OSC_ENA_MASK 0x0002 /* FLL2_OSC_ENA */

2232

#define WM8994_FLL2_OSC_ENA_SHIFT 1 /* FLL2_OSC_ENA */

2233

#define WM8994_FLL2_OSC_ENA_WIDTH 1 /* FLL2_OSC_ENA */

2234

#define WM8994_FLL2_ENA 0x0001 /* FLL2_ENA */

2235

#define WM8994_FLL2_ENA_MASK 0x0001 /* FLL2_ENA */

2236

#define WM8994_FLL2_ENA_SHIFT 0 /* FLL2_ENA */

2237

#define WM8994_FLL2_ENA_WIDTH 1 /* FLL2_ENA */

2238

2239

/*

2240

* R577 (0x241) - FLL2 Control (2)

2241

*/

2242

#define WM8994_FLL2_OUTDIV_MASK 0x3F00 /* FLL2_OUTDIV - [13:8] */

2243

#define WM8994_FLL2_OUTDIV_SHIFT 8 /* FLL2_OUTDIV - [13:8] */

2244

#define WM8994_FLL2_OUTDIV_WIDTH 6 /* FLL2_OUTDIV - [13:8] */

2245

#define WM8994_FLL2_CTRL_RATE_MASK 0x0070 /* FLL2_CTRL_RATE - [6:4] */

2246

#define WM8994_FLL2_CTRL_RATE_SHIFT 4 /* FLL2_CTRL_RATE - [6:4] */

2247

#define WM8994_FLL2_CTRL_RATE_WIDTH 3 /* FLL2_CTRL_RATE - [6:4] */

2248

#define WM8994_FLL2_FRATIO_MASK 0x0007 /* FLL2_FRATIO - [2:0] */

2249

#define WM8994_FLL2_FRATIO_SHIFT 0 /* FLL2_FRATIO - [2:0] */

2250

#define WM8994_FLL2_FRATIO_WIDTH 3 /* FLL2_FRATIO - [2:0] */

2251

2252

/*

2253

* R578 (0x242) - FLL2 Control (3)

2254

*/

2255

#define WM8994_FLL2_K_MASK 0xFFFF /* FLL2_K - [15:0] */

2256

#define WM8994_FLL2_K_SHIFT 0 /* FLL2_K - [15:0] */

2257

#define WM8994_FLL2_K_WIDTH 16 /* FLL2_K - [15:0] */

2258

2259

/*

2260

* R579 (0x243) - FLL2 Control (4)

2261

*/

2262

#define WM8994_FLL2_N_MASK 0x7FE0 /* FLL2_N - [14:5] */

2263

#define WM8994_FLL2_N_SHIFT 5 /* FLL2_N - [14:5] */

2264

#define WM8994_FLL2_N_WIDTH 10 /* FLL2_N - [14:5] */

2265

#define WM8994_FLL2_LOOP_GAIN_MASK 0x000F /* FLL2_LOOP_GAIN - [3:0] */

2266

#define WM8994_FLL2_LOOP_GAIN_SHIFT 0 /* FLL2_LOOP_GAIN - [3:0] */

2267

#define WM8994_FLL2_LOOP_GAIN_WIDTH 4 /* FLL2_LOOP_GAIN - [3:0] */

2268

2269

/*

2270

* R580 (0x244) - FLL2 Control (5)

2271

*/

2272

#define WM8994_FLL2_FRC_NCO_VAL_MASK 0x1F80 /* FLL2_FRC_NCO_VAL - [12:7] */

2273

#define WM8994_FLL2_FRC_NCO_VAL_SHIFT 7 /* FLL2_FRC_NCO_VAL - [12:7] */

2274

#define WM8994_FLL2_FRC_NCO_VAL_WIDTH 6 /* FLL2_FRC_NCO_VAL - [12:7] */

2275

#define WM8994_FLL2_FRC_NCO 0x0040 /* FLL2_FRC_NCO */

2276

#define WM8994_FLL2_FRC_NCO_MASK 0x0040 /* FLL2_FRC_NCO */

2277

#define WM8994_FLL2_FRC_NCO_SHIFT 6 /* FLL2_FRC_NCO */

2278

#define WM8994_FLL2_FRC_NCO_WIDTH 1 /* FLL2_FRC_NCO */

2279

#define WM8994_FLL2_REFCLK_DIV_MASK 0x0018 /* FLL2_REFCLK_DIV - [4:3] */

2280

#define WM8994_FLL2_REFCLK_DIV_SHIFT 3 /* FLL2_REFCLK_DIV - [4:3] */

2281

#define WM8994_FLL2_REFCLK_DIV_WIDTH 2 /* FLL2_REFCLK_DIV - [4:3] */

2282

#define WM8994_FLL2_REFCLK_SRC_MASK 0x0003 /* FLL2_REFCLK_SRC - [1:0] */

2283

#define WM8994_FLL2_REFCLK_SRC_SHIFT 0 /* FLL2_REFCLK_SRC - [1:0] */

2284

#define WM8994_FLL2_REFCLK_SRC_WIDTH 2 /* FLL2_REFCLK_SRC - [1:0] */

2285

2286

/*

2287

* R768 (0x300) - AIF1 Control (1)

2288

*/

2289

#define WM8994_AIF1ADCL_SRC 0x8000 /* AIF1ADCL_SRC */

2290

#define WM8994_AIF1ADCL_SRC_MASK 0x8000 /* AIF1ADCL_SRC */

2291

#define WM8994_AIF1ADCL_SRC_SHIFT 15 /* AIF1ADCL_SRC */

2292

#define WM8994_AIF1ADCL_SRC_WIDTH 1 /* AIF1ADCL_SRC */

2293

#define WM8994_AIF1ADCR_SRC 0x4000 /* AIF1ADCR_SRC */

2294

#define WM8994_AIF1ADCR_SRC_MASK 0x4000 /* AIF1ADCR_SRC */

2295

#define WM8994_AIF1ADCR_SRC_SHIFT 14 /* AIF1ADCR_SRC */

2296

#define WM8994_AIF1ADCR_SRC_WIDTH 1 /* AIF1ADCR_SRC */

2297

#define WM8994_AIF1ADC_TDM 0x2000 /* AIF1ADC_TDM */

2298

#define WM8994_AIF1ADC_TDM_MASK 0x2000 /* AIF1ADC_TDM */

2299

#define WM8994_AIF1ADC_TDM_SHIFT 13 /* AIF1ADC_TDM */

2300

#define WM8994_AIF1ADC_TDM_WIDTH 1 /* AIF1ADC_TDM */

2301

#define WM8994_AIF1_BCLK_INV 0x0100 /* AIF1_BCLK_INV */

2302

#define WM8994_AIF1_BCLK_INV_MASK 0x0100 /* AIF1_BCLK_INV */

2303

#define WM8994_AIF1_BCLK_INV_SHIFT 8 /* AIF1_BCLK_INV */

2304

#define WM8994_AIF1_BCLK_INV_WIDTH 1 /* AIF1_BCLK_INV */

2305

#define WM8994_AIF1_LRCLK_INV 0x0080 /* AIF1_LRCLK_INV */

2306

#define WM8994_AIF1_LRCLK_INV_MASK 0x0080 /* AIF1_LRCLK_INV */

2307

#define WM8994_AIF1_LRCLK_INV_SHIFT 7 /* AIF1_LRCLK_INV */

2308

#define WM8994_AIF1_LRCLK_INV_WIDTH 1 /* AIF1_LRCLK_INV */

2309

#define WM8994_AIF1_WL_MASK 0x0060 /* AIF1_WL - [6:5] */

2310

#define WM8994_AIF1_WL_SHIFT 5 /* AIF1_WL - [6:5] */

2311

#define WM8994_AIF1_WL_WIDTH 2 /* AIF1_WL - [6:5] */

2312

#define WM8994_AIF1_FMT_MASK 0x0018 /* AIF1_FMT - [4:3] */

2313

#define WM8994_AIF1_FMT_SHIFT 3 /* AIF1_FMT - [4:3] */

2314

#define WM8994_AIF1_FMT_WIDTH 2 /* AIF1_FMT - [4:3] */

2315

2316

/*

2317

* R769 (0x301) - AIF1 Control (2)

2318

*/

2319

#define WM8994_AIF1DACL_SRC 0x8000 /* AIF1DACL_SRC */

2320

#define WM8994_AIF1DACL_SRC_MASK 0x8000 /* AIF1DACL_SRC */

2321

#define WM8994_AIF1DACL_SRC_SHIFT 15 /* AIF1DACL_SRC */

2322

#define WM8994_AIF1DACL_SRC_WIDTH 1 /* AIF1DACL_SRC */

2323

#define WM8994_AIF1DACR_SRC 0x4000 /* AIF1DACR_SRC */

2324

#define WM8994_AIF1DACR_SRC_MASK 0x4000 /* AIF1DACR_SRC */

2325

#define WM8994_AIF1DACR_SRC_SHIFT 14 /* AIF1DACR_SRC */

2326

#define WM8994_AIF1DACR_SRC_WIDTH 1 /* AIF1DACR_SRC */

2327

#define WM8994_AIF1DAC_BOOST_MASK 0x0C00 /* AIF1DAC_BOOST - [11:10] */

2328

#define WM8994_AIF1DAC_BOOST_SHIFT 10 /* AIF1DAC_BOOST - [11:10] */

2329

#define WM8994_AIF1DAC_BOOST_WIDTH 2 /* AIF1DAC_BOOST - [11:10] */

2330

#define WM8994_AIF1_MONO 0x0100 /* AIF1_MONO */

2331

#define WM8994_AIF1_MONO_MASK 0x0100 /* AIF1_MONO */

2332

#define WM8994_AIF1_MONO_SHIFT 8 /* AIF1_MONO */

2333

#define WM8994_AIF1_MONO_WIDTH 1 /* AIF1_MONO */

2334

#define WM8994_AIF1DAC_COMP 0x0010 /* AIF1DAC_COMP */

2335

#define WM8994_AIF1DAC_COMP_MASK 0x0010 /* AIF1DAC_COMP */

2336

#define WM8994_AIF1DAC_COMP_SHIFT 4 /* AIF1DAC_COMP */

2337

#define WM8994_AIF1DAC_COMP_WIDTH 1 /* AIF1DAC_COMP */

2338

#define WM8994_AIF1DAC_COMPMODE 0x0008 /* AIF1DAC_COMPMODE */

2339

#define WM8994_AIF1DAC_COMPMODE_MASK 0x0008 /* AIF1DAC_COMPMODE */

2340

#define WM8994_AIF1DAC_COMPMODE_SHIFT 3 /* AIF1DAC_COMPMODE */

2341

#define WM8994_AIF1DAC_COMPMODE_WIDTH 1 /* AIF1DAC_COMPMODE */

2342

#define WM8994_AIF1ADC_COMP 0x0004 /* AIF1ADC_COMP */

2343

#define WM8994_AIF1ADC_COMP_MASK 0x0004 /* AIF1ADC_COMP */

2344

#define WM8994_AIF1ADC_COMP_SHIFT 2 /* AIF1ADC_COMP */

2345

#define WM8994_AIF1ADC_COMP_WIDTH 1 /* AIF1ADC_COMP */

2346

#define WM8994_AIF1ADC_COMPMODE 0x0002 /* AIF1ADC_COMPMODE */

2347

#define WM8994_AIF1ADC_COMPMODE_MASK 0x0002 /* AIF1ADC_COMPMODE */

2348

#define WM8994_AIF1ADC_COMPMODE_SHIFT 1 /* AIF1ADC_COMPMODE */

2349

#define WM8994_AIF1ADC_COMPMODE_WIDTH 1 /* AIF1ADC_COMPMODE */

2350

#define WM8994_AIF1_LOOPBACK 0x0001 /* AIF1_LOOPBACK */

2351

#define WM8994_AIF1_LOOPBACK_MASK 0x0001 /* AIF1_LOOPBACK */

2352

#define WM8994_AIF1_LOOPBACK_SHIFT 0 /* AIF1_LOOPBACK */

2353

#define WM8994_AIF1_LOOPBACK_WIDTH 1 /* AIF1_LOOPBACK */

2354

2355

/*

2356

* R770 (0x302) - AIF1 Master/Slave

2357

*/

2358

#define WM8994_AIF1_TRI 0x8000 /* AIF1_TRI */

2359

#define WM8994_AIF1_TRI_MASK 0x8000 /* AIF1_TRI */

2360

#define WM8994_AIF1_TRI_SHIFT 15 /* AIF1_TRI */

2361

#define WM8994_AIF1_TRI_WIDTH 1 /* AIF1_TRI */

2362

#define WM8994_AIF1_MSTR 0x4000 /* AIF1_MSTR */

2363

#define WM8994_AIF1_MSTR_MASK 0x4000 /* AIF1_MSTR */

2364

#define WM8994_AIF1_MSTR_SHIFT 14 /* AIF1_MSTR */

2365

#define WM8994_AIF1_MSTR_WIDTH 1 /* AIF1_MSTR */

2366

#define WM8994_AIF1_CLK_FRC 0x2000 /* AIF1_CLK_FRC */

2367

#define WM8994_AIF1_CLK_FRC_MASK 0x2000 /* AIF1_CLK_FRC */

2368

#define WM8994_AIF1_CLK_FRC_SHIFT 13 /* AIF1_CLK_FRC */

2369

#define WM8994_AIF1_CLK_FRC_WIDTH 1 /* AIF1_CLK_FRC */

2370

#define WM8994_AIF1_LRCLK_FRC 0x1000 /* AIF1_LRCLK_FRC */

2371

#define WM8994_AIF1_LRCLK_FRC_MASK 0x1000 /* AIF1_LRCLK_FRC */

2372

#define WM8994_AIF1_LRCLK_FRC_SHIFT 12 /* AIF1_LRCLK_FRC */

2373

#define WM8994_AIF1_LRCLK_FRC_WIDTH 1 /* AIF1_LRCLK_FRC */

2374

2375

/*

2376

* R771 (0x303) - AIF1 BCLK

2377

*/

2378

#define WM8994_AIF1_BCLK_DIV_MASK 0x01F0 /* AIF1_BCLK_DIV - [8:4] */

2379

#define WM8994_AIF1_BCLK_DIV_SHIFT 4 /* AIF1_BCLK_DIV - [8:4] */

2380

#define WM8994_AIF1_BCLK_DIV_WIDTH 5 /* AIF1_BCLK_DIV - [8:4] */

2381

2382

/*

2383

* R772 (0x304) - AIF1ADC LRCLK

2384

*/

2385

#define WM8994_AIF1ADC_LRCLK_DIR 0x0800 /* AIF1ADC_LRCLK_DIR */

2386

#define WM8994_AIF1ADC_LRCLK_DIR_MASK 0x0800 /* AIF1ADC_LRCLK_DIR */

2387

#define WM8994_AIF1ADC_LRCLK_DIR_SHIFT 11 /* AIF1ADC_LRCLK_DIR */

2388

#define WM8994_AIF1ADC_LRCLK_DIR_WIDTH 1 /* AIF1ADC_LRCLK_DIR */

2389

#define WM8994_AIF1ADC_RATE_MASK 0x07FF /* AIF1ADC_RATE - [10:0] */

2390

#define WM8994_AIF1ADC_RATE_SHIFT 0 /* AIF1ADC_RATE - [10:0] */

2391

#define WM8994_AIF1ADC_RATE_WIDTH 11 /* AIF1ADC_RATE - [10:0] */

2392

2393

/*

2394

* R773 (0x305) - AIF1DAC LRCLK

2395

*/

2396

#define WM8994_AIF1DAC_LRCLK_DIR 0x0800 /* AIF1DAC_LRCLK_DIR */

2397

#define WM8994_AIF1DAC_LRCLK_DIR_MASK 0x0800 /* AIF1DAC_LRCLK_DIR */

2398

#define WM8994_AIF1DAC_LRCLK_DIR_SHIFT 11 /* AIF1DAC_LRCLK_DIR */

2399

#define WM8994_AIF1DAC_LRCLK_DIR_WIDTH 1 /* AIF1DAC_LRCLK_DIR */

2400

#define WM8994_AIF1DAC_RATE_MASK 0x07FF /* AIF1DAC_RATE - [10:0] */

2401

#define WM8994_AIF1DAC_RATE_SHIFT 0 /* AIF1DAC_RATE - [10:0] */

2402

#define WM8994_AIF1DAC_RATE_WIDTH 11 /* AIF1DAC_RATE - [10:0] */

2403

2404

/*

2405

* R774 (0x306) - AIF1DAC Data

2406

*/

2407

#define WM8994_AIF1DACL_DAT_INV 0x0002 /* AIF1DACL_DAT_INV */

2408

#define WM8994_AIF1DACL_DAT_INV_MASK 0x0002 /* AIF1DACL_DAT_INV */

2409

#define WM8994_AIF1DACL_DAT_INV_SHIFT 1 /* AIF1DACL_DAT_INV */

2410

#define WM8994_AIF1DACL_DAT_INV_WIDTH 1 /* AIF1DACL_DAT_INV */

2411

#define WM8994_AIF1DACR_DAT_INV 0x0001 /* AIF1DACR_DAT_INV */

2412

#define WM8994_AIF1DACR_DAT_INV_MASK 0x0001 /* AIF1DACR_DAT_INV */

2413

#define WM8994_AIF1DACR_DAT_INV_SHIFT 0 /* AIF1DACR_DAT_INV */

2414

#define WM8994_AIF1DACR_DAT_INV_WIDTH 1 /* AIF1DACR_DAT_INV */

2415

2416

/*

2417

* R775 (0x307) - AIF1ADC Data

2418

*/

2419

#define WM8994_AIF1ADCL_DAT_INV 0x0002 /* AIF1ADCL_DAT_INV */

2420

#define WM8994_AIF1ADCL_DAT_INV_MASK 0x0002 /* AIF1ADCL_DAT_INV */

2421

#define WM8994_AIF1ADCL_DAT_INV_SHIFT 1 /* AIF1ADCL_DAT_INV */

2422

#define WM8994_AIF1ADCL_DAT_INV_WIDTH 1 /* AIF1ADCL_DAT_INV */

2423

#define WM8994_AIF1ADCR_DAT_INV 0x0001 /* AIF1ADCR_DAT_INV */

2424

#define WM8994_AIF1ADCR_DAT_INV_MASK 0x0001 /* AIF1ADCR_DAT_INV */

2425

#define WM8994_AIF1ADCR_DAT_INV_SHIFT 0 /* AIF1ADCR_DAT_INV */

2426

#define WM8994_AIF1ADCR_DAT_INV_WIDTH 1 /* AIF1ADCR_DAT_INV */

2427

2428

/*

2429

* R784 (0x310) - AIF2 Control (1)

2430

*/

2431

#define WM8994_AIF2ADCL_SRC 0x8000 /* AIF2ADCL_SRC */

2432

#define WM8994_AIF2ADCL_SRC_MASK 0x8000 /* AIF2ADCL_SRC */

2433

#define WM8994_AIF2ADCL_SRC_SHIFT 15 /* AIF2ADCL_SRC */

2434

#define WM8994_AIF2ADCL_SRC_WIDTH 1 /* AIF2ADCL_SRC */

2435

#define WM8994_AIF2ADCR_SRC 0x4000 /* AIF2ADCR_SRC */

2436

#define WM8994_AIF2ADCR_SRC_MASK 0x4000 /* AIF2ADCR_SRC */

2437

#define WM8994_AIF2ADCR_SRC_SHIFT 14 /* AIF2ADCR_SRC */

2438

#define WM8994_AIF2ADCR_SRC_WIDTH 1 /* AIF2ADCR_SRC */

2439

#define WM8994_AIF2ADC_TDM 0x2000 /* AIF2ADC_TDM */

2440

#define WM8994_AIF2ADC_TDM_MASK 0x2000 /* AIF2ADC_TDM */

2441

#define WM8994_AIF2ADC_TDM_SHIFT 13 /* AIF2ADC_TDM */

2442

#define WM8994_AIF2ADC_TDM_WIDTH 1 /* AIF2ADC_TDM */

2443

#define WM8994_AIF2ADC_TDM_CHAN 0x1000 /* AIF2ADC_TDM_CHAN */

2444

#define WM8994_AIF2ADC_TDM_CHAN_MASK 0x1000 /* AIF2ADC_TDM_CHAN */

2445

#define WM8994_AIF2ADC_TDM_CHAN_SHIFT 12 /* AIF2ADC_TDM_CHAN */

2446

#define WM8994_AIF2ADC_TDM_CHAN_WIDTH 1 /* AIF2ADC_TDM_CHAN */

2447

#define WM8994_AIF2_BCLK_INV 0x0100 /* AIF2_BCLK_INV */

2448

#define WM8994_AIF2_BCLK_INV_MASK 0x0100 /* AIF2_BCLK_INV */

2449

#define WM8994_AIF2_BCLK_INV_SHIFT 8 /* AIF2_BCLK_INV */

2450

#define WM8994_AIF2_BCLK_INV_WIDTH 1 /* AIF2_BCLK_INV */

2451

#define WM8994_AIF2_LRCLK_INV 0x0080 /* AIF2_LRCLK_INV */

2452

#define WM8994_AIF2_LRCLK_INV_MASK 0x0080 /* AIF2_LRCLK_INV */

2453

#define WM8994_AIF2_LRCLK_INV_SHIFT 7 /* AIF2_LRCLK_INV */

2454

#define WM8994_AIF2_LRCLK_INV_WIDTH 1 /* AIF2_LRCLK_INV */

2455

#define WM8994_AIF2_WL_MASK 0x0060 /* AIF2_WL - [6:5] */

2456

#define WM8994_AIF2_WL_SHIFT 5 /* AIF2_WL - [6:5] */

2457

#define WM8994_AIF2_WL_WIDTH 2 /* AIF2_WL - [6:5] */

2458

#define WM8994_AIF2_FMT_MASK 0x0018 /* AIF2_FMT - [4:3] */

2459

#define WM8994_AIF2_FMT_SHIFT 3 /* AIF2_FMT - [4:3] */

2460

#define WM8994_AIF2_FMT_WIDTH 2 /* AIF2_FMT - [4:3] */

2461

2462

/*

2463

* R785 (0x311) - AIF2 Control (2)

2464

*/

2465

#define WM8994_AIF2DACL_SRC 0x8000 /* AIF2DACL_SRC */

2466

#define WM8994_AIF2DACL_SRC_MASK 0x8000 /* AIF2DACL_SRC */

2467

#define WM8994_AIF2DACL_SRC_SHIFT 15 /* AIF2DACL_SRC */

2468

#define WM8994_AIF2DACL_SRC_WIDTH 1 /* AIF2DACL_SRC */

2469

#define WM8994_AIF2DACR_SRC 0x4000 /* AIF2DACR_SRC */

2470

#define WM8994_AIF2DACR_SRC_MASK 0x4000 /* AIF2DACR_SRC */

2471

#define WM8994_AIF2DACR_SRC_SHIFT 14 /* AIF2DACR_SRC */

2472

#define WM8994_AIF2DACR_SRC_WIDTH 1 /* AIF2DACR_SRC */

2473

#define WM8994_AIF2DAC_TDM 0x2000 /* AIF2DAC_TDM */

2474

#define WM8994_AIF2DAC_TDM_MASK 0x2000 /* AIF2DAC_TDM */

2475

#define WM8994_AIF2DAC_TDM_SHIFT 13 /* AIF2DAC_TDM */

2476

#define WM8994_AIF2DAC_TDM_WIDTH 1 /* AIF2DAC_TDM */

2477

#define WM8994_AIF2DAC_TDM_CHAN 0x1000 /* AIF2DAC_TDM_CHAN */

2478

#define WM8994_AIF2DAC_TDM_CHAN_MASK 0x1000 /* AIF2DAC_TDM_CHAN */

2479

#define WM8994_AIF2DAC_TDM_CHAN_SHIFT 12 /* AIF2DAC_TDM_CHAN */

2480

#define WM8994_AIF2DAC_TDM_CHAN_WIDTH 1 /* AIF2DAC_TDM_CHAN */

2481

#define WM8994_AIF2DAC_BOOST_MASK 0x0C00 /* AIF2DAC_BOOST - [11:10] */

2482

#define WM8994_AIF2DAC_BOOST_SHIFT 10 /* AIF2DAC_BOOST - [11:10] */

2483

#define WM8994_AIF2DAC_BOOST_WIDTH 2 /* AIF2DAC_BOOST - [11:10] */

2484

#define WM8994_AIF2_MONO 0x0100 /* AIF2_MONO */

2485

#define WM8994_AIF2_MONO_MASK 0x0100 /* AIF2_MONO */

2486

#define WM8994_AIF2_MONO_SHIFT 8 /* AIF2_MONO */

2487

#define WM8994_AIF2_MONO_WIDTH 1 /* AIF2_MONO */

2488

#define WM8994_AIF2DAC_COMP 0x0010 /* AIF2DAC_COMP */

2489

#define WM8994_AIF2DAC_COMP_MASK 0x0010 /* AIF2DAC_COMP */

2490

#define WM8994_AIF2DAC_COMP_SHIFT 4 /* AIF2DAC_COMP */

2491

#define WM8994_AIF2DAC_COMP_WIDTH 1 /* AIF2DAC_COMP */

2492

#define WM8994_AIF2DAC_COMPMODE 0x0008 /* AIF2DAC_COMPMODE */

2493

#define WM8994_AIF2DAC_COMPMODE_MASK 0x0008 /* AIF2DAC_COMPMODE */

2494

#define WM8994_AIF2DAC_COMPMODE_SHIFT 3 /* AIF2DAC_COMPMODE */

2495

#define WM8994_AIF2DAC_COMPMODE_WIDTH 1 /* AIF2DAC_COMPMODE */

2496

#define WM8994_AIF2ADC_COMP 0x0004 /* AIF2ADC_COMP */

2497

#define WM8994_AIF2ADC_COMP_MASK 0x0004 /* AIF2ADC_COMP */

2498

#define WM8994_AIF2ADC_COMP_SHIFT 2 /* AIF2ADC_COMP */

2499

#define WM8994_AIF2ADC_COMP_WIDTH 1 /* AIF2ADC_COMP */

2500

#define WM8994_AIF2ADC_COMPMODE 0x0002 /* AIF2ADC_COMPMODE */

2501

#define WM8994_AIF2ADC_COMPMODE_MASK 0x0002 /* AIF2ADC_COMPMODE */

2502

#define WM8994_AIF2ADC_COMPMODE_SHIFT 1 /* AIF2ADC_COMPMODE */

2503

#define WM8994_AIF2ADC_COMPMODE_WIDTH 1 /* AIF2ADC_COMPMODE */

2504

#define WM8994_AIF2_LOOPBACK 0x0001 /* AIF2_LOOPBACK */

2505

#define WM8994_AIF2_LOOPBACK_MASK 0x0001 /* AIF2_LOOPBACK */

2506

#define WM8994_AIF2_LOOPBACK_SHIFT 0 /* AIF2_LOOPBACK */

2507

#define WM8994_AIF2_LOOPBACK_WIDTH 1 /* AIF2_LOOPBACK */

2508

2509

/*

2510

* R786 (0x312) - AIF2 Master/Slave

2511

*/

2512

#define WM8994_AIF2_TRI 0x8000 /* AIF2_TRI */

2513

#define WM8994_AIF2_TRI_MASK 0x8000 /* AIF2_TRI */

2514

#define WM8994_AIF2_TRI_SHIFT 15 /* AIF2_TRI */

2515

#define WM8994_AIF2_TRI_WIDTH 1 /* AIF2_TRI */

2516

#define WM8994_AIF2_MSTR 0x4000 /* AIF2_MSTR */

2517

#define WM8994_AIF2_MSTR_MASK 0x4000 /* AIF2_MSTR */

2518

#define WM8994_AIF2_MSTR_SHIFT 14 /* AIF2_MSTR */

2519

#define WM8994_AIF2_MSTR_WIDTH 1 /* AIF2_MSTR */

2520

#define WM8994_AIF2_CLK_FRC 0x2000 /* AIF2_CLK_FRC */

2521

#define WM8994_AIF2_CLK_FRC_MASK 0x2000 /* AIF2_CLK_FRC */

2522

#define WM8994_AIF2_CLK_FRC_SHIFT 13 /* AIF2_CLK_FRC */

2523

#define WM8994_AIF2_CLK_FRC_WIDTH 1 /* AIF2_CLK_FRC */

2524

#define WM8994_AIF2_LRCLK_FRC 0x1000 /* AIF2_LRCLK_FRC */

2525

#define WM8994_AIF2_LRCLK_FRC_MASK 0x1000 /* AIF2_LRCLK_FRC */

2526

#define WM8994_AIF2_LRCLK_FRC_SHIFT 12 /* AIF2_LRCLK_FRC */

2527

#define WM8994_AIF2_LRCLK_FRC_WIDTH 1 /* AIF2_LRCLK_FRC */

2528

2529

/*

2530

* R787 (0x313) - AIF2 BCLK

2531

*/

2532

#define WM8994_AIF2_BCLK_DIV_MASK 0x01F0 /* AIF2_BCLK_DIV - [8:4] */

2533

#define WM8994_AIF2_BCLK_DIV_SHIFT 4 /* AIF2_BCLK_DIV - [8:4] */

2534

#define WM8994_AIF2_BCLK_DIV_WIDTH 5 /* AIF2_BCLK_DIV - [8:4] */

2535

2536

/*

2537

* R788 (0x314) - AIF2ADC LRCLK

2538

*/

2539

#define WM8994_AIF2ADC_LRCLK_DIR 0x0800 /* AIF2ADC_LRCLK_DIR */

2540

#define WM8994_AIF2ADC_LRCLK_DIR_MASK 0x0800 /* AIF2ADC_LRCLK_DIR */

2541

#define WM8994_AIF2ADC_LRCLK_DIR_SHIFT 11 /* AIF2ADC_LRCLK_DIR */

2542

#define WM8994_AIF2ADC_LRCLK_DIR_WIDTH 1 /* AIF2ADC_LRCLK_DIR */

2543

#define WM8994_AIF2ADC_RATE_MASK 0x07FF /* AIF2ADC_RATE - [10:0] */

2544

#define WM8994_AIF2ADC_RATE_SHIFT 0 /* AIF2ADC_RATE - [10:0] */

2545

#define WM8994_AIF2ADC_RATE_WIDTH 11 /* AIF2ADC_RATE - [10:0] */

2546

2547

/*

2548

* R789 (0x315) - AIF2DAC LRCLK

2549

*/

2550

#define WM8994_AIF2DAC_LRCLK_DIR 0x0800 /* AIF2DAC_LRCLK_DIR */

2551

#define WM8994_AIF2DAC_LRCLK_DIR_MASK 0x0800 /* AIF2DAC_LRCLK_DIR */

2552

#define WM8994_AIF2DAC_LRCLK_DIR_SHIFT 11 /* AIF2DAC_LRCLK_DIR */

2553

#define WM8994_AIF2DAC_LRCLK_DIR_WIDTH 1 /* AIF2DAC_LRCLK_DIR */

2554

#define WM8994_AIF2DAC_RATE_MASK 0x07FF /* AIF2DAC_RATE - [10:0] */

2555

#define WM8994_AIF2DAC_RATE_SHIFT 0 /* AIF2DAC_RATE - [10:0] */

2556

#define WM8994_AIF2DAC_RATE_WIDTH 11 /* AIF2DAC_RATE - [10:0] */

2557

2558

/*

2559

* R790 (0x316) - AIF2DAC Data

2560

*/

2561

#define WM8994_AIF2DACL_DAT_INV 0x0002 /* AIF2DACL_DAT_INV */

2562

#define WM8994_AIF2DACL_DAT_INV_MASK 0x0002 /* AIF2DACL_DAT_INV */

2563

#define WM8994_AIF2DACL_DAT_INV_SHIFT 1 /* AIF2DACL_DAT_INV */

2564

#define WM8994_AIF2DACL_DAT_INV_WIDTH 1 /* AIF2DACL_DAT_INV */

2565

#define WM8994_AIF2DACR_DAT_INV 0x0001 /* AIF2DACR_DAT_INV */

2566

#define WM8994_AIF2DACR_DAT_INV_MASK 0x0001 /* AIF2DACR_DAT_INV */

2567

#define WM8994_AIF2DACR_DAT_INV_SHIFT 0 /* AIF2DACR_DAT_INV */

2568

#define WM8994_AIF2DACR_DAT_INV_WIDTH 1 /* AIF2DACR_DAT_INV */

2569

2570

/*

2571

* R791 (0x317) - AIF2ADC Data

2572

*/

2573

#define WM8994_AIF2ADCL_DAT_INV 0x0002 /* AIF2ADCL_DAT_INV */

2574

#define WM8994_AIF2ADCL_DAT_INV_MASK 0x0002 /* AIF2ADCL_DAT_INV */

2575

#define WM8994_AIF2ADCL_DAT_INV_SHIFT 1 /* AIF2ADCL_DAT_INV */

2576

#define WM8994_AIF2ADCL_DAT_INV_WIDTH 1 /* AIF2ADCL_DAT_INV */

2577

#define WM8994_AIF2ADCR_DAT_INV 0x0001 /* AIF2ADCR_DAT_INV */

2578

#define WM8994_AIF2ADCR_DAT_INV_MASK 0x0001 /* AIF2ADCR_DAT_INV */

2579

#define WM8994_AIF2ADCR_DAT_INV_SHIFT 0 /* AIF2ADCR_DAT_INV */

2580

#define WM8994_AIF2ADCR_DAT_INV_WIDTH 1 /* AIF2ADCR_DAT_INV */

2581

2582

/*

Mark Brown

c4431df

2010-11-26 15:21:07 +0000

[diff] [blame]

2583

* R800 (0x320) - AIF3 Control (1)

2584

*/

2585

#define WM8958_AIF3_LRCLK_INV 0x0080 /* AIF3_LRCLK_INV */

2586

#define WM8958_AIF3_LRCLK_INV_MASK 0x0080 /* AIF3_LRCLK_INV */

2587

#define WM8958_AIF3_LRCLK_INV_SHIFT 7 /* AIF3_LRCLK_INV */

2588

#define WM8958_AIF3_LRCLK_INV_WIDTH 1 /* AIF3_LRCLK_INV */

2589

#define WM8958_AIF3_WL_MASK 0x0060 /* AIF3_WL - [6:5] */

2590

#define WM8958_AIF3_WL_SHIFT 5 /* AIF3_WL - [6:5] */

2591

#define WM8958_AIF3_WL_WIDTH 2 /* AIF3_WL - [6:5] */

2592

#define WM8958_AIF3_FMT_MASK 0x0018 /* AIF3_FMT - [4:3] */

2593

#define WM8958_AIF3_FMT_SHIFT 3 /* AIF3_FMT - [4:3] */

2594

#define WM8958_AIF3_FMT_WIDTH 2 /* AIF3_FMT - [4:3] */

2595

2596

/*

2597

* R801 (0x321) - AIF3 Control (2)

2598

*/

2599

#define WM8958_AIF3DAC_BOOST_MASK 0x0C00 /* AIF3DAC_BOOST - [11:10] */

2600

#define WM8958_AIF3DAC_BOOST_SHIFT 10 /* AIF3DAC_BOOST - [11:10] */

2601

#define WM8958_AIF3DAC_BOOST_WIDTH 2 /* AIF3DAC_BOOST - [11:10] */

2602

#define WM8958_AIF3DAC_COMP 0x0010 /* AIF3DAC_COMP */

2603

#define WM8958_AIF3DAC_COMP_MASK 0x0010 /* AIF3DAC_COMP */

2604

#define WM8958_AIF3DAC_COMP_SHIFT 4 /* AIF3DAC_COMP */

2605

#define WM8958_AIF3DAC_COMP_WIDTH 1 /* AIF3DAC_COMP */

2606

#define WM8958_AIF3DAC_COMPMODE 0x0008 /* AIF3DAC_COMPMODE */

2607

#define WM8958_AIF3DAC_COMPMODE_MASK 0x0008 /* AIF3DAC_COMPMODE */

2608

#define WM8958_AIF3DAC_COMPMODE_SHIFT 3 /* AIF3DAC_COMPMODE */

2609

#define WM8958_AIF3DAC_COMPMODE_WIDTH 1 /* AIF3DAC_COMPMODE */

2610

#define WM8958_AIF3ADC_COMP 0x0004 /* AIF3ADC_COMP */

2611

#define WM8958_AIF3ADC_COMP_MASK 0x0004 /* AIF3ADC_COMP */

2612

#define WM8958_AIF3ADC_COMP_SHIFT 2 /* AIF3ADC_COMP */

2613

#define WM8958_AIF3ADC_COMP_WIDTH 1 /* AIF3ADC_COMP */

2614

#define WM8958_AIF3ADC_COMPMODE 0x0002 /* AIF3ADC_COMPMODE */

2615

#define WM8958_AIF3ADC_COMPMODE_MASK 0x0002 /* AIF3ADC_COMPMODE */

2616

#define WM8958_AIF3ADC_COMPMODE_SHIFT 1 /* AIF3ADC_COMPMODE */

2617

#define WM8958_AIF3ADC_COMPMODE_WIDTH 1 /* AIF3ADC_COMPMODE */

2618

#define WM8958_AIF3_LOOPBACK 0x0001 /* AIF3_LOOPBACK */

2619

#define WM8958_AIF3_LOOPBACK_MASK 0x0001 /* AIF3_LOOPBACK */

2620

#define WM8958_AIF3_LOOPBACK_SHIFT 0 /* AIF3_LOOPBACK */

2621

#define WM8958_AIF3_LOOPBACK_WIDTH 1 /* AIF3_LOOPBACK */

2622

2623

/*

2624

* R802 (0x322) - AIF3DAC Data

2625

*/

2626

#define WM8958_AIF3DAC_DAT_INV 0x0001 /* AIF3DAC_DAT_INV */

2627

#define WM8958_AIF3DAC_DAT_INV_MASK 0x0001 /* AIF3DAC_DAT_INV */

2628

#define WM8958_AIF3DAC_DAT_INV_SHIFT 0 /* AIF3DAC_DAT_INV */

2629

#define WM8958_AIF3DAC_DAT_INV_WIDTH 1 /* AIF3DAC_DAT_INV */

2630

2631

/*

2632

* R803 (0x323) - AIF3ADC Data

2633

*/

2634

#define WM8958_AIF3ADC_DAT_INV 0x0001 /* AIF3ADC_DAT_INV */

2635

#define WM8958_AIF3ADC_DAT_INV_MASK 0x0001 /* AIF3ADC_DAT_INV */

2636

#define WM8958_AIF3ADC_DAT_INV_SHIFT 0 /* AIF3ADC_DAT_INV */

2637

#define WM8958_AIF3ADC_DAT_INV_WIDTH 1 /* AIF3ADC_DAT_INV */

2638

2639

/*

Mark Brown

1c4d3b70

2010-01-29 18:20:28 +0000

[diff] [blame]

2640

* R1024 (0x400) - AIF1 ADC1 Left Volume

2641

*/

2642

#define WM8994_AIF1ADC1_VU 0x0100 /* AIF1ADC1_VU */

2643

#define WM8994_AIF1ADC1_VU_MASK 0x0100 /* AIF1ADC1_VU */

2644

#define WM8994_AIF1ADC1_VU_SHIFT 8 /* AIF1ADC1_VU */

2645

#define WM8994_AIF1ADC1_VU_WIDTH 1 /* AIF1ADC1_VU */

2646

#define WM8994_AIF1ADC1L_VOL_MASK 0x00FF /* AIF1ADC1L_VOL - [7:0] */

2647

#define WM8994_AIF1ADC1L_VOL_SHIFT 0 /* AIF1ADC1L_VOL - [7:0] */

2648

#define WM8994_AIF1ADC1L_VOL_WIDTH 8 /* AIF1ADC1L_VOL - [7:0] */

2649

2650

/*

2651

* R1025 (0x401) - AIF1 ADC1 Right Volume

2652

*/

2653

#define WM8994_AIF1ADC1_VU 0x0100 /* AIF1ADC1_VU */

2654

#define WM8994_AIF1ADC1_VU_MASK 0x0100 /* AIF1ADC1_VU */

2655

#define WM8994_AIF1ADC1_VU_SHIFT 8 /* AIF1ADC1_VU */

2656

#define WM8994_AIF1ADC1_VU_WIDTH 1 /* AIF1ADC1_VU */

2657

#define WM8994_AIF1ADC1R_VOL_MASK 0x00FF /* AIF1ADC1R_VOL - [7:0] */

2658

#define WM8994_AIF1ADC1R_VOL_SHIFT 0 /* AIF1ADC1R_VOL - [7:0] */

2659

#define WM8994_AIF1ADC1R_VOL_WIDTH 8 /* AIF1ADC1R_VOL - [7:0] */

2660

2661

/*

2662

* R1026 (0x402) - AIF1 DAC1 Left Volume

2663

*/

2664

#define WM8994_AIF1DAC1_VU 0x0100 /* AIF1DAC1_VU */

2665

#define WM8994_AIF1DAC1_VU_MASK 0x0100 /* AIF1DAC1_VU */

2666

#define WM8994_AIF1DAC1_VU_SHIFT 8 /* AIF1DAC1_VU */

2667

#define WM8994_AIF1DAC1_VU_WIDTH 1 /* AIF1DAC1_VU */

2668

#define WM8994_AIF1DAC1L_VOL_MASK 0x00FF /* AIF1DAC1L_VOL - [7:0] */

2669

#define WM8994_AIF1DAC1L_VOL_SHIFT 0 /* AIF1DAC1L_VOL - [7:0] */

2670

#define WM8994_AIF1DAC1L_VOL_WIDTH 8 /* AIF1DAC1L_VOL - [7:0] */

2671

2672

/*

2673

* R1027 (0x403) - AIF1 DAC1 Right Volume

2674

*/

2675

#define WM8994_AIF1DAC1_VU 0x0100 /* AIF1DAC1_VU */

2676

#define WM8994_AIF1DAC1_VU_MASK 0x0100 /* AIF1DAC1_VU */

2677

#define WM8994_AIF1DAC1_VU_SHIFT 8 /* AIF1DAC1_VU */

2678

#define WM8994_AIF1DAC1_VU_WIDTH 1 /* AIF1DAC1_VU */

2679

#define WM8994_AIF1DAC1R_VOL_MASK 0x00FF /* AIF1DAC1R_VOL - [7:0] */

2680

#define WM8994_AIF1DAC1R_VOL_SHIFT 0 /* AIF1DAC1R_VOL - [7:0] */

2681

#define WM8994_AIF1DAC1R_VOL_WIDTH 8 /* AIF1DAC1R_VOL - [7:0] */

2682

2683

/*

2684

* R1028 (0x404) - AIF1 ADC2 Left Volume

2685

*/

2686

#define WM8994_AIF1ADC2_VU 0x0100 /* AIF1ADC2_VU */

2687

#define WM8994_AIF1ADC2_VU_MASK 0x0100 /* AIF1ADC2_VU */

2688

#define WM8994_AIF1ADC2_VU_SHIFT 8 /* AIF1ADC2_VU */

2689

#define WM8994_AIF1ADC2_VU_WIDTH 1 /* AIF1ADC2_VU */

2690

#define WM8994_AIF1ADC2L_VOL_MASK 0x00FF /* AIF1ADC2L_VOL - [7:0] */

2691

#define WM8994_AIF1ADC2L_VOL_SHIFT 0 /* AIF1ADC2L_VOL - [7:0] */

2692

#define WM8994_AIF1ADC2L_VOL_WIDTH 8 /* AIF1ADC2L_VOL - [7:0] */

2693

2694

/*

2695

* R1029 (0x405) - AIF1 ADC2 Right Volume

2696

*/

2697

#define WM8994_AIF1ADC2_VU 0x0100 /* AIF1ADC2_VU */

2698

#define WM8994_AIF1ADC2_VU_MASK 0x0100 /* AIF1ADC2_VU */

2699

#define WM8994_AIF1ADC2_VU_SHIFT 8 /* AIF1ADC2_VU */

2700

#define WM8994_AIF1ADC2_VU_WIDTH 1 /* AIF1ADC2_VU */

2701

#define WM8994_AIF1ADC2R_VOL_MASK 0x00FF /* AIF1ADC2R_VOL - [7:0] */

2702

#define WM8994_AIF1ADC2R_VOL_SHIFT 0 /* AIF1ADC2R_VOL - [7:0] */

2703

#define WM8994_AIF1ADC2R_VOL_WIDTH 8 /* AIF1ADC2R_VOL - [7:0] */

2704

2705

/*

2706

* R1030 (0x406) - AIF1 DAC2 Left Volume

2707

*/

2708

#define WM8994_AIF1DAC2_VU 0x0100 /* AIF1DAC2_VU */

2709

#define WM8994_AIF1DAC2_VU_MASK 0x0100 /* AIF1DAC2_VU */

2710

#define WM8994_AIF1DAC2_VU_SHIFT 8 /* AIF1DAC2_VU */

2711

#define WM8994_AIF1DAC2_VU_WIDTH 1 /* AIF1DAC2_VU */

2712

#define WM8994_AIF1DAC2L_VOL_MASK 0x00FF /* AIF1DAC2L_VOL - [7:0] */

2713

#define WM8994_AIF1DAC2L_VOL_SHIFT 0 /* AIF1DAC2L_VOL - [7:0] */

2714

#define WM8994_AIF1DAC2L_VOL_WIDTH 8 /* AIF1DAC2L_VOL - [7:0] */

2715

2716

/*

2717

* R1031 (0x407) - AIF1 DAC2 Right Volume

2718

*/

2719

#define WM8994_AIF1DAC2_VU 0x0100 /* AIF1DAC2_VU */

2720

#define WM8994_AIF1DAC2_VU_MASK 0x0100 /* AIF1DAC2_VU */

2721

#define WM8994_AIF1DAC2_VU_SHIFT 8 /* AIF1DAC2_VU */

2722

#define WM8994_AIF1DAC2_VU_WIDTH 1 /* AIF1DAC2_VU */

2723

#define WM8994_AIF1DAC2R_VOL_MASK 0x00FF /* AIF1DAC2R_VOL - [7:0] */

2724

#define WM8994_AIF1DAC2R_VOL_SHIFT 0 /* AIF1DAC2R_VOL - [7:0] */

2725

#define WM8994_AIF1DAC2R_VOL_WIDTH 8 /* AIF1DAC2R_VOL - [7:0] */

2726

2727

/*

2728

* R1040 (0x410) - AIF1 ADC1 Filters

2729

*/

2730

#define WM8994_AIF1ADC_4FS 0x8000 /* AIF1ADC_4FS */

2731

#define WM8994_AIF1ADC_4FS_MASK 0x8000 /* AIF1ADC_4FS */

2732

#define WM8994_AIF1ADC_4FS_SHIFT 15 /* AIF1ADC_4FS */

2733

#define WM8994_AIF1ADC_4FS_WIDTH 1 /* AIF1ADC_4FS */

2734

#define WM8994_AIF1ADC1_HPF_CUT_MASK 0x6000 /* AIF1ADC1_HPF_CUT - [14:13] */

2735

#define WM8994_AIF1ADC1_HPF_CUT_SHIFT 13 /* AIF1ADC1_HPF_CUT - [14:13] */

2736

#define WM8994_AIF1ADC1_HPF_CUT_WIDTH 2 /* AIF1ADC1_HPF_CUT - [14:13] */

2737

#define WM8994_AIF1ADC1L_HPF 0x1000 /* AIF1ADC1L_HPF */

2738

#define WM8994_AIF1ADC1L_HPF_MASK 0x1000 /* AIF1ADC1L_HPF */

2739

#define WM8994_AIF1ADC1L_HPF_SHIFT 12 /* AIF1ADC1L_HPF */

2740

#define WM8994_AIF1ADC1L_HPF_WIDTH 1 /* AIF1ADC1L_HPF */

2741

#define WM8994_AIF1ADC1R_HPF 0x0800 /* AIF1ADC1R_HPF */

2742

#define WM8994_AIF1ADC1R_HPF_MASK 0x0800 /* AIF1ADC1R_HPF */

2743

#define WM8994_AIF1ADC1R_HPF_SHIFT 11 /* AIF1ADC1R_HPF */

2744

#define WM8994_AIF1ADC1R_HPF_WIDTH 1 /* AIF1ADC1R_HPF */

2745

2746

/*

2747

* R1041 (0x411) - AIF1 ADC2 Filters

2748

*/

2749

#define WM8994_AIF1ADC2_HPF_CUT_MASK 0x6000 /* AIF1ADC2_HPF_CUT - [14:13] */

2750

#define WM8994_AIF1ADC2_HPF_CUT_SHIFT 13 /* AIF1ADC2_HPF_CUT - [14:13] */

2751

#define WM8994_AIF1ADC2_HPF_CUT_WIDTH 2 /* AIF1ADC2_HPF_CUT - [14:13] */

2752

#define WM8994_AIF1ADC2L_HPF 0x1000 /* AIF1ADC2L_HPF */

2753

#define WM8994_AIF1ADC2L_HPF_MASK 0x1000 /* AIF1ADC2L_HPF */

2754

#define WM8994_AIF1ADC2L_HPF_SHIFT 12 /* AIF1ADC2L_HPF */

2755

#define WM8994_AIF1ADC2L_HPF_WIDTH 1 /* AIF1ADC2L_HPF */

2756

#define WM8994_AIF1ADC2R_HPF 0x0800 /* AIF1ADC2R_HPF */

2757

#define WM8994_AIF1ADC2R_HPF_MASK 0x0800 /* AIF1ADC2R_HPF */

2758

#define WM8994_AIF1ADC2R_HPF_SHIFT 11 /* AIF1ADC2R_HPF */

2759

#define WM8994_AIF1ADC2R_HPF_WIDTH 1 /* AIF1ADC2R_HPF */

2760

2761

/*

2762

* R1056 (0x420) - AIF1 DAC1 Filters (1)

2763

*/

2764

#define WM8994_AIF1DAC1_MUTE 0x0200 /* AIF1DAC1_MUTE */

2765

#define WM8994_AIF1DAC1_MUTE_MASK 0x0200 /* AIF1DAC1_MUTE */

2766

#define WM8994_AIF1DAC1_MUTE_SHIFT 9 /* AIF1DAC1_MUTE */

2767

#define WM8994_AIF1DAC1_MUTE_WIDTH 1 /* AIF1DAC1_MUTE */

2768

#define WM8994_AIF1DAC1_MONO 0x0080 /* AIF1DAC1_MONO */

2769

#define WM8994_AIF1DAC1_MONO_MASK 0x0080 /* AIF1DAC1_MONO */

2770

#define WM8994_AIF1DAC1_MONO_SHIFT 7 /* AIF1DAC1_MONO */

2771

#define WM8994_AIF1DAC1_MONO_WIDTH 1 /* AIF1DAC1_MONO */

2772

#define WM8994_AIF1DAC1_MUTERATE 0x0020 /* AIF1DAC1_MUTERATE */

2773

#define WM8994_AIF1DAC1_MUTERATE_MASK 0x0020 /* AIF1DAC1_MUTERATE */

2774

#define WM8994_AIF1DAC1_MUTERATE_SHIFT 5 /* AIF1DAC1_MUTERATE */

2775

#define WM8994_AIF1DAC1_MUTERATE_WIDTH 1 /* AIF1DAC1_MUTERATE */

2776

#define WM8994_AIF1DAC1_UNMUTE_RAMP 0x0010 /* AIF1DAC1_UNMUTE_RAMP */

2777

#define WM8994_AIF1DAC1_UNMUTE_RAMP_MASK 0x0010 /* AIF1DAC1_UNMUTE_RAMP */

2778

#define WM8994_AIF1DAC1_UNMUTE_RAMP_SHIFT 4 /* AIF1DAC1_UNMUTE_RAMP */

2779

#define WM8994_AIF1DAC1_UNMUTE_RAMP_WIDTH 1 /* AIF1DAC1_UNMUTE_RAMP */

2780

#define WM8994_AIF1DAC1_DEEMP_MASK 0x0006 /* AIF1DAC1_DEEMP - [2:1] */

2781

#define WM8994_AIF1DAC1_DEEMP_SHIFT 1 /* AIF1DAC1_DEEMP - [2:1] */

2782

#define WM8994_AIF1DAC1_DEEMP_WIDTH 2 /* AIF1DAC1_DEEMP - [2:1] */

2783

2784

/*

2785

* R1057 (0x421) - AIF1 DAC1 Filters (2)

2786

*/

2787

#define WM8994_AIF1DAC1_3D_GAIN_MASK 0x3E00 /* AIF1DAC1_3D_GAIN - [13:9] */

2788

#define WM8994_AIF1DAC1_3D_GAIN_SHIFT 9 /* AIF1DAC1_3D_GAIN - [13:9] */

2789

#define WM8994_AIF1DAC1_3D_GAIN_WIDTH 5 /* AIF1DAC1_3D_GAIN - [13:9] */

2790

#define WM8994_AIF1DAC1_3D_ENA 0x0100 /* AIF1DAC1_3D_ENA */

2791

#define WM8994_AIF1DAC1_3D_ENA_MASK 0x0100 /* AIF1DAC1_3D_ENA */

2792

#define WM8994_AIF1DAC1_3D_ENA_SHIFT 8 /* AIF1DAC1_3D_ENA */

2793

#define WM8994_AIF1DAC1_3D_ENA_WIDTH 1 /* AIF1DAC1_3D_ENA */

2794

2795

/*

2796

* R1058 (0x422) - AIF1 DAC2 Filters (1)

2797

*/

2798

#define WM8994_AIF1DAC2_MUTE 0x0200 /* AIF1DAC2_MUTE */

2799

#define WM8994_AIF1DAC2_MUTE_MASK 0x0200 /* AIF1DAC2_MUTE */

2800

#define WM8994_AIF1DAC2_MUTE_SHIFT 9 /* AIF1DAC2_MUTE */

2801

#define WM8994_AIF1DAC2_MUTE_WIDTH 1 /* AIF1DAC2_MUTE */

2802

#define WM8994_AIF1DAC2_MONO 0x0080 /* AIF1DAC2_MONO */

2803

#define WM8994_AIF1DAC2_MONO_MASK 0x0080 /* AIF1DAC2_MONO */

2804

#define WM8994_AIF1DAC2_MONO_SHIFT 7 /* AIF1DAC2_MONO */

2805

#define WM8994_AIF1DAC2_MONO_WIDTH 1 /* AIF1DAC2_MONO */

2806

#define WM8994_AIF1DAC2_MUTERATE 0x0020 /* AIF1DAC2_MUTERATE */

2807

#define WM8994_AIF1DAC2_MUTERATE_MASK 0x0020 /* AIF1DAC2_MUTERATE */

2808

#define WM8994_AIF1DAC2_MUTERATE_SHIFT 5 /* AIF1DAC2_MUTERATE */

2809

#define WM8994_AIF1DAC2_MUTERATE_WIDTH 1 /* AIF1DAC2_MUTERATE */

2810

#define WM8994_AIF1DAC2_UNMUTE_RAMP 0x0010 /* AIF1DAC2_UNMUTE_RAMP */

2811

#define WM8994_AIF1DAC2_UNMUTE_RAMP_MASK 0x0010 /* AIF1DAC2_UNMUTE_RAMP */

2812

#define WM8994_AIF1DAC2_UNMUTE_RAMP_SHIFT 4 /* AIF1DAC2_UNMUTE_RAMP */

2813

#define WM8994_AIF1DAC2_UNMUTE_RAMP_WIDTH 1 /* AIF1DAC2_UNMUTE_RAMP */

2814

#define WM8994_AIF1DAC2_DEEMP_MASK 0x0006 /* AIF1DAC2_DEEMP - [2:1] */

2815

#define WM8994_AIF1DAC2_DEEMP_SHIFT 1 /* AIF1DAC2_DEEMP - [2:1] */

2816

#define WM8994_AIF1DAC2_DEEMP_WIDTH 2 /* AIF1DAC2_DEEMP - [2:1] */

2817

2818

/*

2819

* R1059 (0x423) - AIF1 DAC2 Filters (2)

2820

*/

2821

#define WM8994_AIF1DAC2_3D_GAIN_MASK 0x3E00 /* AIF1DAC2_3D_GAIN - [13:9] */

2822

#define WM8994_AIF1DAC2_3D_GAIN_SHIFT 9 /* AIF1DAC2_3D_GAIN - [13:9] */

2823

#define WM8994_AIF1DAC2_3D_GAIN_WIDTH 5 /* AIF1DAC2_3D_GAIN - [13:9] */

2824

#define WM8994_AIF1DAC2_3D_ENA 0x0100 /* AIF1DAC2_3D_ENA */

2825

#define WM8994_AIF1DAC2_3D_ENA_MASK 0x0100 /* AIF1DAC2_3D_ENA */

2826

#define WM8994_AIF1DAC2_3D_ENA_SHIFT 8 /* AIF1DAC2_3D_ENA */

2827

#define WM8994_AIF1DAC2_3D_ENA_WIDTH 1 /* AIF1DAC2_3D_ENA */

2828

2829

/*

2830

* R1088 (0x440) - AIF1 DRC1 (1)

2831

*/

2832

#define WM8994_AIF1DRC1_SIG_DET_RMS_MASK 0xF800 /* AIF1DRC1_SIG_DET_RMS - [15:11] */

2833

#define WM8994_AIF1DRC1_SIG_DET_RMS_SHIFT 11 /* AIF1DRC1_SIG_DET_RMS - [15:11] */

2834

#define WM8994_AIF1DRC1_SIG_DET_RMS_WIDTH 5 /* AIF1DRC1_SIG_DET_RMS - [15:11] */

2835

#define WM8994_AIF1DRC1_SIG_DET_PK_MASK 0x0600 /* AIF1DRC1_SIG_DET_PK - [10:9] */

2836

#define WM8994_AIF1DRC1_SIG_DET_PK_SHIFT 9 /* AIF1DRC1_SIG_DET_PK - [10:9] */

2837

#define WM8994_AIF1DRC1_SIG_DET_PK_WIDTH 2 /* AIF1DRC1_SIG_DET_PK - [10:9] */

2838

#define WM8994_AIF1DRC1_NG_ENA 0x0100 /* AIF1DRC1_NG_ENA */

2839

#define WM8994_AIF1DRC1_NG_ENA_MASK 0x0100 /* AIF1DRC1_NG_ENA */

2840

#define WM8994_AIF1DRC1_NG_ENA_SHIFT 8 /* AIF1DRC1_NG_ENA */

2841

#define WM8994_AIF1DRC1_NG_ENA_WIDTH 1 /* AIF1DRC1_NG_ENA */

2842

#define WM8994_AIF1DRC1_SIG_DET_MODE 0x0080 /* AIF1DRC1_SIG_DET_MODE */

2843

#define WM8994_AIF1DRC1_SIG_DET_MODE_MASK 0x0080 /* AIF1DRC1_SIG_DET_MODE */

2844

#define WM8994_AIF1DRC1_SIG_DET_MODE_SHIFT 7 /* AIF1DRC1_SIG_DET_MODE */

2845

#define WM8994_AIF1DRC1_SIG_DET_MODE_WIDTH 1 /* AIF1DRC1_SIG_DET_MODE */

2846

#define WM8994_AIF1DRC1_SIG_DET 0x0040 /* AIF1DRC1_SIG_DET */

2847

#define WM8994_AIF1DRC1_SIG_DET_MASK 0x0040 /* AIF1DRC1_SIG_DET */

2848

#define WM8994_AIF1DRC1_SIG_DET_SHIFT 6 /* AIF1DRC1_SIG_DET */

2849

#define WM8994_AIF1DRC1_SIG_DET_WIDTH 1 /* AIF1DRC1_SIG_DET */

2850

#define WM8994_AIF1DRC1_KNEE2_OP_ENA 0x0020 /* AIF1DRC1_KNEE2_OP_ENA */

2851

#define WM8994_AIF1DRC1_KNEE2_OP_ENA_MASK 0x0020 /* AIF1DRC1_KNEE2_OP_ENA */

2852

#define WM8994_AIF1DRC1_KNEE2_OP_ENA_SHIFT 5 /* AIF1DRC1_KNEE2_OP_ENA */

2853

#define WM8994_AIF1DRC1_KNEE2_OP_ENA_WIDTH 1 /* AIF1DRC1_KNEE2_OP_ENA */

2854

#define WM8994_AIF1DRC1_QR 0x0010 /* AIF1DRC1_QR */

2855

#define WM8994_AIF1DRC1_QR_MASK 0x0010 /* AIF1DRC1_QR */

2856

#define WM8994_AIF1DRC1_QR_SHIFT 4 /* AIF1DRC1_QR */

2857

#define WM8994_AIF1DRC1_QR_WIDTH 1 /* AIF1DRC1_QR */

2858

#define WM8994_AIF1DRC1_ANTICLIP 0x0008 /* AIF1DRC1_ANTICLIP */

2859

#define WM8994_AIF1DRC1_ANTICLIP_MASK 0x0008 /* AIF1DRC1_ANTICLIP */

2860

#define WM8994_AIF1DRC1_ANTICLIP_SHIFT 3 /* AIF1DRC1_ANTICLIP */

2861

#define WM8994_AIF1DRC1_ANTICLIP_WIDTH 1 /* AIF1DRC1_ANTICLIP */

2862

#define WM8994_AIF1DAC1_DRC_ENA 0x0004 /* AIF1DAC1_DRC_ENA */

2863

#define WM8994_AIF1DAC1_DRC_ENA_MASK 0x0004 /* AIF1DAC1_DRC_ENA */

2864

#define WM8994_AIF1DAC1_DRC_ENA_SHIFT 2 /* AIF1DAC1_DRC_ENA */

2865

#define WM8994_AIF1DAC1_DRC_ENA_WIDTH 1 /* AIF1DAC1_DRC_ENA */

2866

#define WM8994_AIF1ADC1L_DRC_ENA 0x0002 /* AIF1ADC1L_DRC_ENA */

2867

#define WM8994_AIF1ADC1L_DRC_ENA_MASK 0x0002 /* AIF1ADC1L_DRC_ENA */

2868

#define WM8994_AIF1ADC1L_DRC_ENA_SHIFT 1 /* AIF1ADC1L_DRC_ENA */

2869

#define WM8994_AIF1ADC1L_DRC_ENA_WIDTH 1 /* AIF1ADC1L_DRC_ENA */

2870

#define WM8994_AIF1ADC1R_DRC_ENA 0x0001 /* AIF1ADC1R_DRC_ENA */

2871

#define WM8994_AIF1ADC1R_DRC_ENA_MASK 0x0001 /* AIF1ADC1R_DRC_ENA */

2872

#define WM8994_AIF1ADC1R_DRC_ENA_SHIFT 0 /* AIF1ADC1R_DRC_ENA */

2873

#define WM8994_AIF1ADC1R_DRC_ENA_WIDTH 1 /* AIF1ADC1R_DRC_ENA */

2874

2875

/*

2876

* R1089 (0x441) - AIF1 DRC1 (2)

2877

*/

2878

#define WM8994_AIF1DRC1_ATK_MASK 0x1E00 /* AIF1DRC1_ATK - [12:9] */

2879

#define WM8994_AIF1DRC1_ATK_SHIFT 9 /* AIF1DRC1_ATK - [12:9] */

2880

#define WM8994_AIF1DRC1_ATK_WIDTH 4 /* AIF1DRC1_ATK - [12:9] */

2881

#define WM8994_AIF1DRC1_DCY_MASK 0x01E0 /* AIF1DRC1_DCY - [8:5] */

2882

#define WM8994_AIF1DRC1_DCY_SHIFT 5 /* AIF1DRC1_DCY - [8:5] */

2883

#define WM8994_AIF1DRC1_DCY_WIDTH 4 /* AIF1DRC1_DCY - [8:5] */

2884

#define WM8994_AIF1DRC1_MINGAIN_MASK 0x001C /* AIF1DRC1_MINGAIN - [4:2] */

2885

#define WM8994_AIF1DRC1_MINGAIN_SHIFT 2 /* AIF1DRC1_MINGAIN - [4:2] */

2886

#define WM8994_AIF1DRC1_MINGAIN_WIDTH 3 /* AIF1DRC1_MINGAIN - [4:2] */

2887

#define WM8994_AIF1DRC1_MAXGAIN_MASK 0x0003 /* AIF1DRC1_MAXGAIN - [1:0] */

2888

#define WM8994_AIF1DRC1_MAXGAIN_SHIFT 0 /* AIF1DRC1_MAXGAIN - [1:0] */

2889

#define WM8994_AIF1DRC1_MAXGAIN_WIDTH 2 /* AIF1DRC1_MAXGAIN - [1:0] */

2890

2891

/*

2892

* R1090 (0x442) - AIF1 DRC1 (3)

2893

*/

2894

#define WM8994_AIF1DRC1_NG_MINGAIN_MASK 0xF000 /* AIF1DRC1_NG_MINGAIN - [15:12] */

2895

#define WM8994_AIF1DRC1_NG_MINGAIN_SHIFT 12 /* AIF1DRC1_NG_MINGAIN - [15:12] */

2896

#define WM8994_AIF1DRC1_NG_MINGAIN_WIDTH 4 /* AIF1DRC1_NG_MINGAIN - [15:12] */

2897

#define WM8994_AIF1DRC1_NG_EXP_MASK 0x0C00 /* AIF1DRC1_NG_EXP - [11:10] */

2898

#define WM8994_AIF1DRC1_NG_EXP_SHIFT 10 /* AIF1DRC1_NG_EXP - [11:10] */

2899

#define WM8994_AIF1DRC1_NG_EXP_WIDTH 2 /* AIF1DRC1_NG_EXP - [11:10] */

2900

#define WM8994_AIF1DRC1_QR_THR_MASK 0x0300 /* AIF1DRC1_QR_THR - [9:8] */

2901

#define WM8994_AIF1DRC1_QR_THR_SHIFT 8 /* AIF1DRC1_QR_THR - [9:8] */

2902

#define WM8994_AIF1DRC1_QR_THR_WIDTH 2 /* AIF1DRC1_QR_THR - [9:8] */

2903

#define WM8994_AIF1DRC1_QR_DCY_MASK 0x00C0 /* AIF1DRC1_QR_DCY - [7:6] */

2904

#define WM8994_AIF1DRC1_QR_DCY_SHIFT 6 /* AIF1DRC1_QR_DCY - [7:6] */

2905

#define WM8994_AIF1DRC1_QR_DCY_WIDTH 2 /* AIF1DRC1_QR_DCY - [7:6] */

2906

#define WM8994_AIF1DRC1_HI_COMP_MASK 0x0038 /* AIF1DRC1_HI_COMP - [5:3] */

2907

#define WM8994_AIF1DRC1_HI_COMP_SHIFT 3 /* AIF1DRC1_HI_COMP - [5:3] */

2908

#define WM8994_AIF1DRC1_HI_COMP_WIDTH 3 /* AIF1DRC1_HI_COMP - [5:3] */

2909

#define WM8994_AIF1DRC1_LO_COMP_MASK 0x0007 /* AIF1DRC1_LO_COMP - [2:0] */

2910

#define WM8994_AIF1DRC1_LO_COMP_SHIFT 0 /* AIF1DRC1_LO_COMP - [2:0] */

2911

#define WM8994_AIF1DRC1_LO_COMP_WIDTH 3 /* AIF1DRC1_LO_COMP - [2:0] */

2912

2913

/*

2914

* R1091 (0x443) - AIF1 DRC1 (4)

2915

*/

2916

#define WM8994_AIF1DRC1_KNEE_IP_MASK 0x07E0 /* AIF1DRC1_KNEE_IP - [10:5] */

2917

#define WM8994_AIF1DRC1_KNEE_IP_SHIFT 5 /* AIF1DRC1_KNEE_IP - [10:5] */

2918

#define WM8994_AIF1DRC1_KNEE_IP_WIDTH 6 /* AIF1DRC1_KNEE_IP - [10:5] */

2919

#define WM8994_AIF1DRC1_KNEE_OP_MASK 0x001F /* AIF1DRC1_KNEE_OP - [4:0] */

2920

#define WM8994_AIF1DRC1_KNEE_OP_SHIFT 0 /* AIF1DRC1_KNEE_OP - [4:0] */

2921

#define WM8994_AIF1DRC1_KNEE_OP_WIDTH 5 /* AIF1DRC1_KNEE_OP - [4:0] */

2922

2923

/*

2924

* R1092 (0x444) - AIF1 DRC1 (5)

2925

*/

2926

#define WM8994_AIF1DRC1_KNEE2_IP_MASK 0x03E0 /* AIF1DRC1_KNEE2_IP - [9:5] */

2927

#define WM8994_AIF1DRC1_KNEE2_IP_SHIFT 5 /* AIF1DRC1_KNEE2_IP - [9:5] */

2928

#define WM8994_AIF1DRC1_KNEE2_IP_WIDTH 5 /* AIF1DRC1_KNEE2_IP - [9:5] */

2929

#define WM8994_AIF1DRC1_KNEE2_OP_MASK 0x001F /* AIF1DRC1_KNEE2_OP - [4:0] */

2930

#define WM8994_AIF1DRC1_KNEE2_OP_SHIFT 0 /* AIF1DRC1_KNEE2_OP - [4:0] */

2931

#define WM8994_AIF1DRC1_KNEE2_OP_WIDTH 5 /* AIF1DRC1_KNEE2_OP - [4:0] */

2932

2933

/*

2934

* R1104 (0x450) - AIF1 DRC2 (1)

2935

*/

2936

#define WM8994_AIF1DRC2_SIG_DET_RMS_MASK 0xF800 /* AIF1DRC2_SIG_DET_RMS - [15:11] */

2937

#define WM8994_AIF1DRC2_SIG_DET_RMS_SHIFT 11 /* AIF1DRC2_SIG_DET_RMS - [15:11] */

2938

#define WM8994_AIF1DRC2_SIG_DET_RMS_WIDTH 5 /* AIF1DRC2_SIG_DET_RMS - [15:11] */

2939

#define WM8994_AIF1DRC2_SIG_DET_PK_MASK 0x0600 /* AIF1DRC2_SIG_DET_PK - [10:9] */

2940

#define WM8994_AIF1DRC2_SIG_DET_PK_SHIFT 9 /* AIF1DRC2_SIG_DET_PK - [10:9] */

2941

#define WM8994_AIF1DRC2_SIG_DET_PK_WIDTH 2 /* AIF1DRC2_SIG_DET_PK - [10:9] */

2942

#define WM8994_AIF1DRC2_NG_ENA 0x0100 /* AIF1DRC2_NG_ENA */

2943

#define WM8994_AIF1DRC2_NG_ENA_MASK 0x0100 /* AIF1DRC2_NG_ENA */

2944

#define WM8994_AIF1DRC2_NG_ENA_SHIFT 8 /* AIF1DRC2_NG_ENA */

2945

#define WM8994_AIF1DRC2_NG_ENA_WIDTH 1 /* AIF1DRC2_NG_ENA */

2946

#define WM8994_AIF1DRC2_SIG_DET_MODE 0x0080 /* AIF1DRC2_SIG_DET_MODE */

2947

#define WM8994_AIF1DRC2_SIG_DET_MODE_MASK 0x0080 /* AIF1DRC2_SIG_DET_MODE */

2948

#define WM8994_AIF1DRC2_SIG_DET_MODE_SHIFT 7 /* AIF1DRC2_SIG_DET_MODE */

2949

#define WM8994_AIF1DRC2_SIG_DET_MODE_WIDTH 1 /* AIF1DRC2_SIG_DET_MODE */

2950

#define WM8994_AIF1DRC2_SIG_DET 0x0040 /* AIF1DRC2_SIG_DET */

2951

#define WM8994_AIF1DRC2_SIG_DET_MASK 0x0040 /* AIF1DRC2_SIG_DET */

2952

#define WM8994_AIF1DRC2_SIG_DET_SHIFT 6 /* AIF1DRC2_SIG_DET */

2953

#define WM8994_AIF1DRC2_SIG_DET_WIDTH 1 /* AIF1DRC2_SIG_DET */

2954

#define WM8994_AIF1DRC2_KNEE2_OP_ENA 0x0020 /* AIF1DRC2_KNEE2_OP_ENA */

2955

#define WM8994_AIF1DRC2_KNEE2_OP_ENA_MASK 0x0020 /* AIF1DRC2_KNEE2_OP_ENA */

2956

#define WM8994_AIF1DRC2_KNEE2_OP_ENA_SHIFT 5 /* AIF1DRC2_KNEE2_OP_ENA */

2957

#define WM8994_AIF1DRC2_KNEE2_OP_ENA_WIDTH 1 /* AIF1DRC2_KNEE2_OP_ENA */

2958

#define WM8994_AIF1DRC2_QR 0x0010 /* AIF1DRC2_QR */

2959

#define WM8994_AIF1DRC2_QR_MASK 0x0010 /* AIF1DRC2_QR */

2960

#define WM8994_AIF1DRC2_QR_SHIFT 4 /* AIF1DRC2_QR */

2961

#define WM8994_AIF1DRC2_QR_WIDTH 1 /* AIF1DRC2_QR */

2962

#define WM8994_AIF1DRC2_ANTICLIP 0x0008 /* AIF1DRC2_ANTICLIP */

2963

#define WM8994_AIF1DRC2_ANTICLIP_MASK 0x0008 /* AIF1DRC2_ANTICLIP */

2964

#define WM8994_AIF1DRC2_ANTICLIP_SHIFT 3 /* AIF1DRC2_ANTICLIP */

2965

#define WM8994_AIF1DRC2_ANTICLIP_WIDTH 1 /* AIF1DRC2_ANTICLIP */

2966

#define WM8994_AIF1DAC2_DRC_ENA 0x0004 /* AIF1DAC2_DRC_ENA */

2967

#define WM8994_AIF1DAC2_DRC_ENA_MASK 0x0004 /* AIF1DAC2_DRC_ENA */

2968

#define WM8994_AIF1DAC2_DRC_ENA_SHIFT 2 /* AIF1DAC2_DRC_ENA */

2969

#define WM8994_AIF1DAC2_DRC_ENA_WIDTH 1 /* AIF1DAC2_DRC_ENA */

2970

#define WM8994_AIF1ADC2L_DRC_ENA 0x0002 /* AIF1ADC2L_DRC_ENA */

2971

#define WM8994_AIF1ADC2L_DRC_ENA_MASK 0x0002 /* AIF1ADC2L_DRC_ENA */

2972

#define WM8994_AIF1ADC2L_DRC_ENA_SHIFT 1 /* AIF1ADC2L_DRC_ENA */

2973

#define WM8994_AIF1ADC2L_DRC_ENA_WIDTH 1 /* AIF1ADC2L_DRC_ENA */

2974

#define WM8994_AIF1ADC2R_DRC_ENA 0x0001 /* AIF1ADC2R_DRC_ENA */

2975

#define WM8994_AIF1ADC2R_DRC_ENA_MASK 0x0001 /* AIF1ADC2R_DRC_ENA */

2976

#define WM8994_AIF1ADC2R_DRC_ENA_SHIFT 0 /* AIF1ADC2R_DRC_ENA */

2977

#define WM8994_AIF1ADC2R_DRC_ENA_WIDTH 1 /* AIF1ADC2R_DRC_ENA */

2978

2979

/*

2980

* R1105 (0x451) - AIF1 DRC2 (2)

2981

*/

2982

#define WM8994_AIF1DRC2_ATK_MASK 0x1E00 /* AIF1DRC2_ATK - [12:9] */

2983

#define WM8994_AIF1DRC2_ATK_SHIFT 9 /* AIF1DRC2_ATK - [12:9] */

2984

#define WM8994_AIF1DRC2_ATK_WIDTH 4 /* AIF1DRC2_ATK - [12:9] */

2985

#define WM8994_AIF1DRC2_DCY_MASK 0x01E0 /* AIF1DRC2_DCY - [8:5] */

2986

#define WM8994_AIF1DRC2_DCY_SHIFT 5 /* AIF1DRC2_DCY - [8:5] */

2987

#define WM8994_AIF1DRC2_DCY_WIDTH 4 /* AIF1DRC2_DCY - [8:5] */

2988

#define WM8994_AIF1DRC2_MINGAIN_MASK 0x001C /* AIF1DRC2_MINGAIN - [4:2] */

2989

#define WM8994_AIF1DRC2_MINGAIN_SHIFT 2 /* AIF1DRC2_MINGAIN - [4:2] */

2990

#define WM8994_AIF1DRC2_MINGAIN_WIDTH 3 /* AIF1DRC2_MINGAIN - [4:2] */

2991

#define WM8994_AIF1DRC2_MAXGAIN_MASK 0x0003 /* AIF1DRC2_MAXGAIN - [1:0] */

2992

#define WM8994_AIF1DRC2_MAXGAIN_SHIFT 0 /* AIF1DRC2_MAXGAIN - [1:0] */

2993

#define WM8994_AIF1DRC2_MAXGAIN_WIDTH 2 /* AIF1DRC2_MAXGAIN - [1:0] */

2994

2995

/*

2996

* R1106 (0x452) - AIF1 DRC2 (3)

2997

*/

2998

#define WM8994_AIF1DRC2_NG_MINGAIN_MASK 0xF000 /* AIF1DRC2_NG_MINGAIN - [15:12] */

2999

#define WM8994_AIF1DRC2_NG_MINGAIN_SHIFT 12 /* AIF1DRC2_NG_MINGAIN - [15:12] */

3000

#define WM8994_AIF1DRC2_NG_MINGAIN_WIDTH 4 /* AIF1DRC2_NG_MINGAIN - [15:12] */

3001

#define WM8994_AIF1DRC2_NG_EXP_MASK 0x0C00 /* AIF1DRC2_NG_EXP - [11:10] */

3002

#define WM8994_AIF1DRC2_NG_EXP_SHIFT 10 /* AIF1DRC2_NG_EXP - [11:10] */

3003

#define WM8994_AIF1DRC2_NG_EXP_WIDTH 2 /* AIF1DRC2_NG_EXP - [11:10] */

3004

#define WM8994_AIF1DRC2_QR_THR_MASK 0x0300 /* AIF1DRC2_QR_THR - [9:8] */

3005

#define WM8994_AIF1DRC2_QR_THR_SHIFT 8 /* AIF1DRC2_QR_THR - [9:8] */

3006

#define WM8994_AIF1DRC2_QR_THR_WIDTH 2 /* AIF1DRC2_QR_THR - [9:8] */

3007

#define WM8994_AIF1DRC2_QR_DCY_MASK 0x00C0 /* AIF1DRC2_QR_DCY - [7:6] */

3008

#define WM8994_AIF1DRC2_QR_DCY_SHIFT 6 /* AIF1DRC2_QR_DCY - [7:6] */

3009

#define WM8994_AIF1DRC2_QR_DCY_WIDTH 2 /* AIF1DRC2_QR_DCY - [7:6] */

3010

#define WM8994_AIF1DRC2_HI_COMP_MASK 0x0038 /* AIF1DRC2_HI_COMP - [5:3] */

3011

#define WM8994_AIF1DRC2_HI_COMP_SHIFT 3 /* AIF1DRC2_HI_COMP - [5:3] */

3012

#define WM8994_AIF1DRC2_HI_COMP_WIDTH 3 /* AIF1DRC2_HI_COMP - [5:3] */

3013

#define WM8994_AIF1DRC2_LO_COMP_MASK 0x0007 /* AIF1DRC2_LO_COMP - [2:0] */

3014

#define WM8994_AIF1DRC2_LO_COMP_SHIFT 0 /* AIF1DRC2_LO_COMP - [2:0] */

3015

#define WM8994_AIF1DRC2_LO_COMP_WIDTH 3 /* AIF1DRC2_LO_COMP - [2:0] */

3016

3017

/*

3018

* R1107 (0x453) - AIF1 DRC2 (4)

3019

*/

3020

#define WM8994_AIF1DRC2_KNEE_IP_MASK 0x07E0 /* AIF1DRC2_KNEE_IP - [10:5] */

3021

#define WM8994_AIF1DRC2_KNEE_IP_SHIFT 5 /* AIF1DRC2_KNEE_IP - [10:5] */

3022

#define WM8994_AIF1DRC2_KNEE_IP_WIDTH 6 /* AIF1DRC2_KNEE_IP - [10:5] */

3023

#define WM8994_AIF1DRC2_KNEE_OP_MASK 0x001F /* AIF1DRC2_KNEE_OP - [4:0] */

3024

#define WM8994_AIF1DRC2_KNEE_OP_SHIFT 0 /* AIF1DRC2_KNEE_OP - [4:0] */

3025

#define WM8994_AIF1DRC2_KNEE_OP_WIDTH 5 /* AIF1DRC2_KNEE_OP - [4:0] */

3026

3027

/*

3028

* R1108 (0x454) - AIF1 DRC2 (5)

3029

*/

3030

#define WM8994_AIF1DRC2_KNEE2_IP_MASK 0x03E0 /* AIF1DRC2_KNEE2_IP - [9:5] */

3031

#define WM8994_AIF1DRC2_KNEE2_IP_SHIFT 5 /* AIF1DRC2_KNEE2_IP - [9:5] */

3032

#define WM8994_AIF1DRC2_KNEE2_IP_WIDTH 5 /* AIF1DRC2_KNEE2_IP - [9:5] */

3033

#define WM8994_AIF1DRC2_KNEE2_OP_MASK 0x001F /* AIF1DRC2_KNEE2_OP - [4:0] */

3034

#define WM8994_AIF1DRC2_KNEE2_OP_SHIFT 0 /* AIF1DRC2_KNEE2_OP - [4:0] */

3035

#define WM8994_AIF1DRC2_KNEE2_OP_WIDTH 5 /* AIF1DRC2_KNEE2_OP - [4:0] */

3036

3037

/*

3038

* R1152 (0x480) - AIF1 DAC1 EQ Gains (1)

3039

*/

3040

#define WM8994_AIF1DAC1_EQ_B1_GAIN_MASK 0xF800 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */

3041

#define WM8994_AIF1DAC1_EQ_B1_GAIN_SHIFT 11 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */

3042

#define WM8994_AIF1DAC1_EQ_B1_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */

3043

#define WM8994_AIF1DAC1_EQ_B2_GAIN_MASK 0x07C0 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */

3044

#define WM8994_AIF1DAC1_EQ_B2_GAIN_SHIFT 6 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */

3045

#define WM8994_AIF1DAC1_EQ_B2_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */

3046

#define WM8994_AIF1DAC1_EQ_B3_GAIN_MASK 0x003E /* AIF1DAC1_EQ_B3_GAIN - [5:1] */

3047

#define WM8994_AIF1DAC1_EQ_B3_GAIN_SHIFT 1 /* AIF1DAC1_EQ_B3_GAIN - [5:1] */

3048

#define WM8994_AIF1DAC1_EQ_B3_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B3_GAIN - [5:1] */

3049

#define WM8994_AIF1DAC1_EQ_ENA 0x0001 /* AIF1DAC1_EQ_ENA */

3050

#define WM8994_AIF1DAC1_EQ_ENA_MASK 0x0001 /* AIF1DAC1_EQ_ENA */

3051

#define WM8994_AIF1DAC1_EQ_ENA_SHIFT 0 /* AIF1DAC1_EQ_ENA */

3052

#define WM8994_AIF1DAC1_EQ_ENA_WIDTH 1 /* AIF1DAC1_EQ_ENA */

3053

3054

/*

3055

* R1153 (0x481) - AIF1 DAC1 EQ Gains (2)

3056

*/

3057

#define WM8994_AIF1DAC1_EQ_B4_GAIN_MASK 0xF800 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */

3058

#define WM8994_AIF1DAC1_EQ_B4_GAIN_SHIFT 11 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */

3059

#define WM8994_AIF1DAC1_EQ_B4_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */

3060

#define WM8994_AIF1DAC1_EQ_B5_GAIN_MASK 0x07C0 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */

3061

#define WM8994_AIF1DAC1_EQ_B5_GAIN_SHIFT 6 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */

3062

#define WM8994_AIF1DAC1_EQ_B5_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */

3063

3064

/*

3065

* R1154 (0x482) - AIF1 DAC1 EQ Band 1 A

3066

*/

3067

#define WM8994_AIF1DAC1_EQ_B1_A_MASK 0xFFFF /* AIF1DAC1_EQ_B1_A - [15:0] */

3068

#define WM8994_AIF1DAC1_EQ_B1_A_SHIFT 0 /* AIF1DAC1_EQ_B1_A - [15:0] */

3069

#define WM8994_AIF1DAC1_EQ_B1_A_WIDTH 16 /* AIF1DAC1_EQ_B1_A - [15:0] */

3070

3071

/*

3072

* R1155 (0x483) - AIF1 DAC1 EQ Band 1 B

3073

*/

3074

#define WM8994_AIF1DAC1_EQ_B1_B_MASK 0xFFFF /* AIF1DAC1_EQ_B1_B - [15:0] */

3075

#define WM8994_AIF1DAC1_EQ_B1_B_SHIFT 0 /* AIF1DAC1_EQ_B1_B - [15:0] */

3076

#define WM8994_AIF1DAC1_EQ_B1_B_WIDTH 16 /* AIF1DAC1_EQ_B1_B - [15:0] */

3077

3078

/*

3079

* R1156 (0x484) - AIF1 DAC1 EQ Band 1 PG

3080

*/

3081

#define WM8994_AIF1DAC1_EQ_B1_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B1_PG - [15:0] */

3082

#define WM8994_AIF1DAC1_EQ_B1_PG_SHIFT 0 /* AIF1DAC1_EQ_B1_PG - [15:0] */

3083

#define WM8994_AIF1DAC1_EQ_B1_PG_WIDTH 16 /* AIF1DAC1_EQ_B1_PG - [15:0] */

3084

3085

/*

3086

* R1157 (0x485) - AIF1 DAC1 EQ Band 2 A

3087

*/

3088

#define WM8994_AIF1DAC1_EQ_B2_A_MASK 0xFFFF /* AIF1DAC1_EQ_B2_A - [15:0] */

3089

#define WM8994_AIF1DAC1_EQ_B2_A_SHIFT 0 /* AIF1DAC1_EQ_B2_A - [15:0] */

3090

#define WM8994_AIF1DAC1_EQ_B2_A_WIDTH 16 /* AIF1DAC1_EQ_B2_A - [15:0] */

3091

3092

/*

3093

* R1158 (0x486) - AIF1 DAC1 EQ Band 2 B

3094

*/

3095

#define WM8994_AIF1DAC1_EQ_B2_B_MASK 0xFFFF /* AIF1DAC1_EQ_B2_B - [15:0] */

3096

#define WM8994_AIF1DAC1_EQ_B2_B_SHIFT 0 /* AIF1DAC1_EQ_B2_B - [15:0] */

3097

#define WM8994_AIF1DAC1_EQ_B2_B_WIDTH 16 /* AIF1DAC1_EQ_B2_B - [15:0] */

3098

3099

/*

3100

* R1159 (0x487) - AIF1 DAC1 EQ Band 2 C

3101

*/

3102

#define WM8994_AIF1DAC1_EQ_B2_C_MASK 0xFFFF /* AIF1DAC1_EQ_B2_C - [15:0] */

3103

#define WM8994_AIF1DAC1_EQ_B2_C_SHIFT 0 /* AIF1DAC1_EQ_B2_C - [15:0] */

3104

#define WM8994_AIF1DAC1_EQ_B2_C_WIDTH 16 /* AIF1DAC1_EQ_B2_C - [15:0] */

3105

3106

/*

3107

* R1160 (0x488) - AIF1 DAC1 EQ Band 2 PG

3108

*/

3109

#define WM8994_AIF1DAC1_EQ_B2_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B2_PG - [15:0] */

3110

#define WM8994_AIF1DAC1_EQ_B2_PG_SHIFT 0 /* AIF1DAC1_EQ_B2_PG - [15:0] */

3111

#define WM8994_AIF1DAC1_EQ_B2_PG_WIDTH 16 /* AIF1DAC1_EQ_B2_PG - [15:0] */

3112

3113

/*

3114

* R1161 (0x489) - AIF1 DAC1 EQ Band 3 A

3115

*/

3116

#define WM8994_AIF1DAC1_EQ_B3_A_MASK 0xFFFF /* AIF1DAC1_EQ_B3_A - [15:0] */

3117

#define WM8994_AIF1DAC1_EQ_B3_A_SHIFT 0 /* AIF1DAC1_EQ_B3_A - [15:0] */

3118

#define WM8994_AIF1DAC1_EQ_B3_A_WIDTH 16 /* AIF1DAC1_EQ_B3_A - [15:0] */

3119

3120

/*

3121

* R1162 (0x48A) - AIF1 DAC1 EQ Band 3 B

3122

*/

3123

#define WM8994_AIF1DAC1_EQ_B3_B_MASK 0xFFFF /* AIF1DAC1_EQ_B3_B - [15:0] */

3124

#define WM8994_AIF1DAC1_EQ_B3_B_SHIFT 0 /* AIF1DAC1_EQ_B3_B - [15:0] */

3125

#define WM8994_AIF1DAC1_EQ_B3_B_WIDTH 16 /* AIF1DAC1_EQ_B3_B - [15:0] */

3126

3127

/*

3128

* R1163 (0x48B) - AIF1 DAC1 EQ Band 3 C

3129

*/

3130

#define WM8994_AIF1DAC1_EQ_B3_C_MASK 0xFFFF /* AIF1DAC1_EQ_B3_C - [15:0] */

3131

#define WM8994_AIF1DAC1_EQ_B3_C_SHIFT 0 /* AIF1DAC1_EQ_B3_C - [15:0] */

3132

#define WM8994_AIF1DAC1_EQ_B3_C_WIDTH 16 /* AIF1DAC1_EQ_B3_C - [15:0] */

3133

3134

/*

3135

* R1164 (0x48C) - AIF1 DAC1 EQ Band 3 PG

3136

*/

3137

#define WM8994_AIF1DAC1_EQ_B3_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B3_PG - [15:0] */

3138

#define WM8994_AIF1DAC1_EQ_B3_PG_SHIFT 0 /* AIF1DAC1_EQ_B3_PG - [15:0] */

3139

#define WM8994_AIF1DAC1_EQ_B3_PG_WIDTH 16 /* AIF1DAC1_EQ_B3_PG - [15:0] */

3140

3141

/*

3142

* R1165 (0x48D) - AIF1 DAC1 EQ Band 4 A

3143

*/

3144

#define WM8994_AIF1DAC1_EQ_B4_A_MASK 0xFFFF /* AIF1DAC1_EQ_B4_A - [15:0] */

3145

#define WM8994_AIF1DAC1_EQ_B4_A_SHIFT 0 /* AIF1DAC1_EQ_B4_A - [15:0] */

3146

#define WM8994_AIF1DAC1_EQ_B4_A_WIDTH 16 /* AIF1DAC1_EQ_B4_A - [15:0] */

3147

3148

/*

3149

* R1166 (0x48E) - AIF1 DAC1 EQ Band 4 B

3150

*/

3151

#define WM8994_AIF1DAC1_EQ_B4_B_MASK 0xFFFF /* AIF1DAC1_EQ_B4_B - [15:0] */

3152

#define WM8994_AIF1DAC1_EQ_B4_B_SHIFT 0 /* AIF1DAC1_EQ_B4_B - [15:0] */

3153

#define WM8994_AIF1DAC1_EQ_B4_B_WIDTH 16 /* AIF1DAC1_EQ_B4_B - [15:0] */

3154

3155

/*

3156

* R1167 (0x48F) - AIF1 DAC1 EQ Band 4 C

3157

*/

3158

#define WM8994_AIF1DAC1_EQ_B4_C_MASK 0xFFFF /* AIF1DAC1_EQ_B4_C - [15:0] */

3159

#define WM8994_AIF1DAC1_EQ_B4_C_SHIFT 0 /* AIF1DAC1_EQ_B4_C - [15:0] */

3160

#define WM8994_AIF1DAC1_EQ_B4_C_WIDTH 16 /* AIF1DAC1_EQ_B4_C - [15:0] */

3161

3162

/*

3163

* R1168 (0x490) - AIF1 DAC1 EQ Band 4 PG

3164

*/

3165

#define WM8994_AIF1DAC1_EQ_B4_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B4_PG - [15:0] */

3166

#define WM8994_AIF1DAC1_EQ_B4_PG_SHIFT 0 /* AIF1DAC1_EQ_B4_PG - [15:0] */

3167

#define WM8994_AIF1DAC1_EQ_B4_PG_WIDTH 16 /* AIF1DAC1_EQ_B4_PG - [15:0] */

3168

3169

/*

3170

* R1169 (0x491) - AIF1 DAC1 EQ Band 5 A

3171

*/

3172

#define WM8994_AIF1DAC1_EQ_B5_A_MASK 0xFFFF /* AIF1DAC1_EQ_B5_A - [15:0] */

3173

#define WM8994_AIF1DAC1_EQ_B5_A_SHIFT 0 /* AIF1DAC1_EQ_B5_A - [15:0] */

3174

#define WM8994_AIF1DAC1_EQ_B5_A_WIDTH 16 /* AIF1DAC1_EQ_B5_A - [15:0] */

3175

3176

/*

3177

* R1170 (0x492) - AIF1 DAC1 EQ Band 5 B

3178

*/

3179

#define WM8994_AIF1DAC1_EQ_B5_B_MASK 0xFFFF /* AIF1DAC1_EQ_B5_B - [15:0] */

3180

#define WM8994_AIF1DAC1_EQ_B5_B_SHIFT 0 /* AIF1DAC1_EQ_B5_B - [15:0] */

3181

#define WM8994_AIF1DAC1_EQ_B5_B_WIDTH 16 /* AIF1DAC1_EQ_B5_B - [15:0] */

3182

3183

/*

3184

* R1171 (0x493) - AIF1 DAC1 EQ Band 5 PG

3185

*/

3186

#define WM8994_AIF1DAC1_EQ_B5_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B5_PG - [15:0] */

3187

#define WM8994_AIF1DAC1_EQ_B5_PG_SHIFT 0 /* AIF1DAC1_EQ_B5_PG - [15:0] */

3188

#define WM8994_AIF1DAC1_EQ_B5_PG_WIDTH 16 /* AIF1DAC1_EQ_B5_PG - [15:0] */

3189

3190

/*

3191

* R1184 (0x4A0) - AIF1 DAC2 EQ Gains (1)

3192

*/

3193

#define WM8994_AIF1DAC2_EQ_B1_GAIN_MASK 0xF800 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */

3194

#define WM8994_AIF1DAC2_EQ_B1_GAIN_SHIFT 11 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */

3195

#define WM8994_AIF1DAC2_EQ_B1_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */

3196

#define WM8994_AIF1DAC2_EQ_B2_GAIN_MASK 0x07C0 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */

3197

#define WM8994_AIF1DAC2_EQ_B2_GAIN_SHIFT 6 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */

3198

#define WM8994_AIF1DAC2_EQ_B2_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */

3199

#define WM8994_AIF1DAC2_EQ_B3_GAIN_MASK 0x003E /* AIF1DAC2_EQ_B3_GAIN - [5:1] */

3200

#define WM8994_AIF1DAC2_EQ_B3_GAIN_SHIFT 1 /* AIF1DAC2_EQ_B3_GAIN - [5:1] */

3201

#define WM8994_AIF1DAC2_EQ_B3_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B3_GAIN - [5:1] */

3202

#define WM8994_AIF1DAC2_EQ_ENA 0x0001 /* AIF1DAC2_EQ_ENA */

3203

#define WM8994_AIF1DAC2_EQ_ENA_MASK 0x0001 /* AIF1DAC2_EQ_ENA */

3204

#define WM8994_AIF1DAC2_EQ_ENA_SHIFT 0 /* AIF1DAC2_EQ_ENA */

3205

#define WM8994_AIF1DAC2_EQ_ENA_WIDTH 1 /* AIF1DAC2_EQ_ENA */

3206

3207

/*

3208

* R1185 (0x4A1) - AIF1 DAC2 EQ Gains (2)

3209

*/

3210

#define WM8994_AIF1DAC2_EQ_B4_GAIN_MASK 0xF800 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */

3211

#define WM8994_AIF1DAC2_EQ_B4_GAIN_SHIFT 11 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */

3212

#define WM8994_AIF1DAC2_EQ_B4_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */

3213

#define WM8994_AIF1DAC2_EQ_B5_GAIN_MASK 0x07C0 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */

3214

#define WM8994_AIF1DAC2_EQ_B5_GAIN_SHIFT 6 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */

3215

#define WM8994_AIF1DAC2_EQ_B5_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */

3216

3217

/*

3218

* R1186 (0x4A2) - AIF1 DAC2 EQ Band 1 A

3219

*/

3220

#define WM8994_AIF1DAC2_EQ_B1_A_MASK 0xFFFF /* AIF1DAC2_EQ_B1_A - [15:0] */

3221

#define WM8994_AIF1DAC2_EQ_B1_A_SHIFT 0 /* AIF1DAC2_EQ_B1_A - [15:0] */

3222

#define WM8994_AIF1DAC2_EQ_B1_A_WIDTH 16 /* AIF1DAC2_EQ_B1_A - [15:0] */

3223

3224

/*

3225

* R1187 (0x4A3) - AIF1 DAC2 EQ Band 1 B

3226

*/

3227

#define WM8994_AIF1DAC2_EQ_B1_B_MASK 0xFFFF /* AIF1DAC2_EQ_B1_B - [15:0] */

3228

#define WM8994_AIF1DAC2_EQ_B1_B_SHIFT 0 /* AIF1DAC2_EQ_B1_B - [15:0] */

3229

#define WM8994_AIF1DAC2_EQ_B1_B_WIDTH 16 /* AIF1DAC2_EQ_B1_B - [15:0] */

3230

3231

/*

3232

* R1188 (0x4A4) - AIF1 DAC2 EQ Band 1 PG

3233

*/

3234

#define WM8994_AIF1DAC2_EQ_B1_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B1_PG - [15:0] */

3235

#define WM8994_AIF1DAC2_EQ_B1_PG_SHIFT 0 /* AIF1DAC2_EQ_B1_PG - [15:0] */

3236

#define WM8994_AIF1DAC2_EQ_B1_PG_WIDTH 16 /* AIF1DAC2_EQ_B1_PG - [15:0] */

3237

3238

/*

3239

* R1189 (0x4A5) - AIF1 DAC2 EQ Band 2 A

3240

*/

3241

#define WM8994_AIF1DAC2_EQ_B2_A_MASK 0xFFFF /* AIF1DAC2_EQ_B2_A - [15:0] */

3242

#define WM8994_AIF1DAC2_EQ_B2_A_SHIFT 0 /* AIF1DAC2_EQ_B2_A - [15:0] */

3243

#define WM8994_AIF1DAC2_EQ_B2_A_WIDTH 16 /* AIF1DAC2_EQ_B2_A - [15:0] */

3244

3245

/*

3246

* R1190 (0x4A6) - AIF1 DAC2 EQ Band 2 B

3247

*/

3248

#define WM8994_AIF1DAC2_EQ_B2_B_MASK 0xFFFF /* AIF1DAC2_EQ_B2_B - [15:0] */

3249

#define WM8994_AIF1DAC2_EQ_B2_B_SHIFT 0 /* AIF1DAC2_EQ_B2_B - [15:0] */

3250

#define WM8994_AIF1DAC2_EQ_B2_B_WIDTH 16 /* AIF1DAC2_EQ_B2_B - [15:0] */

3251

3252

/*

3253

* R1191 (0x4A7) - AIF1 DAC2 EQ Band 2 C

3254

*/

3255

#define WM8994_AIF1DAC2_EQ_B2_C_MASK 0xFFFF /* AIF1DAC2_EQ_B2_C - [15:0] */

3256

#define WM8994_AIF1DAC2_EQ_B2_C_SHIFT 0 /* AIF1DAC2_EQ_B2_C - [15:0] */

3257

#define WM8994_AIF1DAC2_EQ_B2_C_WIDTH 16 /* AIF1DAC2_EQ_B2_C - [15:0] */

3258

3259

/*

3260

* R1192 (0x4A8) - AIF1 DAC2 EQ Band 2 PG

3261

*/

3262

#define WM8994_AIF1DAC2_EQ_B2_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B2_PG - [15:0] */

3263

#define WM8994_AIF1DAC2_EQ_B2_PG_SHIFT 0 /* AIF1DAC2_EQ_B2_PG - [15:0] */

3264

#define WM8994_AIF1DAC2_EQ_B2_PG_WIDTH 16 /* AIF1DAC2_EQ_B2_PG - [15:0] */

3265

3266

/*

3267

* R1193 (0x4A9) - AIF1 DAC2 EQ Band 3 A

3268

*/

3269

#define WM8994_AIF1DAC2_EQ_B3_A_MASK 0xFFFF /* AIF1DAC2_EQ_B3_A - [15:0] */

3270

#define WM8994_AIF1DAC2_EQ_B3_A_SHIFT 0 /* AIF1DAC2_EQ_B3_A - [15:0] */

3271

#define WM8994_AIF1DAC2_EQ_B3_A_WIDTH 16 /* AIF1DAC2_EQ_B3_A - [15:0] */

3272

3273

/*

3274

* R1194 (0x4AA) - AIF1 DAC2 EQ Band 3 B

3275

*/

3276

#define WM8994_AIF1DAC2_EQ_B3_B_MASK 0xFFFF /* AIF1DAC2_EQ_B3_B - [15:0] */

3277

#define WM8994_AIF1DAC2_EQ_B3_B_SHIFT 0 /* AIF1DAC2_EQ_B3_B - [15:0] */

3278

#define WM8994_AIF1DAC2_EQ_B3_B_WIDTH 16 /* AIF1DAC2_EQ_B3_B - [15:0] */

3279

3280

/*

3281

* R1195 (0x4AB) - AIF1 DAC2 EQ Band 3 C

3282

*/

3283

#define WM8994_AIF1DAC2_EQ_B3_C_MASK 0xFFFF /* AIF1DAC2_EQ_B3_C - [15:0] */

3284

#define WM8994_AIF1DAC2_EQ_B3_C_SHIFT 0 /* AIF1DAC2_EQ_B3_C - [15:0] */

3285

#define WM8994_AIF1DAC2_EQ_B3_C_WIDTH 16 /* AIF1DAC2_EQ_B3_C - [15:0] */

3286

3287

/*

3288

* R1196 (0x4AC) - AIF1 DAC2 EQ Band 3 PG

3289

*/

3290

#define WM8994_AIF1DAC2_EQ_B3_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B3_PG - [15:0] */

3291

#define WM8994_AIF1DAC2_EQ_B3_PG_SHIFT 0 /* AIF1DAC2_EQ_B3_PG - [15:0] */

3292

#define WM8994_AIF1DAC2_EQ_B3_PG_WIDTH 16 /* AIF1DAC2_EQ_B3_PG - [15:0] */

3293

3294

/*

3295

* R1197 (0x4AD) - AIF1 DAC2 EQ Band 4 A

3296

*/

3297

#define WM8994_AIF1DAC2_EQ_B4_A_MASK 0xFFFF /* AIF1DAC2_EQ_B4_A - [15:0] */

3298

#define WM8994_AIF1DAC2_EQ_B4_A_SHIFT 0 /* AIF1DAC2_EQ_B4_A - [15:0] */

3299

#define WM8994_AIF1DAC2_EQ_B4_A_WIDTH 16 /* AIF1DAC2_EQ_B4_A - [15:0] */

3300

3301

/*

3302

* R1198 (0x4AE) - AIF1 DAC2 EQ Band 4 B

3303

*/

3304

#define WM8994_AIF1DAC2_EQ_B4_B_MASK 0xFFFF /* AIF1DAC2_EQ_B4_B - [15:0] */

3305

#define WM8994_AIF1DAC2_EQ_B4_B_SHIFT 0 /* AIF1DAC2_EQ_B4_B - [15:0] */

3306

#define WM8994_AIF1DAC2_EQ_B4_B_WIDTH 16 /* AIF1DAC2_EQ_B4_B - [15:0] */

3307

3308

/*

3309

* R1199 (0x4AF) - AIF1 DAC2 EQ Band 4 C

3310

*/

3311

#define WM8994_AIF1DAC2_EQ_B4_C_MASK 0xFFFF /* AIF1DAC2_EQ_B4_C - [15:0] */

3312

#define WM8994_AIF1DAC2_EQ_B4_C_SHIFT 0 /* AIF1DAC2_EQ_B4_C - [15:0] */

3313

#define WM8994_AIF1DAC2_EQ_B4_C_WIDTH 16 /* AIF1DAC2_EQ_B4_C - [15:0] */

3314

3315

/*

3316

* R1200 (0x4B0) - AIF1 DAC2 EQ Band 4 PG

3317

*/

3318

#define WM8994_AIF1DAC2_EQ_B4_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B4_PG - [15:0] */

3319

#define WM8994_AIF1DAC2_EQ_B4_PG_SHIFT 0 /* AIF1DAC2_EQ_B4_PG - [15:0] */

3320

#define WM8994_AIF1DAC2_EQ_B4_PG_WIDTH 16 /* AIF1DAC2_EQ_B4_PG - [15:0] */

3321

3322

/*

3323

* R1201 (0x4B1) - AIF1 DAC2 EQ Band 5 A

3324

*/

3325

#define WM8994_AIF1DAC2_EQ_B5_A_MASK 0xFFFF /* AIF1DAC2_EQ_B5_A - [15:0] */

3326

#define WM8994_AIF1DAC2_EQ_B5_A_SHIFT 0 /* AIF1DAC2_EQ_B5_A - [15:0] */

3327

#define WM8994_AIF1DAC2_EQ_B5_A_WIDTH 16 /* AIF1DAC2_EQ_B5_A - [15:0] */

3328

3329

/*

3330

* R1202 (0x4B2) - AIF1 DAC2 EQ Band 5 B

3331

*/

3332

#define WM8994_AIF1DAC2_EQ_B5_B_MASK 0xFFFF /* AIF1DAC2_EQ_B5_B - [15:0] */

3333

#define WM8994_AIF1DAC2_EQ_B5_B_SHIFT 0 /* AIF1DAC2_EQ_B5_B - [15:0] */

3334

#define WM8994_AIF1DAC2_EQ_B5_B_WIDTH 16 /* AIF1DAC2_EQ_B5_B - [15:0] */

3335

3336

/*

3337

* R1203 (0x4B3) - AIF1 DAC2 EQ Band 5 PG

3338

*/

3339

#define WM8994_AIF1DAC2_EQ_B5_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B5_PG - [15:0] */

3340

#define WM8994_AIF1DAC2_EQ_B5_PG_SHIFT 0 /* AIF1DAC2_EQ_B5_PG - [15:0] */

3341

#define WM8994_AIF1DAC2_EQ_B5_PG_WIDTH 16 /* AIF1DAC2_EQ_B5_PG - [15:0] */

3342

3343

/*

3344

* R1280 (0x500) - AIF2 ADC Left Volume

3345

*/

3346

#define WM8994_AIF2ADC_VU 0x0100 /* AIF2ADC_VU */

3347

#define WM8994_AIF2ADC_VU_MASK 0x0100 /* AIF2ADC_VU */

3348

#define WM8994_AIF2ADC_VU_SHIFT 8 /* AIF2ADC_VU */

3349

#define WM8994_AIF2ADC_VU_WIDTH 1 /* AIF2ADC_VU */

3350

#define WM8994_AIF2ADCL_VOL_MASK 0x00FF /* AIF2ADCL_VOL - [7:0] */

3351

#define WM8994_AIF2ADCL_VOL_SHIFT 0 /* AIF2ADCL_VOL - [7:0] */

3352

#define WM8994_AIF2ADCL_VOL_WIDTH 8 /* AIF2ADCL_VOL - [7:0] */

3353

3354

/*

3355

* R1281 (0x501) - AIF2 ADC Right Volume

3356

*/

3357

#define WM8994_AIF2ADC_VU 0x0100 /* AIF2ADC_VU */

3358

#define WM8994_AIF2ADC_VU_MASK 0x0100 /* AIF2ADC_VU */

3359

#define WM8994_AIF2ADC_VU_SHIFT 8 /* AIF2ADC_VU */

3360

#define WM8994_AIF2ADC_VU_WIDTH 1 /* AIF2ADC_VU */

3361

#define WM8994_AIF2ADCR_VOL_MASK 0x00FF /* AIF2ADCR_VOL - [7:0] */

3362

#define WM8994_AIF2ADCR_VOL_SHIFT 0 /* AIF2ADCR_VOL - [7:0] */

3363

#define WM8994_AIF2ADCR_VOL_WIDTH 8 /* AIF2ADCR_VOL - [7:0] */

3364

3365

/*

3366

* R1282 (0x502) - AIF2 DAC Left Volume

3367

*/

3368

#define WM8994_AIF2DAC_VU 0x0100 /* AIF2DAC_VU */

3369

#define WM8994_AIF2DAC_VU_MASK 0x0100 /* AIF2DAC_VU */

3370

#define WM8994_AIF2DAC_VU_SHIFT 8 /* AIF2DAC_VU */

3371

#define WM8994_AIF2DAC_VU_WIDTH 1 /* AIF2DAC_VU */

3372

#define WM8994_AIF2DACL_VOL_MASK 0x00FF /* AIF2DACL_VOL - [7:0] */

3373

#define WM8994_AIF2DACL_VOL_SHIFT 0 /* AIF2DACL_VOL - [7:0] */

3374

#define WM8994_AIF2DACL_VOL_WIDTH 8 /* AIF2DACL_VOL - [7:0] */

3375

3376

/*

3377

* R1283 (0x503) - AIF2 DAC Right Volume

3378

*/

3379

#define WM8994_AIF2DAC_VU 0x0100 /* AIF2DAC_VU */

3380

#define WM8994_AIF2DAC_VU_MASK 0x0100 /* AIF2DAC_VU */

3381

#define WM8994_AIF2DAC_VU_SHIFT 8 /* AIF2DAC_VU */

3382

#define WM8994_AIF2DAC_VU_WIDTH 1 /* AIF2DAC_VU */

3383

#define WM8994_AIF2DACR_VOL_MASK 0x00FF /* AIF2DACR_VOL - [7:0] */

3384

#define WM8994_AIF2DACR_VOL_SHIFT 0 /* AIF2DACR_VOL - [7:0] */

3385

#define WM8994_AIF2DACR_VOL_WIDTH 8 /* AIF2DACR_VOL - [7:0] */

3386

3387

/*

3388

* R1296 (0x510) - AIF2 ADC Filters

3389

*/

3390

#define WM8994_AIF2ADC_4FS 0x8000 /* AIF2ADC_4FS */

3391

#define WM8994_AIF2ADC_4FS_MASK 0x8000 /* AIF2ADC_4FS */

3392

#define WM8994_AIF2ADC_4FS_SHIFT 15 /* AIF2ADC_4FS */

3393

#define WM8994_AIF2ADC_4FS_WIDTH 1 /* AIF2ADC_4FS */

3394

#define WM8994_AIF2ADC_HPF_CUT_MASK 0x6000 /* AIF2ADC_HPF_CUT - [14:13] */

3395

#define WM8994_AIF2ADC_HPF_CUT_SHIFT 13 /* AIF2ADC_HPF_CUT - [14:13] */

3396

#define WM8994_AIF2ADC_HPF_CUT_WIDTH 2 /* AIF2ADC_HPF_CUT - [14:13] */

3397

#define WM8994_AIF2ADCL_HPF 0x1000 /* AIF2ADCL_HPF */

3398

#define WM8994_AIF2ADCL_HPF_MASK 0x1000 /* AIF2ADCL_HPF */

3399

#define WM8994_AIF2ADCL_HPF_SHIFT 12 /* AIF2ADCL_HPF */

3400

#define WM8994_AIF2ADCL_HPF_WIDTH 1 /* AIF2ADCL_HPF */

3401

#define WM8994_AIF2ADCR_HPF 0x0800 /* AIF2ADCR_HPF */

3402

#define WM8994_AIF2ADCR_HPF_MASK 0x0800 /* AIF2ADCR_HPF */

3403

#define WM8994_AIF2ADCR_HPF_SHIFT 11 /* AIF2ADCR_HPF */

3404

#define WM8994_AIF2ADCR_HPF_WIDTH 1 /* AIF2ADCR_HPF */

3405

3406

/*

3407

* R1312 (0x520) - AIF2 DAC Filters (1)

3408

*/

3409

#define WM8994_AIF2DAC_MUTE 0x0200 /* AIF2DAC_MUTE */

3410

#define WM8994_AIF2DAC_MUTE_MASK 0x0200 /* AIF2DAC_MUTE */

3411

#define WM8994_AIF2DAC_MUTE_SHIFT 9 /* AIF2DAC_MUTE */

3412

#define WM8994_AIF2DAC_MUTE_WIDTH 1 /* AIF2DAC_MUTE */

3413

#define WM8994_AIF2DAC_MONO 0x0080 /* AIF2DAC_MONO */

3414

#define WM8994_AIF2DAC_MONO_MASK 0x0080 /* AIF2DAC_MONO */

3415

#define WM8994_AIF2DAC_MONO_SHIFT 7 /* AIF2DAC_MONO */

3416

#define WM8994_AIF2DAC_MONO_WIDTH 1 /* AIF2DAC_MONO */

3417

#define WM8994_AIF2DAC_MUTERATE 0x0020 /* AIF2DAC_MUTERATE */

3418

#define WM8994_AIF2DAC_MUTERATE_MASK 0x0020 /* AIF2DAC_MUTERATE */

3419

#define WM8994_AIF2DAC_MUTERATE_SHIFT 5 /* AIF2DAC_MUTERATE */

3420

#define WM8994_AIF2DAC_MUTERATE_WIDTH 1 /* AIF2DAC_MUTERATE */

3421

#define WM8994_AIF2DAC_UNMUTE_RAMP 0x0010 /* AIF2DAC_UNMUTE_RAMP */

3422

#define WM8994_AIF2DAC_UNMUTE_RAMP_MASK 0x0010 /* AIF2DAC_UNMUTE_RAMP */

3423

#define WM8994_AIF2DAC_UNMUTE_RAMP_SHIFT 4 /* AIF2DAC_UNMUTE_RAMP */

3424

#define WM8994_AIF2DAC_UNMUTE_RAMP_WIDTH 1 /* AIF2DAC_UNMUTE_RAMP */

3425

#define WM8994_AIF2DAC_DEEMP_MASK 0x0006 /* AIF2DAC_DEEMP - [2:1] */

3426

#define WM8994_AIF2DAC_DEEMP_SHIFT 1 /* AIF2DAC_DEEMP - [2:1] */

3427

#define WM8994_AIF2DAC_DEEMP_WIDTH 2 /* AIF2DAC_DEEMP - [2:1] */

3428

3429

/*

3430

* R1313 (0x521) - AIF2 DAC Filters (2)

3431

*/

3432

#define WM8994_AIF2DAC_3D_GAIN_MASK 0x3E00 /* AIF2DAC_3D_GAIN - [13:9] */

3433

#define WM8994_AIF2DAC_3D_GAIN_SHIFT 9 /* AIF2DAC_3D_GAIN - [13:9] */

3434

#define WM8994_AIF2DAC_3D_GAIN_WIDTH 5 /* AIF2DAC_3D_GAIN - [13:9] */

3435

#define WM8994_AIF2DAC_3D_ENA 0x0100 /* AIF2DAC_3D_ENA */

3436

#define WM8994_AIF2DAC_3D_ENA_MASK 0x0100 /* AIF2DAC_3D_ENA */

3437

#define WM8994_AIF2DAC_3D_ENA_SHIFT 8 /* AIF2DAC_3D_ENA */

3438

#define WM8994_AIF2DAC_3D_ENA_WIDTH 1 /* AIF2DAC_3D_ENA */

3439

3440

/*

3441

* R1344 (0x540) - AIF2 DRC (1)

3442

*/

3443

#define WM8994_AIF2DRC_SIG_DET_RMS_MASK 0xF800 /* AIF2DRC_SIG_DET_RMS - [15:11] */

3444

#define WM8994_AIF2DRC_SIG_DET_RMS_SHIFT 11 /* AIF2DRC_SIG_DET_RMS - [15:11] */

3445

#define WM8994_AIF2DRC_SIG_DET_RMS_WIDTH 5 /* AIF2DRC_SIG_DET_RMS - [15:11] */

3446

#define WM8994_AIF2DRC_SIG_DET_PK_MASK 0x0600 /* AIF2DRC_SIG_DET_PK - [10:9] */

3447

#define WM8994_AIF2DRC_SIG_DET_PK_SHIFT 9 /* AIF2DRC_SIG_DET_PK - [10:9] */

3448

#define WM8994_AIF2DRC_SIG_DET_PK_WIDTH 2 /* AIF2DRC_SIG_DET_PK - [10:9] */

3449

#define WM8994_AIF2DRC_NG_ENA 0x0100 /* AIF2DRC_NG_ENA */

3450

#define WM8994_AIF2DRC_NG_ENA_MASK 0x0100 /* AIF2DRC_NG_ENA */

3451

#define WM8994_AIF2DRC_NG_ENA_SHIFT 8 /* AIF2DRC_NG_ENA */

3452

#define WM8994_AIF2DRC_NG_ENA_WIDTH 1 /* AIF2DRC_NG_ENA */

3453

#define WM8994_AIF2DRC_SIG_DET_MODE 0x0080 /* AIF2DRC_SIG_DET_MODE */

3454

#define WM8994_AIF2DRC_SIG_DET_MODE_MASK 0x0080 /* AIF2DRC_SIG_DET_MODE */

3455

#define WM8994_AIF2DRC_SIG_DET_MODE_SHIFT 7 /* AIF2DRC_SIG_DET_MODE */

3456

#define WM8994_AIF2DRC_SIG_DET_MODE_WIDTH 1 /* AIF2DRC_SIG_DET_MODE */

3457

#define WM8994_AIF2DRC_SIG_DET 0x0040 /* AIF2DRC_SIG_DET */

3458

#define WM8994_AIF2DRC_SIG_DET_MASK 0x0040 /* AIF2DRC_SIG_DET */

3459

#define WM8994_AIF2DRC_SIG_DET_SHIFT 6 /* AIF2DRC_SIG_DET */

3460

#define WM8994_AIF2DRC_SIG_DET_WIDTH 1 /* AIF2DRC_SIG_DET */

3461

#define WM8994_AIF2DRC_KNEE2_OP_ENA 0x0020 /* AIF2DRC_KNEE2_OP_ENA */

3462

#define WM8994_AIF2DRC_KNEE2_OP_ENA_MASK 0x0020 /* AIF2DRC_KNEE2_OP_ENA */

3463

#define WM8994_AIF2DRC_KNEE2_OP_ENA_SHIFT 5 /* AIF2DRC_KNEE2_OP_ENA */

3464

#define WM8994_AIF2DRC_KNEE2_OP_ENA_WIDTH 1 /* AIF2DRC_KNEE2_OP_ENA */

3465

#define WM8994_AIF2DRC_QR 0x0010 /* AIF2DRC_QR */

3466

#define WM8994_AIF2DRC_QR_MASK 0x0010 /* AIF2DRC_QR */

3467

#define WM8994_AIF2DRC_QR_SHIFT 4 /* AIF2DRC_QR */

3468

#define WM8994_AIF2DRC_QR_WIDTH 1 /* AIF2DRC_QR */

3469

#define WM8994_AIF2DRC_ANTICLIP 0x0008 /* AIF2DRC_ANTICLIP */

3470

#define WM8994_AIF2DRC_ANTICLIP_MASK 0x0008 /* AIF2DRC_ANTICLIP */

3471

#define WM8994_AIF2DRC_ANTICLIP_SHIFT 3 /* AIF2DRC_ANTICLIP */

3472

#define WM8994_AIF2DRC_ANTICLIP_WIDTH 1 /* AIF2DRC_ANTICLIP */

3473

#define WM8994_AIF2DAC_DRC_ENA 0x0004 /* AIF2DAC_DRC_ENA */

3474

#define WM8994_AIF2DAC_DRC_ENA_MASK 0x0004 /* AIF2DAC_DRC_ENA */

3475

#define WM8994_AIF2DAC_DRC_ENA_SHIFT 2 /* AIF2DAC_DRC_ENA */

3476

#define WM8994_AIF2DAC_DRC_ENA_WIDTH 1 /* AIF2DAC_DRC_ENA */

3477

#define WM8994_AIF2ADCL_DRC_ENA 0x0002 /* AIF2ADCL_DRC_ENA */

3478

#define WM8994_AIF2ADCL_DRC_ENA_MASK 0x0002 /* AIF2ADCL_DRC_ENA */

3479

#define WM8994_AIF2ADCL_DRC_ENA_SHIFT 1 /* AIF2ADCL_DRC_ENA */

3480

#define WM8994_AIF2ADCL_DRC_ENA_WIDTH 1 /* AIF2ADCL_DRC_ENA */

3481

#define WM8994_AIF2ADCR_DRC_ENA 0x0001 /* AIF2ADCR_DRC_ENA */

3482

#define WM8994_AIF2ADCR_DRC_ENA_MASK 0x0001 /* AIF2ADCR_DRC_ENA */

3483

#define WM8994_AIF2ADCR_DRC_ENA_SHIFT 0 /* AIF2ADCR_DRC_ENA */

3484

#define WM8994_AIF2ADCR_DRC_ENA_WIDTH 1 /* AIF2ADCR_DRC_ENA */

3485

3486

/*

3487

* R1345 (0x541) - AIF2 DRC (2)

3488

*/

3489

#define WM8994_AIF2DRC_ATK_MASK 0x1E00 /* AIF2DRC_ATK - [12:9] */

3490

#define WM8994_AIF2DRC_ATK_SHIFT 9 /* AIF2DRC_ATK - [12:9] */

3491

#define WM8994_AIF2DRC_ATK_WIDTH 4 /* AIF2DRC_ATK - [12:9] */

3492

#define WM8994_AIF2DRC_DCY_MASK 0x01E0 /* AIF2DRC_DCY - [8:5] */

3493

#define WM8994_AIF2DRC_DCY_SHIFT 5 /* AIF2DRC_DCY - [8:5] */

3494

#define WM8994_AIF2DRC_DCY_WIDTH 4 /* AIF2DRC_DCY - [8:5] */

3495

#define WM8994_AIF2DRC_MINGAIN_MASK 0x001C /* AIF2DRC_MINGAIN - [4:2] */

3496

#define WM8994_AIF2DRC_MINGAIN_SHIFT 2 /* AIF2DRC_MINGAIN - [4:2] */

3497

#define WM8994_AIF2DRC_MINGAIN_WIDTH 3 /* AIF2DRC_MINGAIN - [4:2] */

3498

#define WM8994_AIF2DRC_MAXGAIN_MASK 0x0003 /* AIF2DRC_MAXGAIN - [1:0] */

3499

#define WM8994_AIF2DRC_MAXGAIN_SHIFT 0 /* AIF2DRC_MAXGAIN - [1:0] */

3500

#define WM8994_AIF2DRC_MAXGAIN_WIDTH 2 /* AIF2DRC_MAXGAIN - [1:0] */

3501

3502

/*

3503

* R1346 (0x542) - AIF2 DRC (3)

3504

*/

3505

#define WM8994_AIF2DRC_NG_MINGAIN_MASK 0xF000 /* AIF2DRC_NG_MINGAIN - [15:12] */

3506

#define WM8994_AIF2DRC_NG_MINGAIN_SHIFT 12 /* AIF2DRC_NG_MINGAIN - [15:12] */

3507

#define WM8994_AIF2DRC_NG_MINGAIN_WIDTH 4 /* AIF2DRC_NG_MINGAIN - [15:12] */

3508

#define WM8994_AIF2DRC_NG_EXP_MASK 0x0C00 /* AIF2DRC_NG_EXP - [11:10] */

3509

#define WM8994_AIF2DRC_NG_EXP_SHIFT 10 /* AIF2DRC_NG_EXP - [11:10] */

3510

#define WM8994_AIF2DRC_NG_EXP_WIDTH 2 /* AIF2DRC_NG_EXP - [11:10] */

3511

#define WM8994_AIF2DRC_QR_THR_MASK 0x0300 /* AIF2DRC_QR_THR - [9:8] */

3512

#define WM8994_AIF2DRC_QR_THR_SHIFT 8 /* AIF2DRC_QR_THR - [9:8] */

3513

#define WM8994_AIF2DRC_QR_THR_WIDTH 2 /* AIF2DRC_QR_THR - [9:8] */

3514

#define WM8994_AIF2DRC_QR_DCY_MASK 0x00C0 /* AIF2DRC_QR_DCY - [7:6] */

3515

#define WM8994_AIF2DRC_QR_DCY_SHIFT 6 /* AIF2DRC_QR_DCY - [7:6] */

3516

#define WM8994_AIF2DRC_QR_DCY_WIDTH 2 /* AIF2DRC_QR_DCY - [7:6] */

3517

#define WM8994_AIF2DRC_HI_COMP_MASK 0x0038 /* AIF2DRC_HI_COMP - [5:3] */

3518

#define WM8994_AIF2DRC_HI_COMP_SHIFT 3 /* AIF2DRC_HI_COMP - [5:3] */

3519

#define WM8994_AIF2DRC_HI_COMP_WIDTH 3 /* AIF2DRC_HI_COMP - [5:3] */

3520

#define WM8994_AIF2DRC_LO_COMP_MASK 0x0007 /* AIF2DRC_LO_COMP - [2:0] */

3521

#define WM8994_AIF2DRC_LO_COMP_SHIFT 0 /* AIF2DRC_LO_COMP - [2:0] */

3522

#define WM8994_AIF2DRC_LO_COMP_WIDTH 3 /* AIF2DRC_LO_COMP - [2:0] */

3523

3524

/*

3525

* R1347 (0x543) - AIF2 DRC (4)

3526

*/

3527

#define WM8994_AIF2DRC_KNEE_IP_MASK 0x07E0 /* AIF2DRC_KNEE_IP - [10:5] */

3528

#define WM8994_AIF2DRC_KNEE_IP_SHIFT 5 /* AIF2DRC_KNEE_IP - [10:5] */

3529

#define WM8994_AIF2DRC_KNEE_IP_WIDTH 6 /* AIF2DRC_KNEE_IP - [10:5] */

3530

#define WM8994_AIF2DRC_KNEE_OP_MASK 0x001F /* AIF2DRC_KNEE_OP - [4:0] */

3531

#define WM8994_AIF2DRC_KNEE_OP_SHIFT 0 /* AIF2DRC_KNEE_OP - [4:0] */

3532

#define WM8994_AIF2DRC_KNEE_OP_WIDTH 5 /* AIF2DRC_KNEE_OP - [4:0] */

3533

3534

/*

3535

* R1348 (0x544) - AIF2 DRC (5)

3536

*/

3537

#define WM8994_AIF2DRC_KNEE2_IP_MASK 0x03E0 /* AIF2DRC_KNEE2_IP - [9:5] */

3538

#define WM8994_AIF2DRC_KNEE2_IP_SHIFT 5 /* AIF2DRC_KNEE2_IP - [9:5] */

3539

#define WM8994_AIF2DRC_KNEE2_IP_WIDTH 5 /* AIF2DRC_KNEE2_IP - [9:5] */

3540

#define WM8994_AIF2DRC_KNEE2_OP_MASK 0x001F /* AIF2DRC_KNEE2_OP - [4:0] */

3541

#define WM8994_AIF2DRC_KNEE2_OP_SHIFT 0 /* AIF2DRC_KNEE2_OP - [4:0] */

3542

#define WM8994_AIF2DRC_KNEE2_OP_WIDTH 5 /* AIF2DRC_KNEE2_OP - [4:0] */

3543

3544

/*

3545

* R1408 (0x580) - AIF2 EQ Gains (1)

3546

*/

3547

#define WM8994_AIF2DAC_EQ_B1_GAIN_MASK 0xF800 /* AIF2DAC_EQ_B1_GAIN - [15:11] */

3548

#define WM8994_AIF2DAC_EQ_B1_GAIN_SHIFT 11 /* AIF2DAC_EQ_B1_GAIN - [15:11] */

3549

#define WM8994_AIF2DAC_EQ_B1_GAIN_WIDTH 5 /* AIF2DAC_EQ_B1_GAIN - [15:11] */

3550

#define WM8994_AIF2DAC_EQ_B2_GAIN_MASK 0x07C0 /* AIF2DAC_EQ_B2_GAIN - [10:6] */

3551

#define WM8994_AIF2DAC_EQ_B2_GAIN_SHIFT 6 /* AIF2DAC_EQ_B2_GAIN - [10:6] */

3552

#define WM8994_AIF2DAC_EQ_B2_GAIN_WIDTH 5 /* AIF2DAC_EQ_B2_GAIN - [10:6] */

3553

#define WM8994_AIF2DAC_EQ_B3_GAIN_MASK 0x003E /* AIF2DAC_EQ_B3_GAIN - [5:1] */

3554

#define WM8994_AIF2DAC_EQ_B3_GAIN_SHIFT 1 /* AIF2DAC_EQ_B3_GAIN - [5:1] */

3555

#define WM8994_AIF2DAC_EQ_B3_GAIN_WIDTH 5 /* AIF2DAC_EQ_B3_GAIN - [5:1] */

3556

#define WM8994_AIF2DAC_EQ_ENA 0x0001 /* AIF2DAC_EQ_ENA */

3557

#define WM8994_AIF2DAC_EQ_ENA_MASK 0x0001 /* AIF2DAC_EQ_ENA */

3558

#define WM8994_AIF2DAC_EQ_ENA_SHIFT 0 /* AIF2DAC_EQ_ENA */

3559

#define WM8994_AIF2DAC_EQ_ENA_WIDTH 1 /* AIF2DAC_EQ_ENA */

3560

3561

/*

3562

* R1409 (0x581) - AIF2 EQ Gains (2)

3563

*/

3564

#define WM8994_AIF2DAC_EQ_B4_GAIN_MASK 0xF800 /* AIF2DAC_EQ_B4_GAIN - [15:11] */

3565

#define WM8994_AIF2DAC_EQ_B4_GAIN_SHIFT 11 /* AIF2DAC_EQ_B4_GAIN - [15:11] */

3566

#define WM8994_AIF2DAC_EQ_B4_GAIN_WIDTH 5 /* AIF2DAC_EQ_B4_GAIN - [15:11] */

3567

#define WM8994_AIF2DAC_EQ_B5_GAIN_MASK 0x07C0 /* AIF2DAC_EQ_B5_GAIN - [10:6] */

3568

#define WM8994_AIF2DAC_EQ_B5_GAIN_SHIFT 6 /* AIF2DAC_EQ_B5_GAIN - [10:6] */

3569

#define WM8994_AIF2DAC_EQ_B5_GAIN_WIDTH 5 /* AIF2DAC_EQ_B5_GAIN - [10:6] */

3570

3571

/*

3572

* R1410 (0x582) - AIF2 EQ Band 1 A

3573

*/

3574

#define WM8994_AIF2DAC_EQ_B1_A_MASK 0xFFFF /* AIF2DAC_EQ_B1_A - [15:0] */

3575

#define WM8994_AIF2DAC_EQ_B1_A_SHIFT 0 /* AIF2DAC_EQ_B1_A - [15:0] */

3576

#define WM8994_AIF2DAC_EQ_B1_A_WIDTH 16 /* AIF2DAC_EQ_B1_A - [15:0] */

3577

3578

/*

3579

* R1411 (0x583) - AIF2 EQ Band 1 B

3580

*/

3581

#define WM8994_AIF2DAC_EQ_B1_B_MASK 0xFFFF /* AIF2DAC_EQ_B1_B - [15:0] */

3582

#define WM8994_AIF2DAC_EQ_B1_B_SHIFT 0 /* AIF2DAC_EQ_B1_B - [15:0] */

3583

#define WM8994_AIF2DAC_EQ_B1_B_WIDTH 16 /* AIF2DAC_EQ_B1_B - [15:0] */

3584

3585

/*

3586

* R1412 (0x584) - AIF2 EQ Band 1 PG

3587

*/

3588

#define WM8994_AIF2DAC_EQ_B1_PG_MASK 0xFFFF /* AIF2DAC_EQ_B1_PG - [15:0] */

3589

#define WM8994_AIF2DAC_EQ_B1_PG_SHIFT 0 /* AIF2DAC_EQ_B1_PG - [15:0] */

3590

#define WM8994_AIF2DAC_EQ_B1_PG_WIDTH 16 /* AIF2DAC_EQ_B1_PG - [15:0] */

3591

3592

/*

3593

* R1413 (0x585) - AIF2 EQ Band 2 A

3594

*/

3595

#define WM8994_AIF2DAC_EQ_B2_A_MASK 0xFFFF /* AIF2DAC_EQ_B2_A - [15:0] */

3596

#define WM8994_AIF2DAC_EQ_B2_A_SHIFT 0 /* AIF2DAC_EQ_B2_A - [15:0] */

3597

#define WM8994_AIF2DAC_EQ_B2_A_WIDTH 16 /* AIF2DAC_EQ_B2_A - [15:0] */

3598

3599

/*

3600

* R1414 (0x586) - AIF2 EQ Band 2 B

3601

*/

3602

#define WM8994_AIF2DAC_EQ_B2_B_MASK 0xFFFF /* AIF2DAC_EQ_B2_B - [15:0] */

3603

#define WM8994_AIF2DAC_EQ_B2_B_SHIFT 0 /* AIF2DAC_EQ_B2_B - [15:0] */

3604

#define WM8994_AIF2DAC_EQ_B2_B_WIDTH 16 /* AIF2DAC_EQ_B2_B - [15:0] */

3605

3606

/*

3607

* R1415 (0x587) - AIF2 EQ Band 2 C

3608

*/

3609

#define WM8994_AIF2DAC_EQ_B2_C_MASK 0xFFFF /* AIF2DAC_EQ_B2_C - [15:0] */

3610

#define WM8994_AIF2DAC_EQ_B2_C_SHIFT 0 /* AIF2DAC_EQ_B2_C - [15:0] */

3611

#define WM8994_AIF2DAC_EQ_B2_C_WIDTH 16 /* AIF2DAC_EQ_B2_C - [15:0] */

3612

3613

/*

3614

* R1416 (0x588) - AIF2 EQ Band 2 PG

3615

*/

3616

#define WM8994_AIF2DAC_EQ_B2_PG_MASK 0xFFFF /* AIF2DAC_EQ_B2_PG - [15:0] */

3617

#define WM8994_AIF2DAC_EQ_B2_PG_SHIFT 0 /* AIF2DAC_EQ_B2_PG - [15:0] */

3618

#define WM8994_AIF2DAC_EQ_B2_PG_WIDTH 16 /* AIF2DAC_EQ_B2_PG - [15:0] */

3619

3620

/*

3621

* R1417 (0x589) - AIF2 EQ Band 3 A

3622

*/

3623

#define WM8994_AIF2DAC_EQ_B3_A_MASK 0xFFFF /* AIF2DAC_EQ_B3_A - [15:0] */

3624

#define WM8994_AIF2DAC_EQ_B3_A_SHIFT 0 /* AIF2DAC_EQ_B3_A - [15:0] */

3625

#define WM8994_AIF2DAC_EQ_B3_A_WIDTH 16 /* AIF2DAC_EQ_B3_A - [15:0] */

3626

3627

/*

3628

* R1418 (0x58A) - AIF2 EQ Band 3 B

3629

*/

3630

#define WM8994_AIF2DAC_EQ_B3_B_MASK 0xFFFF /* AIF2DAC_EQ_B3_B - [15:0] */

3631

#define WM8994_AIF2DAC_EQ_B3_B_SHIFT 0 /* AIF2DAC_EQ_B3_B - [15:0] */

3632

#define WM8994_AIF2DAC_EQ_B3_B_WIDTH 16 /* AIF2DAC_EQ_B3_B - [15:0] */

3633

3634

/*

3635

* R1419 (0x58B) - AIF2 EQ Band 3 C

3636

*/

3637

#define WM8994_AIF2DAC_EQ_B3_C_MASK 0xFFFF /* AIF2DAC_EQ_B3_C - [15:0] */

3638

#define WM8994_AIF2DAC_EQ_B3_C_SHIFT 0 /* AIF2DAC_EQ_B3_C - [15:0] */

3639

#define WM8994_AIF2DAC_EQ_B3_C_WIDTH 16 /* AIF2DAC_EQ_B3_C - [15:0] */

3640

3641

/*

3642

* R1420 (0x58C) - AIF2 EQ Band 3 PG

3643

*/

3644

#define WM8994_AIF2DAC_EQ_B3_PG_MASK 0xFFFF /* AIF2DAC_EQ_B3_PG - [15:0] */

3645

#define WM8994_AIF2DAC_EQ_B3_PG_SHIFT 0 /* AIF2DAC_EQ_B3_PG - [15:0] */

3646

#define WM8994_AIF2DAC_EQ_B3_PG_WIDTH 16 /* AIF2DAC_EQ_B3_PG - [15:0] */

3647

3648

/*

3649

* R1421 (0x58D) - AIF2 EQ Band 4 A

3650

*/

3651

#define WM8994_AIF2DAC_EQ_B4_A_MASK 0xFFFF /* AIF2DAC_EQ_B4_A - [15:0] */

3652

#define WM8994_AIF2DAC_EQ_B4_A_SHIFT 0 /* AIF2DAC_EQ_B4_A - [15:0] */

3653

#define WM8994_AIF2DAC_EQ_B4_A_WIDTH 16 /* AIF2DAC_EQ_B4_A - [15:0] */

3654

3655

/*

3656

* R1422 (0x58E) - AIF2 EQ Band 4 B

3657

*/

3658

#define WM8994_AIF2DAC_EQ_B4_B_MASK 0xFFFF /* AIF2DAC_EQ_B4_B - [15:0] */

3659

#define WM8994_AIF2DAC_EQ_B4_B_SHIFT 0 /* AIF2DAC_EQ_B4_B - [15:0] */

3660

#define WM8994_AIF2DAC_EQ_B4_B_WIDTH 16 /* AIF2DAC_EQ_B4_B - [15:0] */

3661

3662

/*

3663

* R1423 (0x58F) - AIF2 EQ Band 4 C

3664

*/

3665

#define WM8994_AIF2DAC_EQ_B4_C_MASK 0xFFFF /* AIF2DAC_EQ_B4_C - [15:0] */

3666

#define WM8994_AIF2DAC_EQ_B4_C_SHIFT 0 /* AIF2DAC_EQ_B4_C - [15:0] */

3667

#define WM8994_AIF2DAC_EQ_B4_C_WIDTH 16 /* AIF2DAC_EQ_B4_C - [15:0] */

3668

3669

/*

3670

* R1424 (0x590) - AIF2 EQ Band 4 PG

3671

*/

3672

#define WM8994_AIF2DAC_EQ_B4_PG_MASK 0xFFFF /* AIF2DAC_EQ_B4_PG - [15:0] */

3673

#define WM8994_AIF2DAC_EQ_B4_PG_SHIFT 0 /* AIF2DAC_EQ_B4_PG - [15:0] */

3674

#define WM8994_AIF2DAC_EQ_B4_PG_WIDTH 16 /* AIF2DAC_EQ_B4_PG - [15:0] */

3675

3676

/*

3677

* R1425 (0x591) - AIF2 EQ Band 5 A

3678

*/

3679

#define WM8994_AIF2DAC_EQ_B5_A_MASK 0xFFFF /* AIF2DAC_EQ_B5_A - [15:0] */

3680

#define WM8994_AIF2DAC_EQ_B5_A_SHIFT 0 /* AIF2DAC_EQ_B5_A - [15:0] */

3681

#define WM8994_AIF2DAC_EQ_B5_A_WIDTH 16 /* AIF2DAC_EQ_B5_A - [15:0] */

3682

3683

/*

3684

* R1426 (0x592) - AIF2 EQ Band 5 B

3685

*/

3686

#define WM8994_AIF2DAC_EQ_B5_B_MASK 0xFFFF /* AIF2DAC_EQ_B5_B - [15:0] */

3687

#define WM8994_AIF2DAC_EQ_B5_B_SHIFT 0 /* AIF2DAC_EQ_B5_B - [15:0] */

3688

#define WM8994_AIF2DAC_EQ_B5_B_WIDTH 16 /* AIF2DAC_EQ_B5_B - [15:0] */

3689

3690

/*

3691

* R1427 (0x593) - AIF2 EQ Band 5 PG

3692

*/

3693

#define WM8994_AIF2DAC_EQ_B5_PG_MASK 0xFFFF /* AIF2DAC_EQ_B5_PG - [15:0] */

3694

#define WM8994_AIF2DAC_EQ_B5_PG_SHIFT 0 /* AIF2DAC_EQ_B5_PG - [15:0] */

3695

#define WM8994_AIF2DAC_EQ_B5_PG_WIDTH 16 /* AIF2DAC_EQ_B5_PG - [15:0] */

3696

3697

/*

3698

* R1536 (0x600) - DAC1 Mixer Volumes

3699

*/

3700

#define WM8994_ADCR_DAC1_VOL_MASK 0x01E0 /* ADCR_DAC1_VOL - [8:5] */

3701

#define WM8994_ADCR_DAC1_VOL_SHIFT 5 /* ADCR_DAC1_VOL - [8:5] */

3702

#define WM8994_ADCR_DAC1_VOL_WIDTH 4 /* ADCR_DAC1_VOL - [8:5] */

3703

#define WM8994_ADCL_DAC1_VOL_MASK 0x000F /* ADCL_DAC1_VOL - [3:0] */

3704

#define WM8994_ADCL_DAC1_VOL_SHIFT 0 /* ADCL_DAC1_VOL - [3:0] */

3705

#define WM8994_ADCL_DAC1_VOL_WIDTH 4 /* ADCL_DAC1_VOL - [3:0] */

3706

3707

/*

3708

* R1537 (0x601) - DAC1 Left Mixer Routing

3709

*/

3710

#define WM8994_ADCR_TO_DAC1L 0x0020 /* ADCR_TO_DAC1L */

3711

#define WM8994_ADCR_TO_DAC1L_MASK 0x0020 /* ADCR_TO_DAC1L */

3712

#define WM8994_ADCR_TO_DAC1L_SHIFT 5 /* ADCR_TO_DAC1L */

3713

#define WM8994_ADCR_TO_DAC1L_WIDTH 1 /* ADCR_TO_DAC1L */

3714

#define WM8994_ADCL_TO_DAC1L 0x0010 /* ADCL_TO_DAC1L */

3715

#define WM8994_ADCL_TO_DAC1L_MASK 0x0010 /* ADCL_TO_DAC1L */

3716

#define WM8994_ADCL_TO_DAC1L_SHIFT 4 /* ADCL_TO_DAC1L */

3717

#define WM8994_ADCL_TO_DAC1L_WIDTH 1 /* ADCL_TO_DAC1L */

3718

#define WM8994_AIF2DACL_TO_DAC1L 0x0004 /* AIF2DACL_TO_DAC1L */

3719

#define WM8994_AIF2DACL_TO_DAC1L_MASK 0x0004 /* AIF2DACL_TO_DAC1L */

3720

#define WM8994_AIF2DACL_TO_DAC1L_SHIFT 2 /* AIF2DACL_TO_DAC1L */

3721

#define WM8994_AIF2DACL_TO_DAC1L_WIDTH 1 /* AIF2DACL_TO_DAC1L */

3722

#define WM8994_AIF1DAC2L_TO_DAC1L 0x0002 /* AIF1DAC2L_TO_DAC1L */

3723

#define WM8994_AIF1DAC2L_TO_DAC1L_MASK 0x0002 /* AIF1DAC2L_TO_DAC1L */

3724

#define WM8994_AIF1DAC2L_TO_DAC1L_SHIFT 1 /* AIF1DAC2L_TO_DAC1L */

3725

#define WM8994_AIF1DAC2L_TO_DAC1L_WIDTH 1 /* AIF1DAC2L_TO_DAC1L */

3726

#define WM8994_AIF1DAC1L_TO_DAC1L 0x0001 /* AIF1DAC1L_TO_DAC1L */

3727

#define WM8994_AIF1DAC1L_TO_DAC1L_MASK 0x0001 /* AIF1DAC1L_TO_DAC1L */

3728

#define WM8994_AIF1DAC1L_TO_DAC1L_SHIFT 0 /* AIF1DAC1L_TO_DAC1L */

3729

#define WM8994_AIF1DAC1L_TO_DAC1L_WIDTH 1 /* AIF1DAC1L_TO_DAC1L */

3730

3731

/*

3732

* R1538 (0x602) - DAC1 Right Mixer Routing

3733

*/

3734

#define WM8994_ADCR_TO_DAC1R 0x0020 /* ADCR_TO_DAC1R */

3735

#define WM8994_ADCR_TO_DAC1R_MASK 0x0020 /* ADCR_TO_DAC1R */

3736

#define WM8994_ADCR_TO_DAC1R_SHIFT 5 /* ADCR_TO_DAC1R */

3737

#define WM8994_ADCR_TO_DAC1R_WIDTH 1 /* ADCR_TO_DAC1R */

3738

#define WM8994_ADCL_TO_DAC1R 0x0010 /* ADCL_TO_DAC1R */

3739

#define WM8994_ADCL_TO_DAC1R_MASK 0x0010 /* ADCL_TO_DAC1R */

3740

#define WM8994_ADCL_TO_DAC1R_SHIFT 4 /* ADCL_TO_DAC1R */

3741

#define WM8994_ADCL_TO_DAC1R_WIDTH 1 /* ADCL_TO_DAC1R */

3742

#define WM8994_AIF2DACR_TO_DAC1R 0x0004 /* AIF2DACR_TO_DAC1R */

3743

#define WM8994_AIF2DACR_TO_DAC1R_MASK 0x0004 /* AIF2DACR_TO_DAC1R */

3744

#define WM8994_AIF2DACR_TO_DAC1R_SHIFT 2 /* AIF2DACR_TO_DAC1R */

3745

#define WM8994_AIF2DACR_TO_DAC1R_WIDTH 1 /* AIF2DACR_TO_DAC1R */

3746

#define WM8994_AIF1DAC2R_TO_DAC1R 0x0002 /* AIF1DAC2R_TO_DAC1R */

3747

#define WM8994_AIF1DAC2R_TO_DAC1R_MASK 0x0002 /* AIF1DAC2R_TO_DAC1R */

3748

#define WM8994_AIF1DAC2R_TO_DAC1R_SHIFT 1 /* AIF1DAC2R_TO_DAC1R */

3749

#define WM8994_AIF1DAC2R_TO_DAC1R_WIDTH 1 /* AIF1DAC2R_TO_DAC1R */

3750

#define WM8994_AIF1DAC1R_TO_DAC1R 0x0001 /* AIF1DAC1R_TO_DAC1R */

3751

#define WM8994_AIF1DAC1R_TO_DAC1R_MASK 0x0001 /* AIF1DAC1R_TO_DAC1R */

3752

#define WM8994_AIF1DAC1R_TO_DAC1R_SHIFT 0 /* AIF1DAC1R_TO_DAC1R */

3753

#define WM8994_AIF1DAC1R_TO_DAC1R_WIDTH 1 /* AIF1DAC1R_TO_DAC1R */

3754

3755

/*

3756

* R1539 (0x603) - DAC2 Mixer Volumes

3757

*/

3758

#define WM8994_ADCR_DAC2_VOL_MASK 0x01E0 /* ADCR_DAC2_VOL - [8:5] */

3759

#define WM8994_ADCR_DAC2_VOL_SHIFT 5 /* ADCR_DAC2_VOL - [8:5] */

3760

#define WM8994_ADCR_DAC2_VOL_WIDTH 4 /* ADCR_DAC2_VOL - [8:5] */

3761

#define WM8994_ADCL_DAC2_VOL_MASK 0x000F /* ADCL_DAC2_VOL - [3:0] */

3762

#define WM8994_ADCL_DAC2_VOL_SHIFT 0 /* ADCL_DAC2_VOL - [3:0] */

3763

#define WM8994_ADCL_DAC2_VOL_WIDTH 4 /* ADCL_DAC2_VOL - [3:0] */

3764

3765

/*

3766

* R1540 (0x604) - DAC2 Left Mixer Routing

3767

*/

3768

#define WM8994_ADCR_TO_DAC2L 0x0020 /* ADCR_TO_DAC2L */

3769

#define WM8994_ADCR_TO_DAC2L_MASK 0x0020 /* ADCR_TO_DAC2L */

3770

#define WM8994_ADCR_TO_DAC2L_SHIFT 5 /* ADCR_TO_DAC2L */

3771

#define WM8994_ADCR_TO_DAC2L_WIDTH 1 /* ADCR_TO_DAC2L */

3772

#define WM8994_ADCL_TO_DAC2L 0x0010 /* ADCL_TO_DAC2L */

3773

#define WM8994_ADCL_TO_DAC2L_MASK 0x0010 /* ADCL_TO_DAC2L */

3774

#define WM8994_ADCL_TO_DAC2L_SHIFT 4 /* ADCL_TO_DAC2L */

3775

#define WM8994_ADCL_TO_DAC2L_WIDTH 1 /* ADCL_TO_DAC2L */

3776

#define WM8994_AIF2DACL_TO_DAC2L 0x0004 /* AIF2DACL_TO_DAC2L */

3777

#define WM8994_AIF2DACL_TO_DAC2L_MASK 0x0004 /* AIF2DACL_TO_DAC2L */

3778

#define WM8994_AIF2DACL_TO_DAC2L_SHIFT 2 /* AIF2DACL_TO_DAC2L */

3779

#define WM8994_AIF2DACL_TO_DAC2L_WIDTH 1 /* AIF2DACL_TO_DAC2L */

3780

#define WM8994_AIF1DAC2L_TO_DAC2L 0x0002 /* AIF1DAC2L_TO_DAC2L */

3781

#define WM8994_AIF1DAC2L_TO_DAC2L_MASK 0x0002 /* AIF1DAC2L_TO_DAC2L */

3782

#define WM8994_AIF1DAC2L_TO_DAC2L_SHIFT 1 /* AIF1DAC2L_TO_DAC2L */

3783

#define WM8994_AIF1DAC2L_TO_DAC2L_WIDTH 1 /* AIF1DAC2L_TO_DAC2L */

3784

#define WM8994_AIF1DAC1L_TO_DAC2L 0x0001 /* AIF1DAC1L_TO_DAC2L */

3785

#define WM8994_AIF1DAC1L_TO_DAC2L_MASK 0x0001 /* AIF1DAC1L_TO_DAC2L */

3786

#define WM8994_AIF1DAC1L_TO_DAC2L_SHIFT 0 /* AIF1DAC1L_TO_DAC2L */

3787

#define WM8994_AIF1DAC1L_TO_DAC2L_WIDTH 1 /* AIF1DAC1L_TO_DAC2L */

3788

3789

/*

3790

* R1541 (0x605) - DAC2 Right Mixer Routing

3791

*/

3792

#define WM8994_ADCR_TO_DAC2R 0x0020 /* ADCR_TO_DAC2R */

3793

#define WM8994_ADCR_TO_DAC2R_MASK 0x0020 /* ADCR_TO_DAC2R */

3794

#define WM8994_ADCR_TO_DAC2R_SHIFT 5 /* ADCR_TO_DAC2R */

3795

#define WM8994_ADCR_TO_DAC2R_WIDTH 1 /* ADCR_TO_DAC2R */

3796

#define WM8994_ADCL_TO_DAC2R 0x0010 /* ADCL_TO_DAC2R */

3797

#define WM8994_ADCL_TO_DAC2R_MASK 0x0010 /* ADCL_TO_DAC2R */

3798

#define WM8994_ADCL_TO_DAC2R_SHIFT 4 /* ADCL_TO_DAC2R */

3799

#define WM8994_ADCL_TO_DAC2R_WIDTH 1 /* ADCL_TO_DAC2R */

3800

#define WM8994_AIF2DACR_TO_DAC2R 0x0004 /* AIF2DACR_TO_DAC2R */

3801

#define WM8994_AIF2DACR_TO_DAC2R_MASK 0x0004 /* AIF2DACR_TO_DAC2R */

3802

#define WM8994_AIF2DACR_TO_DAC2R_SHIFT 2 /* AIF2DACR_TO_DAC2R */

3803

#define WM8994_AIF2DACR_TO_DAC2R_WIDTH 1 /* AIF2DACR_TO_DAC2R */

3804

#define WM8994_AIF1DAC2R_TO_DAC2R 0x0002 /* AIF1DAC2R_TO_DAC2R */

3805

#define WM8994_AIF1DAC2R_TO_DAC2R_MASK 0x0002 /* AIF1DAC2R_TO_DAC2R */

3806

#define WM8994_AIF1DAC2R_TO_DAC2R_SHIFT 1 /* AIF1DAC2R_TO_DAC2R */

3807

#define WM8994_AIF1DAC2R_TO_DAC2R_WIDTH 1 /* AIF1DAC2R_TO_DAC2R */

3808

#define WM8994_AIF1DAC1R_TO_DAC2R 0x0001 /* AIF1DAC1R_TO_DAC2R */

3809

#define WM8994_AIF1DAC1R_TO_DAC2R_MASK 0x0001 /* AIF1DAC1R_TO_DAC2R */

3810

#define WM8994_AIF1DAC1R_TO_DAC2R_SHIFT 0 /* AIF1DAC1R_TO_DAC2R */

3811

#define WM8994_AIF1DAC1R_TO_DAC2R_WIDTH 1 /* AIF1DAC1R_TO_DAC2R */

3812

3813

/*

3814

* R1542 (0x606) - AIF1 ADC1 Left Mixer Routing

3815

*/

3816

#define WM8994_ADC1L_TO_AIF1ADC1L 0x0002 /* ADC1L_TO_AIF1ADC1L */

3817

#define WM8994_ADC1L_TO_AIF1ADC1L_MASK 0x0002 /* ADC1L_TO_AIF1ADC1L */

3818

#define WM8994_ADC1L_TO_AIF1ADC1L_SHIFT 1 /* ADC1L_TO_AIF1ADC1L */

3819

#define WM8994_ADC1L_TO_AIF1ADC1L_WIDTH 1 /* ADC1L_TO_AIF1ADC1L */

3820

#define WM8994_AIF2DACL_TO_AIF1ADC1L 0x0001 /* AIF2DACL_TO_AIF1ADC1L */

3821

#define WM8994_AIF2DACL_TO_AIF1ADC1L_MASK 0x0001 /* AIF2DACL_TO_AIF1ADC1L */

3822

#define WM8994_AIF2DACL_TO_AIF1ADC1L_SHIFT 0 /* AIF2DACL_TO_AIF1ADC1L */

3823

#define WM8994_AIF2DACL_TO_AIF1ADC1L_WIDTH 1 /* AIF2DACL_TO_AIF1ADC1L */

3824

3825

/*

3826

* R1543 (0x607) - AIF1 ADC1 Right Mixer Routing

3827

*/

3828

#define WM8994_ADC1R_TO_AIF1ADC1R 0x0002 /* ADC1R_TO_AIF1ADC1R */

3829

#define WM8994_ADC1R_TO_AIF1ADC1R_MASK 0x0002 /* ADC1R_TO_AIF1ADC1R */

3830

#define WM8994_ADC1R_TO_AIF1ADC1R_SHIFT 1 /* ADC1R_TO_AIF1ADC1R */

3831

#define WM8994_ADC1R_TO_AIF1ADC1R_WIDTH 1 /* ADC1R_TO_AIF1ADC1R */

3832

#define WM8994_AIF2DACR_TO_AIF1ADC1R 0x0001 /* AIF2DACR_TO_AIF1ADC1R */

3833

#define WM8994_AIF2DACR_TO_AIF1ADC1R_MASK 0x0001 /* AIF2DACR_TO_AIF1ADC1R */

3834

#define WM8994_AIF2DACR_TO_AIF1ADC1R_SHIFT 0 /* AIF2DACR_TO_AIF1ADC1R */

3835

#define WM8994_AIF2DACR_TO_AIF1ADC1R_WIDTH 1 /* AIF2DACR_TO_AIF1ADC1R */

3836

3837

/*

3838

* R1544 (0x608) - AIF1 ADC2 Left Mixer Routing

3839

*/

3840

#define WM8994_ADC2L_TO_AIF1ADC2L 0x0002 /* ADC2L_TO_AIF1ADC2L */

3841

#define WM8994_ADC2L_TO_AIF1ADC2L_MASK 0x0002 /* ADC2L_TO_AIF1ADC2L */

3842

#define WM8994_ADC2L_TO_AIF1ADC2L_SHIFT 1 /* ADC2L_TO_AIF1ADC2L */

3843

#define WM8994_ADC2L_TO_AIF1ADC2L_WIDTH 1 /* ADC2L_TO_AIF1ADC2L */

3844

#define WM8994_AIF2DACL_TO_AIF1ADC2L 0x0001 /* AIF2DACL_TO_AIF1ADC2L */

3845

#define WM8994_AIF2DACL_TO_AIF1ADC2L_MASK 0x0001 /* AIF2DACL_TO_AIF1ADC2L */

3846

#define WM8994_AIF2DACL_TO_AIF1ADC2L_SHIFT 0 /* AIF2DACL_TO_AIF1ADC2L */

3847

#define WM8994_AIF2DACL_TO_AIF1ADC2L_WIDTH 1 /* AIF2DACL_TO_AIF1ADC2L */

3848

3849

/*

3850

* R1545 (0x609) - AIF1 ADC2 Right mixer Routing

3851

*/

3852

#define WM8994_ADC2R_TO_AIF1ADC2R 0x0002 /* ADC2R_TO_AIF1ADC2R */

3853

#define WM8994_ADC2R_TO_AIF1ADC2R_MASK 0x0002 /* ADC2R_TO_AIF1ADC2R */

3854

#define WM8994_ADC2R_TO_AIF1ADC2R_SHIFT 1 /* ADC2R_TO_AIF1ADC2R */

3855

#define WM8994_ADC2R_TO_AIF1ADC2R_WIDTH 1 /* ADC2R_TO_AIF1ADC2R */

3856

#define WM8994_AIF2DACR_TO_AIF1ADC2R 0x0001 /* AIF2DACR_TO_AIF1ADC2R */

3857

#define WM8994_AIF2DACR_TO_AIF1ADC2R_MASK 0x0001 /* AIF2DACR_TO_AIF1ADC2R */

3858

#define WM8994_AIF2DACR_TO_AIF1ADC2R_SHIFT 0 /* AIF2DACR_TO_AIF1ADC2R */

3859

#define WM8994_AIF2DACR_TO_AIF1ADC2R_WIDTH 1 /* AIF2DACR_TO_AIF1ADC2R */

3860

3861

/*

3862

* R1552 (0x610) - DAC1 Left Volume

3863

*/

3864

#define WM8994_DAC1L_MUTE 0x0200 /* DAC1L_MUTE */

3865

#define WM8994_DAC1L_MUTE_MASK 0x0200 /* DAC1L_MUTE */

3866

#define WM8994_DAC1L_MUTE_SHIFT 9 /* DAC1L_MUTE */

3867

#define WM8994_DAC1L_MUTE_WIDTH 1 /* DAC1L_MUTE */

3868

#define WM8994_DAC1_VU 0x0100 /* DAC1_VU */

3869

#define WM8994_DAC1_VU_MASK 0x0100 /* DAC1_VU */

3870

#define WM8994_DAC1_VU_SHIFT 8 /* DAC1_VU */

3871

#define WM8994_DAC1_VU_WIDTH 1 /* DAC1_VU */

3872

#define WM8994_DAC1L_VOL_MASK 0x00FF /* DAC1L_VOL - [7:0] */

3873

#define WM8994_DAC1L_VOL_SHIFT 0 /* DAC1L_VOL - [7:0] */

3874

#define WM8994_DAC1L_VOL_WIDTH 8 /* DAC1L_VOL - [7:0] */

3875

3876

/*

3877

* R1553 (0x611) - DAC1 Right Volume

3878

*/

3879

#define WM8994_DAC1R_MUTE 0x0200 /* DAC1R_MUTE */

3880

#define WM8994_DAC1R_MUTE_MASK 0x0200 /* DAC1R_MUTE */

3881

#define WM8994_DAC1R_MUTE_SHIFT 9 /* DAC1R_MUTE */

3882

#define WM8994_DAC1R_MUTE_WIDTH 1 /* DAC1R_MUTE */

3883

#define WM8994_DAC1_VU 0x0100 /* DAC1_VU */

3884

#define WM8994_DAC1_VU_MASK 0x0100 /* DAC1_VU */

3885

#define WM8994_DAC1_VU_SHIFT 8 /* DAC1_VU */

3886

#define WM8994_DAC1_VU_WIDTH 1 /* DAC1_VU */

3887

#define WM8994_DAC1R_VOL_MASK 0x00FF /* DAC1R_VOL - [7:0] */

3888

#define WM8994_DAC1R_VOL_SHIFT 0 /* DAC1R_VOL - [7:0] */

3889

#define WM8994_DAC1R_VOL_WIDTH 8 /* DAC1R_VOL - [7:0] */

3890

3891

/*

3892

* R1554 (0x612) - DAC2 Left Volume

3893

*/

3894

#define WM8994_DAC2L_MUTE 0x0200 /* DAC2L_MUTE */

3895

#define WM8994_DAC2L_MUTE_MASK 0x0200 /* DAC2L_MUTE */

3896

#define WM8994_DAC2L_MUTE_SHIFT 9 /* DAC2L_MUTE */

3897

#define WM8994_DAC2L_MUTE_WIDTH 1 /* DAC2L_MUTE */

3898

#define WM8994_DAC2_VU 0x0100 /* DAC2_VU */

3899

#define WM8994_DAC2_VU_MASK 0x0100 /* DAC2_VU */

3900

#define WM8994_DAC2_VU_SHIFT 8 /* DAC2_VU */

3901

#define WM8994_DAC2_VU_WIDTH 1 /* DAC2_VU */

3902

#define WM8994_DAC2L_VOL_MASK 0x00FF /* DAC2L_VOL - [7:0] */

3903

#define WM8994_DAC2L_VOL_SHIFT 0 /* DAC2L_VOL - [7:0] */

3904

#define WM8994_DAC2L_VOL_WIDTH 8 /* DAC2L_VOL - [7:0] */

3905

3906

/*

3907

* R1555 (0x613) - DAC2 Right Volume

3908

*/

3909

#define WM8994_DAC2R_MUTE 0x0200 /* DAC2R_MUTE */

3910

#define WM8994_DAC2R_MUTE_MASK 0x0200 /* DAC2R_MUTE */

3911

#define WM8994_DAC2R_MUTE_SHIFT 9 /* DAC2R_MUTE */

3912

#define WM8994_DAC2R_MUTE_WIDTH 1 /* DAC2R_MUTE */

3913

#define WM8994_DAC2_VU 0x0100 /* DAC2_VU */

3914

#define WM8994_DAC2_VU_MASK 0x0100 /* DAC2_VU */

3915

#define WM8994_DAC2_VU_SHIFT 8 /* DAC2_VU */

3916

#define WM8994_DAC2_VU_WIDTH 1 /* DAC2_VU */

3917

#define WM8994_DAC2R_VOL_MASK 0x00FF /* DAC2R_VOL - [7:0] */

3918

#define WM8994_DAC2R_VOL_SHIFT 0 /* DAC2R_VOL - [7:0] */

3919

#define WM8994_DAC2R_VOL_WIDTH 8 /* DAC2R_VOL - [7:0] */

3920

3921

/*

3922

* R1556 (0x614) - DAC Softmute

3923

*/

3924

#define WM8994_DAC_SOFTMUTEMODE 0x0002 /* DAC_SOFTMUTEMODE */

3925

#define WM8994_DAC_SOFTMUTEMODE_MASK 0x0002 /* DAC_SOFTMUTEMODE */

3926

#define WM8994_DAC_SOFTMUTEMODE_SHIFT 1 /* DAC_SOFTMUTEMODE */

3927

#define WM8994_DAC_SOFTMUTEMODE_WIDTH 1 /* DAC_SOFTMUTEMODE */

3928

#define WM8994_DAC_MUTERATE 0x0001 /* DAC_MUTERATE */

3929

#define WM8994_DAC_MUTERATE_MASK 0x0001 /* DAC_MUTERATE */

3930

#define WM8994_DAC_MUTERATE_SHIFT 0 /* DAC_MUTERATE */

3931

#define WM8994_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */

3932

3933

/*

3934

* R1568 (0x620) - Oversampling

3935

*/

3936

#define WM8994_ADC_OSR128 0x0002 /* ADC_OSR128 */

3937

#define WM8994_ADC_OSR128_MASK 0x0002 /* ADC_OSR128 */

3938

#define WM8994_ADC_OSR128_SHIFT 1 /* ADC_OSR128 */

3939

#define WM8994_ADC_OSR128_WIDTH 1 /* ADC_OSR128 */

3940

#define WM8994_DAC_OSR128 0x0001 /* DAC_OSR128 */

3941

#define WM8994_DAC_OSR128_MASK 0x0001 /* DAC_OSR128 */

3942

#define WM8994_DAC_OSR128_SHIFT 0 /* DAC_OSR128 */

3943

#define WM8994_DAC_OSR128_WIDTH 1 /* DAC_OSR128 */

3944

3945

/*

3946

* R1569 (0x621) - Sidetone

3947

*/

3948

#define WM8994_ST_HPF_CUT_MASK 0x0380 /* ST_HPF_CUT - [9:7] */

3949

#define WM8994_ST_HPF_CUT_SHIFT 7 /* ST_HPF_CUT - [9:7] */

3950

#define WM8994_ST_HPF_CUT_WIDTH 3 /* ST_HPF_CUT - [9:7] */

3951

#define WM8994_ST_HPF 0x0040 /* ST_HPF */

3952

#define WM8994_ST_HPF_MASK 0x0040 /* ST_HPF */

3953

#define WM8994_ST_HPF_SHIFT 6 /* ST_HPF */

3954

#define WM8994_ST_HPF_WIDTH 1 /* ST_HPF */

3955

#define WM8994_STR_SEL 0x0002 /* STR_SEL */

3956

#define WM8994_STR_SEL_MASK 0x0002 /* STR_SEL */

3957

#define WM8994_STR_SEL_SHIFT 1 /* STR_SEL */

3958

#define WM8994_STR_SEL_WIDTH 1 /* STR_SEL */

3959

#define WM8994_STL_SEL 0x0001 /* STL_SEL */

3960

#define WM8994_STL_SEL_MASK 0x0001 /* STL_SEL */

3961

#define WM8994_STL_SEL_SHIFT 0 /* STL_SEL */

3962

#define WM8994_STL_SEL_WIDTH 1 /* STL_SEL */

3963

3964

/*

3965

* R1824 (0x720) - Pull Control (1)

3966

*/

3967

#define WM8994_DMICDAT2_PU 0x0800 /* DMICDAT2_PU */

3968

#define WM8994_DMICDAT2_PU_MASK 0x0800 /* DMICDAT2_PU */

3969

#define WM8994_DMICDAT2_PU_SHIFT 11 /* DMICDAT2_PU */

3970

#define WM8994_DMICDAT2_PU_WIDTH 1 /* DMICDAT2_PU */

3971

#define WM8994_DMICDAT2_PD 0x0400 /* DMICDAT2_PD */

3972

#define WM8994_DMICDAT2_PD_MASK 0x0400 /* DMICDAT2_PD */

3973

#define WM8994_DMICDAT2_PD_SHIFT 10 /* DMICDAT2_PD */

3974

#define WM8994_DMICDAT2_PD_WIDTH 1 /* DMICDAT2_PD */

3975

#define WM8994_DMICDAT1_PU 0x0200 /* DMICDAT1_PU */

3976

#define WM8994_DMICDAT1_PU_MASK 0x0200 /* DMICDAT1_PU */

3977

#define WM8994_DMICDAT1_PU_SHIFT 9 /* DMICDAT1_PU */

3978

#define WM8994_DMICDAT1_PU_WIDTH 1 /* DMICDAT1_PU */

3979

#define WM8994_DMICDAT1_PD 0x0100 /* DMICDAT1_PD */

3980

#define WM8994_DMICDAT1_PD_MASK 0x0100 /* DMICDAT1_PD */

3981

#define WM8994_DMICDAT1_PD_SHIFT 8 /* DMICDAT1_PD */

3982

#define WM8994_DMICDAT1_PD_WIDTH 1 /* DMICDAT1_PD */

3983

#define WM8994_MCLK1_PU 0x0080 /* MCLK1_PU */

3984

#define WM8994_MCLK1_PU_MASK 0x0080 /* MCLK1_PU */

3985

#define WM8994_MCLK1_PU_SHIFT 7 /* MCLK1_PU */

3986

#define WM8994_MCLK1_PU_WIDTH 1 /* MCLK1_PU */

3987

#define WM8994_MCLK1_PD 0x0040 /* MCLK1_PD */

3988

#define WM8994_MCLK1_PD_MASK 0x0040 /* MCLK1_PD */

3989

#define WM8994_MCLK1_PD_SHIFT 6 /* MCLK1_PD */

3990

#define WM8994_MCLK1_PD_WIDTH 1 /* MCLK1_PD */

3991

#define WM8994_DACDAT1_PU 0x0020 /* DACDAT1_PU */

3992

#define WM8994_DACDAT1_PU_MASK 0x0020 /* DACDAT1_PU */

3993

#define WM8994_DACDAT1_PU_SHIFT 5 /* DACDAT1_PU */

3994

#define WM8994_DACDAT1_PU_WIDTH 1 /* DACDAT1_PU */

3995

#define WM8994_DACDAT1_PD 0x0010 /* DACDAT1_PD */

3996

#define WM8994_DACDAT1_PD_MASK 0x0010 /* DACDAT1_PD */

3997

#define WM8994_DACDAT1_PD_SHIFT 4 /* DACDAT1_PD */

3998

#define WM8994_DACDAT1_PD_WIDTH 1 /* DACDAT1_PD */

3999

#define WM8994_DACLRCLK1_PU 0x0008 /* DACLRCLK1_PU */

4000

#define WM8994_DACLRCLK1_PU_MASK 0x0008 /* DACLRCLK1_PU */

4001

#define WM8994_DACLRCLK1_PU_SHIFT 3 /* DACLRCLK1_PU */

4002

#define WM8994_DACLRCLK1_PU_WIDTH 1 /* DACLRCLK1_PU */

4003

#define WM8994_DACLRCLK1_PD 0x0004 /* DACLRCLK1_PD */

4004

#define WM8994_DACLRCLK1_PD_MASK 0x0004 /* DACLRCLK1_PD */

4005

#define WM8994_DACLRCLK1_PD_SHIFT 2 /* DACLRCLK1_PD */

4006

#define WM8994_DACLRCLK1_PD_WIDTH 1 /* DACLRCLK1_PD */

4007

#define WM8994_BCLK1_PU 0x0002 /* BCLK1_PU */

4008

#define WM8994_BCLK1_PU_MASK 0x0002 /* BCLK1_PU */

4009

#define WM8994_BCLK1_PU_SHIFT 1 /* BCLK1_PU */

4010

#define WM8994_BCLK1_PU_WIDTH 1 /* BCLK1_PU */

4011

#define WM8994_BCLK1_PD 0x0001 /* BCLK1_PD */

4012

#define WM8994_BCLK1_PD_MASK 0x0001 /* BCLK1_PD */

4013

#define WM8994_BCLK1_PD_SHIFT 0 /* BCLK1_PD */

4014

#define WM8994_BCLK1_PD_WIDTH 1 /* BCLK1_PD */

4015

4016

/*

4017

* R1825 (0x721) - Pull Control (2)

4018

*/

4019

#define WM8994_CSNADDR_PD 0x0100 /* CSNADDR_PD */

4020

#define WM8994_CSNADDR_PD_MASK 0x0100 /* CSNADDR_PD */

4021

#define WM8994_CSNADDR_PD_SHIFT 8 /* CSNADDR_PD */

4022

#define WM8994_CSNADDR_PD_WIDTH 1 /* CSNADDR_PD */

4023

#define WM8994_LDO2ENA_PD 0x0040 /* LDO2ENA_PD */

4024

#define WM8994_LDO2ENA_PD_MASK 0x0040 /* LDO2ENA_PD */

4025

#define WM8994_LDO2ENA_PD_SHIFT 6 /* LDO2ENA_PD */

4026

#define WM8994_LDO2ENA_PD_WIDTH 1 /* LDO2ENA_PD */

4027

#define WM8994_LDO1ENA_PD 0x0010 /* LDO1ENA_PD */

4028

#define WM8994_LDO1ENA_PD_MASK 0x0010 /* LDO1ENA_PD */

4029

#define WM8994_LDO1ENA_PD_SHIFT 4 /* LDO1ENA_PD */

4030

#define WM8994_LDO1ENA_PD_WIDTH 1 /* LDO1ENA_PD */

4031

#define WM8994_CIFMODE_PD 0x0004 /* CIFMODE_PD */

4032

#define WM8994_CIFMODE_PD_MASK 0x0004 /* CIFMODE_PD */

4033

#define WM8994_CIFMODE_PD_SHIFT 2 /* CIFMODE_PD */

4034

#define WM8994_CIFMODE_PD_WIDTH 1 /* CIFMODE_PD */

4035

#define WM8994_SPKMODE_PU 0x0002 /* SPKMODE_PU */

4036

#define WM8994_SPKMODE_PU_MASK 0x0002 /* SPKMODE_PU */

4037

#define WM8994_SPKMODE_PU_SHIFT 1 /* SPKMODE_PU */

4038

#define WM8994_SPKMODE_PU_WIDTH 1 /* SPKMODE_PU */

4039

4040

/*

4041

* R1840 (0x730) - Interrupt Status 1

4042

*/

4043

#define WM8994_GP11_EINT 0x0400 /* GP11_EINT */

4044

#define WM8994_GP11_EINT_MASK 0x0400 /* GP11_EINT */

4045

#define WM8994_GP11_EINT_SHIFT 10 /* GP11_EINT */

4046

#define WM8994_GP11_EINT_WIDTH 1 /* GP11_EINT */

4047

#define WM8994_GP10_EINT 0x0200 /* GP10_EINT */

4048

#define WM8994_GP10_EINT_MASK 0x0200 /* GP10_EINT */

4049

#define WM8994_GP10_EINT_SHIFT 9 /* GP10_EINT */

4050

#define WM8994_GP10_EINT_WIDTH 1 /* GP10_EINT */

4051

#define WM8994_GP9_EINT 0x0100 /* GP9_EINT */

4052

#define WM8994_GP9_EINT_MASK 0x0100 /* GP9_EINT */

4053

#define WM8994_GP9_EINT_SHIFT 8 /* GP9_EINT */

4054

#define WM8994_GP9_EINT_WIDTH 1 /* GP9_EINT */

4055

#define WM8994_GP8_EINT 0x0080 /* GP8_EINT */

4056

#define WM8994_GP8_EINT_MASK 0x0080 /* GP8_EINT */

4057

#define WM8994_GP8_EINT_SHIFT 7 /* GP8_EINT */

4058

#define WM8994_GP8_EINT_WIDTH 1 /* GP8_EINT */

4059

#define WM8994_GP7_EINT 0x0040 /* GP7_EINT */

4060

#define WM8994_GP7_EINT_MASK 0x0040 /* GP7_EINT */

4061

#define WM8994_GP7_EINT_SHIFT 6 /* GP7_EINT */

4062

#define WM8994_GP7_EINT_WIDTH 1 /* GP7_EINT */

4063

#define WM8994_GP6_EINT 0x0020 /* GP6_EINT */

4064

#define WM8994_GP6_EINT_MASK 0x0020 /* GP6_EINT */

4065

#define WM8994_GP6_EINT_SHIFT 5 /* GP6_EINT */

4066

#define WM8994_GP6_EINT_WIDTH 1 /* GP6_EINT */

4067

#define WM8994_GP5_EINT 0x0010 /* GP5_EINT */

4068

#define WM8994_GP5_EINT_MASK 0x0010 /* GP5_EINT */

4069

#define WM8994_GP5_EINT_SHIFT 4 /* GP5_EINT */

4070

#define WM8994_GP5_EINT_WIDTH 1 /* GP5_EINT */

4071

#define WM8994_GP4_EINT 0x0008 /* GP4_EINT */

4072

#define WM8994_GP4_EINT_MASK 0x0008 /* GP4_EINT */

4073

#define WM8994_GP4_EINT_SHIFT 3 /* GP4_EINT */

4074

#define WM8994_GP4_EINT_WIDTH 1 /* GP4_EINT */

4075

#define WM8994_GP3_EINT 0x0004 /* GP3_EINT */

4076

#define WM8994_GP3_EINT_MASK 0x0004 /* GP3_EINT */

4077

#define WM8994_GP3_EINT_SHIFT 2 /* GP3_EINT */

4078

#define WM8994_GP3_EINT_WIDTH 1 /* GP3_EINT */

4079

#define WM8994_GP2_EINT 0x0002 /* GP2_EINT */

4080

#define WM8994_GP2_EINT_MASK 0x0002 /* GP2_EINT */

4081

#define WM8994_GP2_EINT_SHIFT 1 /* GP2_EINT */

4082

#define WM8994_GP2_EINT_WIDTH 1 /* GP2_EINT */

4083

#define WM8994_GP1_EINT 0x0001 /* GP1_EINT */

4084

#define WM8994_GP1_EINT_MASK 0x0001 /* GP1_EINT */

4085

#define WM8994_GP1_EINT_SHIFT 0 /* GP1_EINT */

4086

#define WM8994_GP1_EINT_WIDTH 1 /* GP1_EINT */

4087

4088

/*

4089

* R1841 (0x731) - Interrupt Status 2

4090

*/

4091

#define WM8994_TEMP_WARN_EINT 0x8000 /* TEMP_WARN_EINT */

4092

#define WM8994_TEMP_WARN_EINT_MASK 0x8000 /* TEMP_WARN_EINT */

4093

#define WM8994_TEMP_WARN_EINT_SHIFT 15 /* TEMP_WARN_EINT */

4094

#define WM8994_TEMP_WARN_EINT_WIDTH 1 /* TEMP_WARN_EINT */

4095

#define WM8994_DCS_DONE_EINT 0x4000 /* DCS_DONE_EINT */

4096

#define WM8994_DCS_DONE_EINT_MASK 0x4000 /* DCS_DONE_EINT */

4097

#define WM8994_DCS_DONE_EINT_SHIFT 14 /* DCS_DONE_EINT */

4098

#define WM8994_DCS_DONE_EINT_WIDTH 1 /* DCS_DONE_EINT */

4099

#define WM8994_WSEQ_DONE_EINT 0x2000 /* WSEQ_DONE_EINT */

4100

#define WM8994_WSEQ_DONE_EINT_MASK 0x2000 /* WSEQ_DONE_EINT */

4101

#define WM8994_WSEQ_DONE_EINT_SHIFT 13 /* WSEQ_DONE_EINT */

4102

#define WM8994_WSEQ_DONE_EINT_WIDTH 1 /* WSEQ_DONE_EINT */

4103

#define WM8994_FIFOS_ERR_EINT 0x1000 /* FIFOS_ERR_EINT */

4104

#define WM8994_FIFOS_ERR_EINT_MASK 0x1000 /* FIFOS_ERR_EINT */

4105

#define WM8994_FIFOS_ERR_EINT_SHIFT 12 /* FIFOS_ERR_EINT */

4106

#define WM8994_FIFOS_ERR_EINT_WIDTH 1 /* FIFOS_ERR_EINT */

4107

#define WM8994_AIF2DRC_SIG_DET_EINT 0x0800 /* AIF2DRC_SIG_DET_EINT */

4108

#define WM8994_AIF2DRC_SIG_DET_EINT_MASK 0x0800 /* AIF2DRC_SIG_DET_EINT */

4109

#define WM8994_AIF2DRC_SIG_DET_EINT_SHIFT 11 /* AIF2DRC_SIG_DET_EINT */

4110

#define WM8994_AIF2DRC_SIG_DET_EINT_WIDTH 1 /* AIF2DRC_SIG_DET_EINT */

4111

#define WM8994_AIF1DRC2_SIG_DET_EINT 0x0400 /* AIF1DRC2_SIG_DET_EINT */

4112

#define WM8994_AIF1DRC2_SIG_DET_EINT_MASK 0x0400 /* AIF1DRC2_SIG_DET_EINT */

4113

#define WM8994_AIF1DRC2_SIG_DET_EINT_SHIFT 10 /* AIF1DRC2_SIG_DET_EINT */

4114

#define WM8994_AIF1DRC2_SIG_DET_EINT_WIDTH 1 /* AIF1DRC2_SIG_DET_EINT */

4115

#define WM8994_AIF1DRC1_SIG_DET_EINT 0x0200 /* AIF1DRC1_SIG_DET_EINT */

4116

#define WM8994_AIF1DRC1_SIG_DET_EINT_MASK 0x0200 /* AIF1DRC1_SIG_DET_EINT */

4117

#define WM8994_AIF1DRC1_SIG_DET_EINT_SHIFT 9 /* AIF1DRC1_SIG_DET_EINT */

4118

#define WM8994_AIF1DRC1_SIG_DET_EINT_WIDTH 1 /* AIF1DRC1_SIG_DET_EINT */

4119

#define WM8994_SRC2_LOCK_EINT 0x0100 /* SRC2_LOCK_EINT */

4120

#define WM8994_SRC2_LOCK_EINT_MASK 0x0100 /* SRC2_LOCK_EINT */

4121

#define WM8994_SRC2_LOCK_EINT_SHIFT 8 /* SRC2_LOCK_EINT */

4122

#define WM8994_SRC2_LOCK_EINT_WIDTH 1 /* SRC2_LOCK_EINT */

4123

#define WM8994_SRC1_LOCK_EINT 0x0080 /* SRC1_LOCK_EINT */

4124

#define WM8994_SRC1_LOCK_EINT_MASK 0x0080 /* SRC1_LOCK_EINT */

4125

#define WM8994_SRC1_LOCK_EINT_SHIFT 7 /* SRC1_LOCK_EINT */

4126

#define WM8994_SRC1_LOCK_EINT_WIDTH 1 /* SRC1_LOCK_EINT */

4127

#define WM8994_FLL2_LOCK_EINT 0x0040 /* FLL2_LOCK_EINT */

4128

#define WM8994_FLL2_LOCK_EINT_MASK 0x0040 /* FLL2_LOCK_EINT */

4129

#define WM8994_FLL2_LOCK_EINT_SHIFT 6 /* FLL2_LOCK_EINT */

4130

#define WM8994_FLL2_LOCK_EINT_WIDTH 1 /* FLL2_LOCK_EINT */

4131

#define WM8994_FLL1_LOCK_EINT 0x0020 /* FLL1_LOCK_EINT */

4132

#define WM8994_FLL1_LOCK_EINT_MASK 0x0020 /* FLL1_LOCK_EINT */

4133

#define WM8994_FLL1_LOCK_EINT_SHIFT 5 /* FLL1_LOCK_EINT */

4134

#define WM8994_FLL1_LOCK_EINT_WIDTH 1 /* FLL1_LOCK_EINT */

4135

#define WM8994_MIC2_SHRT_EINT 0x0010 /* MIC2_SHRT_EINT */

4136

#define WM8994_MIC2_SHRT_EINT_MASK 0x0010 /* MIC2_SHRT_EINT */

4137

#define WM8994_MIC2_SHRT_EINT_SHIFT 4 /* MIC2_SHRT_EINT */

4138

#define WM8994_MIC2_SHRT_EINT_WIDTH 1 /* MIC2_SHRT_EINT */

4139

#define WM8994_MIC2_DET_EINT 0x0008 /* MIC2_DET_EINT */

4140

#define WM8994_MIC2_DET_EINT_MASK 0x0008 /* MIC2_DET_EINT */

4141

#define WM8994_MIC2_DET_EINT_SHIFT 3 /* MIC2_DET_EINT */

4142

#define WM8994_MIC2_DET_EINT_WIDTH 1 /* MIC2_DET_EINT */

4143

#define WM8994_MIC1_SHRT_EINT 0x0004 /* MIC1_SHRT_EINT */

4144

#define WM8994_MIC1_SHRT_EINT_MASK 0x0004 /* MIC1_SHRT_EINT */

4145

#define WM8994_MIC1_SHRT_EINT_SHIFT 2 /* MIC1_SHRT_EINT */

4146

#define WM8994_MIC1_SHRT_EINT_WIDTH 1 /* MIC1_SHRT_EINT */

4147

#define WM8994_MIC1_DET_EINT 0x0002 /* MIC1_DET_EINT */

4148

#define WM8994_MIC1_DET_EINT_MASK 0x0002 /* MIC1_DET_EINT */

4149

#define WM8994_MIC1_DET_EINT_SHIFT 1 /* MIC1_DET_EINT */

4150

#define WM8994_MIC1_DET_EINT_WIDTH 1 /* MIC1_DET_EINT */

4151

#define WM8994_TEMP_SHUT_EINT 0x0001 /* TEMP_SHUT_EINT */

4152

#define WM8994_TEMP_SHUT_EINT_MASK 0x0001 /* TEMP_SHUT_EINT */

4153

#define WM8994_TEMP_SHUT_EINT_SHIFT 0 /* TEMP_SHUT_EINT */

4154

#define WM8994_TEMP_SHUT_EINT_WIDTH 1 /* TEMP_SHUT_EINT */

4155

4156

/*

4157

* R1842 (0x732) - Interrupt Raw Status 2

4158

*/

4159

#define WM8994_TEMP_WARN_STS 0x8000 /* TEMP_WARN_STS */

4160

#define WM8994_TEMP_WARN_STS_MASK 0x8000 /* TEMP_WARN_STS */

4161

#define WM8994_TEMP_WARN_STS_SHIFT 15 /* TEMP_WARN_STS */

4162

#define WM8994_TEMP_WARN_STS_WIDTH 1 /* TEMP_WARN_STS */

4163

#define WM8994_DCS_DONE_STS 0x4000 /* DCS_DONE_STS */

4164

#define WM8994_DCS_DONE_STS_MASK 0x4000 /* DCS_DONE_STS */

4165

#define WM8994_DCS_DONE_STS_SHIFT 14 /* DCS_DONE_STS */

4166

#define WM8994_DCS_DONE_STS_WIDTH 1 /* DCS_DONE_STS */

4167

#define WM8994_WSEQ_DONE_STS 0x2000 /* WSEQ_DONE_STS */

4168

#define WM8994_WSEQ_DONE_STS_MASK 0x2000 /* WSEQ_DONE_STS */

4169

#define WM8994_WSEQ_DONE_STS_SHIFT 13 /* WSEQ_DONE_STS */

4170

#define WM8994_WSEQ_DONE_STS_WIDTH 1 /* WSEQ_DONE_STS */

4171

#define WM8994_FIFOS_ERR_STS 0x1000 /* FIFOS_ERR_STS */

4172

#define WM8994_FIFOS_ERR_STS_MASK 0x1000 /* FIFOS_ERR_STS */

4173

#define WM8994_FIFOS_ERR_STS_SHIFT 12 /* FIFOS_ERR_STS */

4174

#define WM8994_FIFOS_ERR_STS_WIDTH 1 /* FIFOS_ERR_STS */

4175

#define WM8994_AIF2DRC_SIG_DET_STS 0x0800 /* AIF2DRC_SIG_DET_STS */

4176

#define WM8994_AIF2DRC_SIG_DET_STS_MASK 0x0800 /* AIF2DRC_SIG_DET_STS */

4177

#define WM8994_AIF2DRC_SIG_DET_STS_SHIFT 11 /* AIF2DRC_SIG_DET_STS */

4178

#define WM8994_AIF2DRC_SIG_DET_STS_WIDTH 1 /* AIF2DRC_SIG_DET_STS */

4179

#define WM8994_AIF1DRC2_SIG_DET_STS 0x0400 /* AIF1DRC2_SIG_DET_STS */

4180

#define WM8994_AIF1DRC2_SIG_DET_STS_MASK 0x0400 /* AIF1DRC2_SIG_DET_STS */

4181

#define WM8994_AIF1DRC2_SIG_DET_STS_SHIFT 10 /* AIF1DRC2_SIG_DET_STS */

4182

#define WM8994_AIF1DRC2_SIG_DET_STS_WIDTH 1 /* AIF1DRC2_SIG_DET_STS */

4183

#define WM8994_AIF1DRC1_SIG_DET_STS 0x0200 /* AIF1DRC1_SIG_DET_STS */

4184

#define WM8994_AIF1DRC1_SIG_DET_STS_MASK 0x0200 /* AIF1DRC1_SIG_DET_STS */

4185

#define WM8994_AIF1DRC1_SIG_DET_STS_SHIFT 9 /* AIF1DRC1_SIG_DET_STS */

4186

#define WM8994_AIF1DRC1_SIG_DET_STS_WIDTH 1 /* AIF1DRC1_SIG_DET_STS */

4187

#define WM8994_SRC2_LOCK_STS 0x0100 /* SRC2_LOCK_STS */

4188

#define WM8994_SRC2_LOCK_STS_MASK 0x0100 /* SRC2_LOCK_STS */

4189

#define WM8994_SRC2_LOCK_STS_SHIFT 8 /* SRC2_LOCK_STS */

4190

#define WM8994_SRC2_LOCK_STS_WIDTH 1 /* SRC2_LOCK_STS */

4191

#define WM8994_SRC1_LOCK_STS 0x0080 /* SRC1_LOCK_STS */

4192

#define WM8994_SRC1_LOCK_STS_MASK 0x0080 /* SRC1_LOCK_STS */

4193

#define WM8994_SRC1_LOCK_STS_SHIFT 7 /* SRC1_LOCK_STS */

4194

#define WM8994_SRC1_LOCK_STS_WIDTH 1 /* SRC1_LOCK_STS */

4195

#define WM8994_FLL2_LOCK_STS 0x0040 /* FLL2_LOCK_STS */

4196

#define WM8994_FLL2_LOCK_STS_MASK 0x0040 /* FLL2_LOCK_STS */

4197

#define WM8994_FLL2_LOCK_STS_SHIFT 6 /* FLL2_LOCK_STS */

4198

#define WM8994_FLL2_LOCK_STS_WIDTH 1 /* FLL2_LOCK_STS */

4199

#define WM8994_FLL1_LOCK_STS 0x0020 /* FLL1_LOCK_STS */

4200

#define WM8994_FLL1_LOCK_STS_MASK 0x0020 /* FLL1_LOCK_STS */

4201

#define WM8994_FLL1_LOCK_STS_SHIFT 5 /* FLL1_LOCK_STS */

4202

#define WM8994_FLL1_LOCK_STS_WIDTH 1 /* FLL1_LOCK_STS */

4203

#define WM8994_MIC2_SHRT_STS 0x0010 /* MIC2_SHRT_STS */

4204

#define WM8994_MIC2_SHRT_STS_MASK 0x0010 /* MIC2_SHRT_STS */

4205

#define WM8994_MIC2_SHRT_STS_SHIFT 4 /* MIC2_SHRT_STS */

4206

#define WM8994_MIC2_SHRT_STS_WIDTH 1 /* MIC2_SHRT_STS */

4207

#define WM8994_MIC2_DET_STS 0x0008 /* MIC2_DET_STS */

4208

#define WM8994_MIC2_DET_STS_MASK 0x0008 /* MIC2_DET_STS */

4209

#define WM8994_MIC2_DET_STS_SHIFT 3 /* MIC2_DET_STS */

4210

#define WM8994_MIC2_DET_STS_WIDTH 1 /* MIC2_DET_STS */

4211

#define WM8994_MIC1_SHRT_STS 0x0004 /* MIC1_SHRT_STS */

4212

#define WM8994_MIC1_SHRT_STS_MASK 0x0004 /* MIC1_SHRT_STS */

4213

#define WM8994_MIC1_SHRT_STS_SHIFT 2 /* MIC1_SHRT_STS */

4214

#define WM8994_MIC1_SHRT_STS_WIDTH 1 /* MIC1_SHRT_STS */

4215

#define WM8994_MIC1_DET_STS 0x0002 /* MIC1_DET_STS */

4216

#define WM8994_MIC1_DET_STS_MASK 0x0002 /* MIC1_DET_STS */

4217

#define WM8994_MIC1_DET_STS_SHIFT 1 /* MIC1_DET_STS */

4218

#define WM8994_MIC1_DET_STS_WIDTH 1 /* MIC1_DET_STS */

4219

#define WM8994_TEMP_SHUT_STS 0x0001 /* TEMP_SHUT_STS */

4220

#define WM8994_TEMP_SHUT_STS_MASK 0x0001 /* TEMP_SHUT_STS */

4221

#define WM8994_TEMP_SHUT_STS_SHIFT 0 /* TEMP_SHUT_STS */

4222

#define WM8994_TEMP_SHUT_STS_WIDTH 1 /* TEMP_SHUT_STS */

4223

4224

/*

4225

* R1848 (0x738) - Interrupt Status 1 Mask

4226

*/

4227

#define WM8994_IM_GP11_EINT 0x0400 /* IM_GP11_EINT */

4228

#define WM8994_IM_GP11_EINT_MASK 0x0400 /* IM_GP11_EINT */

4229

#define WM8994_IM_GP11_EINT_SHIFT 10 /* IM_GP11_EINT */

4230

#define WM8994_IM_GP11_EINT_WIDTH 1 /* IM_GP11_EINT */

4231

#define WM8994_IM_GP10_EINT 0x0200 /* IM_GP10_EINT */

4232

#define WM8994_IM_GP10_EINT_MASK 0x0200 /* IM_GP10_EINT */

4233

#define WM8994_IM_GP10_EINT_SHIFT 9 /* IM_GP10_EINT */

4234

#define WM8994_IM_GP10_EINT_WIDTH 1 /* IM_GP10_EINT */

4235

#define WM8994_IM_GP9_EINT 0x0100 /* IM_GP9_EINT */

4236

#define WM8994_IM_GP9_EINT_MASK 0x0100 /* IM_GP9_EINT */

4237

#define WM8994_IM_GP9_EINT_SHIFT 8 /* IM_GP9_EINT */

4238

#define WM8994_IM_GP9_EINT_WIDTH 1 /* IM_GP9_EINT */

4239

#define WM8994_IM_GP8_EINT 0x0080 /* IM_GP8_EINT */

4240

#define WM8994_IM_GP8_EINT_MASK 0x0080 /* IM_GP8_EINT */

4241

#define WM8994_IM_GP8_EINT_SHIFT 7 /* IM_GP8_EINT */

4242

#define WM8994_IM_GP8_EINT_WIDTH 1 /* IM_GP8_EINT */

4243

#define WM8994_IM_GP7_EINT 0x0040 /* IM_GP7_EINT */

4244

#define WM8994_IM_GP7_EINT_MASK 0x0040 /* IM_GP7_EINT */

4245

#define WM8994_IM_GP7_EINT_SHIFT 6 /* IM_GP7_EINT */

4246

#define WM8994_IM_GP7_EINT_WIDTH 1 /* IM_GP7_EINT */

4247

#define WM8994_IM_GP6_EINT 0x0020 /* IM_GP6_EINT */

4248

#define WM8994_IM_GP6_EINT_MASK 0x0020 /* IM_GP6_EINT */

4249

#define WM8994_IM_GP6_EINT_SHIFT 5 /* IM_GP6_EINT */

4250

#define WM8994_IM_GP6_EINT_WIDTH 1 /* IM_GP6_EINT */

4251

#define WM8994_IM_GP5_EINT 0x0010 /* IM_GP5_EINT */

4252

#define WM8994_IM_GP5_EINT_MASK 0x0010 /* IM_GP5_EINT */

4253

#define WM8994_IM_GP5_EINT_SHIFT 4 /* IM_GP5_EINT */

4254

#define WM8994_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */

4255

#define WM8994_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */

4256

#define WM8994_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */

4257

#define WM8994_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */

4258

#define WM8994_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */

4259

#define WM8994_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */

4260

#define WM8994_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */

4261

#define WM8994_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */

4262

#define WM8994_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */

4263

#define WM8994_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */

4264

#define WM8994_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */

4265

#define WM8994_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */

4266

#define WM8994_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */

4267

#define WM8994_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */

4268

#define WM8994_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */

4269

#define WM8994_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */

4270

#define WM8994_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */

4271

4272

/*

4273

* R1849 (0x739) - Interrupt Status 2 Mask

4274

*/

4275

#define WM8994_IM_TEMP_WARN_EINT 0x8000 /* IM_TEMP_WARN_EINT */

4276

#define WM8994_IM_TEMP_WARN_EINT_MASK 0x8000 /* IM_TEMP_WARN_EINT */

4277

#define WM8994_IM_TEMP_WARN_EINT_SHIFT 15 /* IM_TEMP_WARN_EINT */

4278

#define WM8994_IM_TEMP_WARN_EINT_WIDTH 1 /* IM_TEMP_WARN_EINT */

4279

#define WM8994_IM_DCS_DONE_EINT 0x4000 /* IM_DCS_DONE_EINT */

4280

#define WM8994_IM_DCS_DONE_EINT_MASK 0x4000 /* IM_DCS_DONE_EINT */

4281

#define WM8994_IM_DCS_DONE_EINT_SHIFT 14 /* IM_DCS_DONE_EINT */

4282

#define WM8994_IM_DCS_DONE_EINT_WIDTH 1 /* IM_DCS_DONE_EINT */

4283

#define WM8994_IM_WSEQ_DONE_EINT 0x2000 /* IM_WSEQ_DONE_EINT */

4284

#define WM8994_IM_WSEQ_DONE_EINT_MASK 0x2000 /* IM_WSEQ_DONE_EINT */

4285

#define WM8994_IM_WSEQ_DONE_EINT_SHIFT 13 /* IM_WSEQ_DONE_EINT */

4286

#define WM8994_IM_WSEQ_DONE_EINT_WIDTH 1 /* IM_WSEQ_DONE_EINT */

4287

#define WM8994_IM_FIFOS_ERR_EINT 0x1000 /* IM_FIFOS_ERR_EINT */

4288

#define WM8994_IM_FIFOS_ERR_EINT_MASK 0x1000 /* IM_FIFOS_ERR_EINT */

4289

#define WM8994_IM_FIFOS_ERR_EINT_SHIFT 12 /* IM_FIFOS_ERR_EINT */

4290

#define WM8994_IM_FIFOS_ERR_EINT_WIDTH 1 /* IM_FIFOS_ERR_EINT */

4291

#define WM8994_IM_AIF2DRC_SIG_DET_EINT 0x0800 /* IM_AIF2DRC_SIG_DET_EINT */

4292

#define WM8994_IM_AIF2DRC_SIG_DET_EINT_MASK 0x0800 /* IM_AIF2DRC_SIG_DET_EINT */

4293

#define WM8994_IM_AIF2DRC_SIG_DET_EINT_SHIFT 11 /* IM_AIF2DRC_SIG_DET_EINT */

4294

#define WM8994_IM_AIF2DRC_SIG_DET_EINT_WIDTH 1 /* IM_AIF2DRC_SIG_DET_EINT */

4295

#define WM8994_IM_AIF1DRC2_SIG_DET_EINT 0x0400 /* IM_AIF1DRC2_SIG_DET_EINT */

4296

#define WM8994_IM_AIF1DRC2_SIG_DET_EINT_MASK 0x0400 /* IM_AIF1DRC2_SIG_DET_EINT */

4297

#define WM8994_IM_AIF1DRC2_SIG_DET_EINT_SHIFT 10 /* IM_AIF1DRC2_SIG_DET_EINT */

4298

#define WM8994_IM_AIF1DRC2_SIG_DET_EINT_WIDTH 1 /* IM_AIF1DRC2_SIG_DET_EINT */

4299

#define WM8994_IM_AIF1DRC1_SIG_DET_EINT 0x0200 /* IM_AIF1DRC1_SIG_DET_EINT */

4300

#define WM8994_IM_AIF1DRC1_SIG_DET_EINT_MASK 0x0200 /* IM_AIF1DRC1_SIG_DET_EINT */

4301

#define WM8994_IM_AIF1DRC1_SIG_DET_EINT_SHIFT 9 /* IM_AIF1DRC1_SIG_DET_EINT */

4302

#define WM8994_IM_AIF1DRC1_SIG_DET_EINT_WIDTH 1 /* IM_AIF1DRC1_SIG_DET_EINT */

4303

#define WM8994_IM_SRC2_LOCK_EINT 0x0100 /* IM_SRC2_LOCK_EINT */

4304

#define WM8994_IM_SRC2_LOCK_EINT_MASK 0x0100 /* IM_SRC2_LOCK_EINT */

4305

#define WM8994_IM_SRC2_LOCK_EINT_SHIFT 8 /* IM_SRC2_LOCK_EINT */

4306

#define WM8994_IM_SRC2_LOCK_EINT_WIDTH 1 /* IM_SRC2_LOCK_EINT */

4307

#define WM8994_IM_SRC1_LOCK_EINT 0x0080 /* IM_SRC1_LOCK_EINT */

4308

#define WM8994_IM_SRC1_LOCK_EINT_MASK 0x0080 /* IM_SRC1_LOCK_EINT */

4309

#define WM8994_IM_SRC1_LOCK_EINT_SHIFT 7 /* IM_SRC1_LOCK_EINT */

4310

#define WM8994_IM_SRC1_LOCK_EINT_WIDTH 1 /* IM_SRC1_LOCK_EINT */

4311

#define WM8994_IM_FLL2_LOCK_EINT 0x0040 /* IM_FLL2_LOCK_EINT */

4312

#define WM8994_IM_FLL2_LOCK_EINT_MASK 0x0040 /* IM_FLL2_LOCK_EINT */

4313

#define WM8994_IM_FLL2_LOCK_EINT_SHIFT 6 /* IM_FLL2_LOCK_EINT */

4314

#define WM8994_IM_FLL2_LOCK_EINT_WIDTH 1 /* IM_FLL2_LOCK_EINT */

4315

#define WM8994_IM_FLL1_LOCK_EINT 0x0020 /* IM_FLL1_LOCK_EINT */

4316

#define WM8994_IM_FLL1_LOCK_EINT_MASK 0x0020 /* IM_FLL1_LOCK_EINT */

4317

#define WM8994_IM_FLL1_LOCK_EINT_SHIFT 5 /* IM_FLL1_LOCK_EINT */

4318

#define WM8994_IM_FLL1_LOCK_EINT_WIDTH 1 /* IM_FLL1_LOCK_EINT */

4319

#define WM8994_IM_MIC2_SHRT_EINT 0x0010 /* IM_MIC2_SHRT_EINT */

4320

#define WM8994_IM_MIC2_SHRT_EINT_MASK 0x0010 /* IM_MIC2_SHRT_EINT */

4321

#define WM8994_IM_MIC2_SHRT_EINT_SHIFT 4 /* IM_MIC2_SHRT_EINT */

4322

#define WM8994_IM_MIC2_SHRT_EINT_WIDTH 1 /* IM_MIC2_SHRT_EINT */

4323

#define WM8994_IM_MIC2_DET_EINT 0x0008 /* IM_MIC2_DET_EINT */

4324

#define WM8994_IM_MIC2_DET_EINT_MASK 0x0008 /* IM_MIC2_DET_EINT */

4325

#define WM8994_IM_MIC2_DET_EINT_SHIFT 3 /* IM_MIC2_DET_EINT */

4326

#define WM8994_IM_MIC2_DET_EINT_WIDTH 1 /* IM_MIC2_DET_EINT */

4327

#define WM8994_IM_MIC1_SHRT_EINT 0x0004 /* IM_MIC1_SHRT_EINT */

4328

#define WM8994_IM_MIC1_SHRT_EINT_MASK 0x0004 /* IM_MIC1_SHRT_EINT */

4329

#define WM8994_IM_MIC1_SHRT_EINT_SHIFT 2 /* IM_MIC1_SHRT_EINT */

4330

#define WM8994_IM_MIC1_SHRT_EINT_WIDTH 1 /* IM_MIC1_SHRT_EINT */

4331

#define WM8994_IM_MIC1_DET_EINT 0x0002 /* IM_MIC1_DET_EINT */

4332

#define WM8994_IM_MIC1_DET_EINT_MASK 0x0002 /* IM_MIC1_DET_EINT */

4333

#define WM8994_IM_MIC1_DET_EINT_SHIFT 1 /* IM_MIC1_DET_EINT */

4334

#define WM8994_IM_MIC1_DET_EINT_WIDTH 1 /* IM_MIC1_DET_EINT */

4335

#define WM8994_IM_TEMP_SHUT_EINT 0x0001 /* IM_TEMP_SHUT_EINT */

4336

#define WM8994_IM_TEMP_SHUT_EINT_MASK 0x0001 /* IM_TEMP_SHUT_EINT */

4337

#define WM8994_IM_TEMP_SHUT_EINT_SHIFT 0 /* IM_TEMP_SHUT_EINT */

4338

#define WM8994_IM_TEMP_SHUT_EINT_WIDTH 1 /* IM_TEMP_SHUT_EINT */

4339

4340

/*

4341

* R1856 (0x740) - Interrupt Control

4342

*/

4343

#define WM8994_IM_IRQ 0x0001 /* IM_IRQ */

4344

#define WM8994_IM_IRQ_MASK 0x0001 /* IM_IRQ */

4345

#define WM8994_IM_IRQ_SHIFT 0 /* IM_IRQ */

4346

#define WM8994_IM_IRQ_WIDTH 1 /* IM_IRQ */

4347

4348

/*

4349

* R1864 (0x748) - IRQ Debounce

4350

*/

4351

#define WM8994_TEMP_WARN_DB 0x0020 /* TEMP_WARN_DB */

4352

#define WM8994_TEMP_WARN_DB_MASK 0x0020 /* TEMP_WARN_DB */

4353

#define WM8994_TEMP_WARN_DB_SHIFT 5 /* TEMP_WARN_DB */

4354

#define WM8994_TEMP_WARN_DB_WIDTH 1 /* TEMP_WARN_DB */

4355

#define WM8994_MIC2_SHRT_DB 0x0010 /* MIC2_SHRT_DB */

4356

#define WM8994_MIC2_SHRT_DB_MASK 0x0010 /* MIC2_SHRT_DB */

4357

#define WM8994_MIC2_SHRT_DB_SHIFT 4 /* MIC2_SHRT_DB */

4358

#define WM8994_MIC2_SHRT_DB_WIDTH 1 /* MIC2_SHRT_DB */

4359

#define WM8994_MIC2_DET_DB 0x0008 /* MIC2_DET_DB */

4360

#define WM8994_MIC2_DET_DB_MASK 0x0008 /* MIC2_DET_DB */

4361

#define WM8994_MIC2_DET_DB_SHIFT 3 /* MIC2_DET_DB */

4362

#define WM8994_MIC2_DET_DB_WIDTH 1 /* MIC2_DET_DB */

4363

#define WM8994_MIC1_SHRT_DB 0x0004 /* MIC1_SHRT_DB */

4364

#define WM8994_MIC1_SHRT_DB_MASK 0x0004 /* MIC1_SHRT_DB */

4365

#define WM8994_MIC1_SHRT_DB_SHIFT 2 /* MIC1_SHRT_DB */

4366

#define WM8994_MIC1_SHRT_DB_WIDTH 1 /* MIC1_SHRT_DB */

4367

#define WM8994_MIC1_DET_DB 0x0002 /* MIC1_DET_DB */

4368

#define WM8994_MIC1_DET_DB_MASK 0x0002 /* MIC1_DET_DB */

4369

#define WM8994_MIC1_DET_DB_SHIFT 1 /* MIC1_DET_DB */

4370

#define WM8994_MIC1_DET_DB_WIDTH 1 /* MIC1_DET_DB */

4371

#define WM8994_TEMP_SHUT_DB 0x0001 /* TEMP_SHUT_DB */

4372

#define WM8994_TEMP_SHUT_DB_MASK 0x0001 /* TEMP_SHUT_DB */

4373

#define WM8994_TEMP_SHUT_DB_SHIFT 0 /* TEMP_SHUT_DB */

4374

#define WM8994_TEMP_SHUT_DB_WIDTH 1 /* TEMP_SHUT_DB */

4375

Mark Brown

d6addcc

2010-11-26 15:21:08 +0000

[diff] [blame^]

4376

/*

4377

* R2304 (0x900) - DSP2_Program

4378

*/

4379

#define WM8958_DSP2_ENA 0x0001 /* DSP2_ENA */

4380

#define WM8958_DSP2_ENA_MASK 0x0001 /* DSP2_ENA */

4381

#define WM8958_DSP2_ENA_SHIFT 0 /* DSP2_ENA */

4382

#define WM8958_DSP2_ENA_WIDTH 1 /* DSP2_ENA */

4383

4384

/*

4385

* R2305 (0x901) - DSP2_Config

4386

*/

4387

#define WM8958_MBC_SEL_MASK 0x0030 /* MBC_SEL - [5:4] */

4388

#define WM8958_MBC_SEL_SHIFT 4 /* MBC_SEL - [5:4] */

4389

#define WM8958_MBC_SEL_WIDTH 2 /* MBC_SEL - [5:4] */

4390

#define WM8958_MBC_ENA 0x0001 /* MBC_ENA */

4391

#define WM8958_MBC_ENA_MASK 0x0001 /* MBC_ENA */

4392

#define WM8958_MBC_ENA_SHIFT 0 /* MBC_ENA */

4393

#define WM8958_MBC_ENA_WIDTH 1 /* MBC_ENA */

4394

4395

/*

4396

* R2560 (0xA00) - DSP2_MagicNum

4397

*/

4398

#define WM8958_DSP2_MAGIC_NUM_MASK 0xFFFF /* DSP2_MAGIC_NUM - [15:0] */

4399

#define WM8958_DSP2_MAGIC_NUM_SHIFT 0 /* DSP2_MAGIC_NUM - [15:0] */

4400

#define WM8958_DSP2_MAGIC_NUM_WIDTH 16 /* DSP2_MAGIC_NUM - [15:0] */

4401

4402

/*

4403

* R2561 (0xA01) - DSP2_ReleaseYear

4404

*/

4405

#define WM8958_DSP2_RELEASE_YEAR_MASK 0xFFFF /* DSP2_RELEASE_YEAR - [15:0] */

4406

#define WM8958_DSP2_RELEASE_YEAR_SHIFT 0 /* DSP2_RELEASE_YEAR - [15:0] */

4407

#define WM8958_DSP2_RELEASE_YEAR_WIDTH 16 /* DSP2_RELEASE_YEAR - [15:0] */

4408

4409

/*

4410

* R2562 (0xA02) - DSP2_ReleaseMonthDay

4411

*/

4412

#define WM8958_DSP2_RELEASE_MONTH_MASK 0xFF00 /* DSP2_RELEASE_MONTH - [15:8] */

4413

#define WM8958_DSP2_RELEASE_MONTH_SHIFT 8 /* DSP2_RELEASE_MONTH - [15:8] */

4414

#define WM8958_DSP2_RELEASE_MONTH_WIDTH 8 /* DSP2_RELEASE_MONTH - [15:8] */

4415

#define WM8958_DSP2_RELEASE_DAY_MASK 0x00FF /* DSP2_RELEASE_DAY - [7:0] */

4416

#define WM8958_DSP2_RELEASE_DAY_SHIFT 0 /* DSP2_RELEASE_DAY - [7:0] */

4417

#define WM8958_DSP2_RELEASE_DAY_WIDTH 8 /* DSP2_RELEASE_DAY - [7:0] */

4418

4419

/*

4420

* R2563 (0xA03) - DSP2_ReleaseTime

4421

*/

4422

#define WM8958_DSP2_RELEASE_HOURS_MASK 0xFF00 /* DSP2_RELEASE_HOURS - [15:8] */

4423

#define WM8958_DSP2_RELEASE_HOURS_SHIFT 8 /* DSP2_RELEASE_HOURS - [15:8] */

4424

#define WM8958_DSP2_RELEASE_HOURS_WIDTH 8 /* DSP2_RELEASE_HOURS - [15:8] */

4425

#define WM8958_DSP2_RELEASE_MINS_MASK 0x00FF /* DSP2_RELEASE_MINS - [7:0] */

4426

#define WM8958_DSP2_RELEASE_MINS_SHIFT 0 /* DSP2_RELEASE_MINS - [7:0] */

4427

#define WM8958_DSP2_RELEASE_MINS_WIDTH 8 /* DSP2_RELEASE_MINS - [7:0] */

4428

4429

/*

4430

* R2564 (0xA04) - DSP2_VerMajMin

4431

*/

4432

#define WM8958_DSP2_MAJOR_VER_MASK 0xFF00 /* DSP2_MAJOR_VER - [15:8] */

4433

#define WM8958_DSP2_MAJOR_VER_SHIFT 8 /* DSP2_MAJOR_VER - [15:8] */

4434

#define WM8958_DSP2_MAJOR_VER_WIDTH 8 /* DSP2_MAJOR_VER - [15:8] */

4435

#define WM8958_DSP2_MINOR_VER_MASK 0x00FF /* DSP2_MINOR_VER - [7:0] */

4436

#define WM8958_DSP2_MINOR_VER_SHIFT 0 /* DSP2_MINOR_VER - [7:0] */

4437

#define WM8958_DSP2_MINOR_VER_WIDTH 8 /* DSP2_MINOR_VER - [7:0] */

4438

4439

/*

4440

* R2565 (0xA05) - DSP2_VerBuild

4441

*/

4442

#define WM8958_DSP2_BUILD_VER_MASK 0xFFFF /* DSP2_BUILD_VER - [15:0] */

4443

#define WM8958_DSP2_BUILD_VER_SHIFT 0 /* DSP2_BUILD_VER - [15:0] */

4444

#define WM8958_DSP2_BUILD_VER_WIDTH 16 /* DSP2_BUILD_VER - [15:0] */

4445

4446

/*

4447

* R2573 (0xA0D) - DSP2_ExecControl

4448

*/

4449

#define WM8958_DSP2_STOPC 0x0020 /* DSP2_STOPC */

4450

#define WM8958_DSP2_STOPC_MASK 0x0020 /* DSP2_STOPC */

4451

#define WM8958_DSP2_STOPC_SHIFT 5 /* DSP2_STOPC */

4452

#define WM8958_DSP2_STOPC_WIDTH 1 /* DSP2_STOPC */

4453

#define WM8958_DSP2_STOPS 0x0010 /* DSP2_STOPS */

4454

#define WM8958_DSP2_STOPS_MASK 0x0010 /* DSP2_STOPS */

4455

#define WM8958_DSP2_STOPS_SHIFT 4 /* DSP2_STOPS */

4456

#define WM8958_DSP2_STOPS_WIDTH 1 /* DSP2_STOPS */

4457

#define WM8958_DSP2_STOPI 0x0008 /* DSP2_STOPI */

4458

#define WM8958_DSP2_STOPI_MASK 0x0008 /* DSP2_STOPI */

4459

#define WM8958_DSP2_STOPI_SHIFT 3 /* DSP2_STOPI */

4460

#define WM8958_DSP2_STOPI_WIDTH 1 /* DSP2_STOPI */

4461

#define WM8958_DSP2_STOP 0x0004 /* DSP2_STOP */

4462

#define WM8958_DSP2_STOP_MASK 0x0004 /* DSP2_STOP */

4463

#define WM8958_DSP2_STOP_SHIFT 2 /* DSP2_STOP */

4464

#define WM8958_DSP2_STOP_WIDTH 1 /* DSP2_STOP */

4465

#define WM8958_DSP2_RUNR 0x0002 /* DSP2_RUNR */

4466

#define WM8958_DSP2_RUNR_MASK 0x0002 /* DSP2_RUNR */

4467

#define WM8958_DSP2_RUNR_SHIFT 1 /* DSP2_RUNR */

4468

#define WM8958_DSP2_RUNR_WIDTH 1 /* DSP2_RUNR */

4469

#define WM8958_DSP2_RUN 0x0001 /* DSP2_RUN */

4470

#define WM8958_DSP2_RUN_MASK 0x0001 /* DSP2_RUN */

4471

#define WM8958_DSP2_RUN_SHIFT 0 /* DSP2_RUN */

4472

#define WM8958_DSP2_RUN_WIDTH 1 /* DSP2_RUN */

4473

Mark Brown

1c4d3b70

2010-01-29 18:20:28 +0000

[diff] [blame]

4474

#endif