| Rajendra Nayak | d79b126 | 2009-12-09 00:01:44 +0530 | [diff] [blame^] | 1 | /* | 
|  | 2 | * OMAP4-specific clock framework functions | 
|  | 3 | * | 
|  | 4 | * Copyright (C) 2009 Texas Instruments, Inc. | 
|  | 5 | * | 
|  | 6 | * Rajendra Nayak (rnayak@ti.com) | 
|  | 7 | * | 
|  | 8 | * This program is free software; you can redistribute it and/or modify | 
|  | 9 | * it under the terms of the GNU General Public License version 2 as | 
|  | 10 | * published by the Free Software Foundation. | 
|  | 11 | */ | 
|  | 12 |  | 
|  | 13 | #include <linux/errno.h> | 
|  | 14 | #include "clock.h" | 
|  | 15 |  | 
|  | 16 | struct clk_functions omap2_clk_functions = { | 
|  | 17 | .clk_enable		= omap2_clk_enable, | 
|  | 18 | .clk_disable		= omap2_clk_disable, | 
|  | 19 | .clk_round_rate		= omap2_clk_round_rate, | 
|  | 20 | .clk_set_rate		= omap2_clk_set_rate, | 
|  | 21 | .clk_set_parent		= omap2_clk_set_parent, | 
|  | 22 | .clk_disable_unused	= omap2_clk_disable_unused, | 
|  | 23 | }; | 
|  | 24 |  | 
|  | 25 | /* | 
|  | 26 | * Dummy functions for DPLL control. Plan is to re-use | 
|  | 27 | * existing OMAP3 dpll control functions. | 
|  | 28 | */ | 
|  | 29 |  | 
|  | 30 | unsigned long omap3_dpll_recalc(struct clk *clk) | 
|  | 31 | { | 
|  | 32 | return 0; | 
|  | 33 | } | 
|  | 34 |  | 
|  | 35 | int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) | 
|  | 36 | { | 
|  | 37 | return 0; | 
|  | 38 | } | 
|  | 39 |  | 
|  | 40 | int omap3_noncore_dpll_enable(struct clk *clk) | 
|  | 41 | { | 
|  | 42 | return 0; | 
|  | 43 | } | 
|  | 44 |  | 
|  | 45 | void omap3_noncore_dpll_disable(struct clk *clk) | 
|  | 46 | { | 
|  | 47 | return; | 
|  | 48 | } | 
|  | 49 |  | 
|  | 50 | const struct clkops clkops_noncore_dpll_ops = { | 
|  | 51 | .enable		= &omap3_noncore_dpll_enable, | 
|  | 52 | .disable	= &omap3_noncore_dpll_disable, | 
|  | 53 | }; | 
|  | 54 |  | 
|  | 55 | void omap2_clk_prepare_for_reboot(void) | 
|  | 56 | { | 
|  | 57 | return; | 
|  | 58 | } |