)]}' { "log": [ { "commit": "3072c379bccfa2844e33103ed9ff530780e660ea", "tree": "9fb6f4e42371a4e5b99ac143b6127d2dd95a9d9d", "parents": [ "034d8e8f273fcb02bebd6a62d8023ffa409fe92f" ], "author": { "name": "peerchen", "email": "peerchen@gmail.com", "time": "Mon May 19 14:44:57 2008 +0800" }, "committer": { "name": "Jeff Garzik", "email": "jgarzik@redhat.com", "time": "Fri May 30 12:40:28 2008 -0400" }, "message": "ahci: change the Device IDs of nvidia MCP7B AHCI controller in ahci.c\n\nChange the partial Device IDs of nvidia MCP7B AHCI controller in ahci.c,\nas the actual PCI IDs deployed in the field differed from the forecasted ones\npreemptively placed in the driver.\n\nSigned-off-by: Peer Chen \u003cpeerchen@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjgarzik@redhat.com\u003e\n" }, { "commit": "78ab88f04f44bed566d51dce0c7cbfeff6449a06", "tree": "f60d9ebf37fca7af191cc16665c9025bc5cf56f4", "parents": [ "a15306365a16380f3bafee9e181ba01231d4acd7" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Thu May 01 23:41:41 2008 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jgarzik@redhat.com", "time": "Tue May 06 11:32:02 2008 -0400" }, "message": "libata: improve post-reset device ready test\n\nSome controllers (jmb and inic162x) use 0x77 and 0x7f to indicate that\nthe device isn\u0027t ready yet. It looks like they use 0xff if device\npresence is detected but connection isn\u0027t established. 0x77 or 0x7f\nafter connection is established and use the value from signature FIS\nafter receiving it.\n\nThis patch implements ata_check_ready(), which takes TF status value\nand determines whether the port is ready or not considering the above\nand other conditions, and use it in @check_ready() functions. This is\nsafe as both 0x77 and 0x7f aren\u0027t valid ready status value even though\nthey have BSY bit cleared.\n\nThis fixes hot plug detection failures which can be triggered with\ncertain drives if they aren\u0027t already spun up when the data connector\nis hot plugged.\n\nTested on sil, sil24, ahci (jmb/ich), piix and inic162x combined with\neight drives from all major vendors.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjgarzik@redhat.com\u003e\n" }, { "commit": "22b5e7a74280deae560c20ee1a9b502b35181327", "tree": "8386b019edec04d92ebb89c66628b0ec69800930", "parents": [ "a79067e513c71733223e13a52aacc8dbd71e9f46" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Tue Apr 29 16:09:22 2008 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jgarzik@redhat.com", "time": "Tue Apr 29 17:42:04 2008 -0400" }, "message": "ahci: SB600 ahci can\u0027t do MSI, blacklist that capability\n\nThis fixes bz#10507.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nCc: Shane Huang \u003cShane.Huang@amd.com\u003e\nSigned-off-by: Jeff Garzik \u003cjgarzik@redhat.com\u003e\n" }, { "commit": "15fe982e429e0e6b7466719acb6cfd9dbfe47f0c", "tree": "de5ac9b692257050bf8dbdb6ebe02e780fddad46", "parents": [ "411cb3869afd91ed40e8f12df64cd9e315356305" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Wed Apr 23 20:52:58 2008 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jgarzik@redhat.com", "time": "Fri Apr 25 00:45:13 2008 -0400" }, "message": "ahci: retry enabling AHCI a few times before spitting out WARN_ON()\n\nSome chips need AHCI_EN set more than once to actually set it. Try a\nfew times before giving up and spitting out WARN_ON().\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nCc: Peer Chen \u003cpchen@nvidia.com\u003e\nCc: Volker Armin Hemmann \u003cvolker.armin.hemmann@tu-clausthal.de\u003e\nSigned-off-by: Jeff Garzik \u003cjgarzik@redhat.com\u003e\n" }, { "commit": "ee959b00c335d7780136c5abda37809191fe52c3", "tree": "7775f3b274fd8caf5e7e5154fea89e96f2babd94", "parents": [ "56d110e852b0b1c85ad6c9bfe1cb4473ceb16402" ], "author": { "name": "Tony Jones", "email": "tonyj@suse.de", "time": "Fri Feb 22 00:13:36 2008 +0100" }, "committer": { "name": "Greg Kroah-Hartman", "email": "gregkh@suse.de", "time": "Sat Apr 19 19:10:33 2008 -0700" }, "message": "SCSI: convert struct class_device to struct device\n\nIt\u0027s big, but there doesn\u0027t seem to be a way to split it up smaller...\n\nSigned-off-by: Tony Jones \u003ctonyj@suse.de\u003e\nSigned-off-by: Kay Sievers \u003ckay.sievers@vrfy.org\u003e\nCc: Roland Dreier \u003crolandd@cisco.com\u003e\nCc: Sean Hefty \u003csean.hefty@intel.com\u003e\nCc: Hal Rosenstock \u003chal.rosenstock@gmail.com\u003e\nCc: James Bottomley \u003cJames.Bottomley@HansenPartnership.com\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n\n" }, { "commit": "45db2f6c95eee7c6622ea1b3edb9abafba58e3ab", "tree": "1c57efcf3e118b177dd7c9c1070b8af70694aff3", "parents": [ "2a0c15ca39f5881aa1b472ca856bb7a2e584ece7" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Tue Apr 08 01:46:56 2008 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jgarzik@redhat.com", "time": "Thu Apr 17 15:44:25 2008 -0400" }, "message": "libata: move link onlineness check out of softreset methods\n\nCurrently, SATA softresets should do link onlineness check before\nactually performing SRST protocol but it doesn\u0027t really belong to\nsoftreset.\n\nThis patch moves onlineness check in softreset to ata_eh_reset() and\nata_eh_followup_srst_needed() to clean up code and help future sata_mv\nchanges which need clear separation between SCR and TF accesses.\n\nsata_fsl is peculiar in that its softreset really isn\u0027t softreset but\ncombination of hardreset and softreset. This patch adds dummy private\n-\u003eprereset to keep the current behavior but the driver really should\nimplement separate hard and soft resets and return -EAGAIN from\nhardreset if it should be follwed by softreset.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjgarzik@redhat.com\u003e\n" }, { "commit": "071f44b1d2c051641b62a3571223314737ccbe59", "tree": "a07794c8109e5d82a78223ae0159eadbf862c463", "parents": [ "48515f6c006c2a9d7b624ee8ad068018c2d3fe0e" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Apr 07 22:47:22 2008 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jgarzik@redhat.com", "time": "Thu Apr 17 15:44:25 2008 -0400" }, "message": "libata: implement PMP helpers\n\nImplement helpers to test whether PMP is supported, attached and\ndetermine pmp number to use when issuing SRST to a link. While at it,\nmove ata_is_host_link() so that it\u0027s together with the two new PMP\nhelpers.\n\nThis change simplifies LLDs and helps making PMP support optional.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\n" }, { "commit": "350756f6dab6d37ef9ed3f18dec520e88969ddac", "tree": "825bb133cf0059e21949d31dda127fd13847339e", "parents": [ "182d7bbac322d6921ce81f8e6aa23d250816381d" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Apr 07 22:47:21 2008 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jgarzik@redhat.com", "time": "Thu Apr 17 15:44:24 2008 -0400" }, "message": "libata: don\u0027t use ap-\u003eioaddr in non-SFF drivers\n\nap-\u003eioaddr is to carry addresses for TF and BMDMA registers of a SFF\ncontroller, don\u0027t abuse it in non-SFF controllers.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\n" }, { "commit": "520d06f92b32d7abe5127d7cc46a819db0f384e6", "tree": "fd4f9ce7fdfa4296a1e71457906500736ca27fa0", "parents": [ "4c9bf4e799ce06a7378f1196587084802a414c03" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Apr 07 22:47:21 2008 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jgarzik@redhat.com", "time": "Thu Apr 17 15:44:24 2008 -0400" }, "message": "libata: remove check_status from non-SFF drivers\n\nNow that all SFF stuff is separated out of core layer, core layer\ndoesn\u0027t call ops-\u003e[alt_]check_status(). In fact, no one calls them\nfor non-SFF drivers anymore. Kill them.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\n" }, { "commit": "4c9bf4e799ce06a7378f1196587084802a414c03", "tree": "70a7d3741e756b975468850537f222349143a0be", "parents": [ "79f97dadfe9b4b561634d202225ba2fa910dc225" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Apr 07 22:47:20 2008 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jgarzik@redhat.com", "time": "Thu Apr 17 15:44:23 2008 -0400" }, "message": "libata: replace tf_read with qc_fill_rtf for non-SFF drivers\n\nNow that all SFF stuff is separated out of core layer, core layer\ndoesn\u0027t call ops-\u003etf_read directly. It gets called only via\nops-\u003eqc_fill_rtf() for non-SFF drivers. This patch directly\nimplements private ops-\u003eqc_fill_rtf() for non-SFF controllers and kill\nops-\u003etf_read().\n\nThis is much cleaner for non-SFF controllers as some of them have to\ncache SFF register values in private data structure and report the\ncached values via ops-\u003etf_read(). Also, ops-\u003etf_read() gets nasty for\ncontrollers which don\u0027t have clear notion of TF registers when\noperation is not in progress.\n\nAs this change makes default ops-\u003eqc_fill_rtf unnecessary, move\nata_sff_qc_fill_rtf() form ata_base_port_ops to ata_sff_port_ops where\nit belongs.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\n" }, { "commit": "79f97dadfe9b4b561634d202225ba2fa910dc225", "tree": "7bea39a135c7c87b7430d6c071288a05990b9309", "parents": [ "22183bf569c8600ff414ac25f23134044e0ef453" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Apr 07 22:47:20 2008 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jgarzik@redhat.com", "time": "Thu Apr 17 15:44:23 2008 -0400" }, "message": "libata: drop @finish_qc from ata_qc_complete_multiple()\n\nata_qc_complete_multiple() took @finish_qc and called it on every qc\nbefore completing it. This was to give opportunity to update TF cache\nbefore ata_qc_complete() tries to fill result_tf. Now that result TF\nis a separate operation, this is no longer necessary.\n\nUpdate sata_sil24, which was the only user of this mechanism, such\nthat it implements its own ops-\u003eqc_fill_rtf() and drop @finish_qc from\nata_qc_complete_multiple().\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\n" }, { "commit": "305d2a1ab137d11d573319c315748a87060fe82d", "tree": "8dcf81b1742db21c6a745688de96a18944c83617", "parents": [ "5958e3025fd9d97429163e074d9cfa3848f51f28" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Apr 07 22:47:20 2008 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jgarzik@redhat.com", "time": "Thu Apr 17 15:44:23 2008 -0400" }, "message": "libata: unify mechanism to request follow-up SRST\n\nPreviously, there were two ways to trigger follow-up SRST from\nhardreset method - returning -EAGAIN and leaving all device classes\nunmodified. Drivers never used the latter mechanism and the only use\ncase for the former was when hardreset couldn\u0027t classify.\n\nDrop the latter mechanism and let -EAGAIN mean \"perform follow-up SRST\nif classification is required\". This change removes unnecessary\nfollow-up SRSTs and simplifies reset implementations.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\n" }, { "commit": "ac371987a81c61c2efbd6931245cdcaf43baad89", "tree": "f88970931b26d2ad344d7d67ddabc64d9b48181d", "parents": [ "57c9efdfb3cee5d4564fcb5f70555e2edb1bc52a" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Apr 07 22:47:19 2008 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jgarzik@redhat.com", "time": "Thu Apr 17 15:44:23 2008 -0400" }, "message": "libata: clear SError after link resume\n\nSError used to be cleared in -\u003epostreset. This has small hotplug race\ncondition. If a device is plugged in after reset is complete but\npostreset hasn\u0027t run yet, its hotplug event gets lost when SError is\ncleared. This patch makes sata_link_resume() clear SError. This\nkills the race condition and makes a lot of sense as some PMP and host\nPHYs don\u0027t work properly without SError cleared.\n\nThis change makes sata_pmp_std_{pre|post}_reset()\u0027s unnecessary as\nthey become identical to ata_std counterparts. It also simplifies\nsata_pmp_hardreset() and ahci_vt8251_hardreset().\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\n" }, { "commit": "9dadd45b24145d6aee2fabb28d7aef972301892b", "tree": "c97c323e2edd400bc94eaceddf20f84e9a6da005", "parents": [ "a89611e8489ac24f371c9fd6fef6605b170b16ba" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Apr 07 22:47:19 2008 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jgarzik@redhat.com", "time": "Thu Apr 17 15:44:22 2008 -0400" }, "message": "libata: move generic hardreset code from sata_sff_hardreset() to sata_link_hardreset()\n\nsata_sff_hardreset() contains link readiness wait logic which isn\u0027t\nSFF specific. Move that part into sata_link_hardreset(), which now\ntakes two more parameters - @online and @check_ready. Both are\noptional. The former is out parameter for link onlineness after\nreset. The latter is used to wait for link readiness after hardreset.\n\nUsers of sata_link_hardreset() is updated to use new funtionality and\nahci_hardreset() is updated to use sata_link_hardreset() instead of\nsata_sff_hardreset(). This doesn\u0027t really cause any behavior change.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\n" }, { "commit": "a89611e8489ac24f371c9fd6fef6605b170b16ba", "tree": "ffde56421ee093e92e8c0673eeaca7ecd6b4093a", "parents": [ "aa2731ad9ad80ac3fca48bd1c4cf0eceede4810e" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Apr 07 22:47:19 2008 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jgarzik@redhat.com", "time": "Thu Apr 17 15:44:22 2008 -0400" }, "message": "ahci: use ata_wait_after_reset() instead of ata_sff_wait_ready()\n\nImplement ahci_check_ready() and replace ata_sff_wait_after_reset()\nwith ata_wait_after_reset(). As ahci was faking TF access, this\nchange doesn\u0027t result in any functional difference.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\n" }, { "commit": "705e76beb90b97421e1f61e857c4246799781bb5", "tree": "e571ad9229d469cd73d1388c76823922400823d5", "parents": [ "203c75b8245c5386044721d9c5eda5c6b71b3d14" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Apr 07 22:47:19 2008 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jgarzik@redhat.com", "time": "Thu Apr 17 15:44:22 2008 -0400" }, "message": "libata: restructure SFF post-reset readiness waits\n\nPreviously, post-softreset readiness is waited as follows.\n\n1. ata_sff_wait_after_reset() waits for 150ms and then for\n ATA_TMOUT_FF_WAIT if status is 0xff and other conditions meet.\n\n2. ata_bus_softreset() finishes with -ENODEV if status is still 0xff.\n If not, continue to #3.\n\n3. ata_bus_post_reset() waits readiness of dev0 and/or dev1 depending\n on devmask using ata_sff_wait_ready().\n\nAnd for post-hardreset readiness,\n\n1. ata_sff_wait_after_reset() waits for 150ms and then for\n ATA_TMOUT_FF_WAIT if status is 0xff and other conditions meet.\n\n2. sata_sff_hardreset waits for device readiness using\n ata_sff_wait_ready().\n\nThis patch merges and unifies post-reset readiness waits into\nata_sff_wait_ready() and ata_sff_wait_after_reset().\n\nATA_TMOUT_FF_WAIT handling is merged into ata_sff_wait_ready(). If TF\nstatus is 0xff, link status is unknown and the port is SATA, it will\ncontinue polling till ATA_TMOUT_FF_WAIT.\n\nata_sff_wait_after_reset() is updated to perform the following steps.\n\n1. waits for 150ms.\n\n2. waits for dev0 readiness using ata_sff_wait_ready(). Note that\n this is done regardless of devmask, as ata_sff_wait_ready() handles\n 0xff status correctly, this preserves the original behavior except\n that it may wait longer after softreset if link is online but\n status is 0xff. This behavior change is very unlikely to cause any\n actual difference and is intended. It brings softreset behavior to\n that of hardreset.\n\n3. waits for dev1 readiness just the same way ata_bus_post_reset() did.\n\nNow both soft and hard resets call ata_sff_wait_after_reset() after\nreset to wait for readiness after resets. As\nata_sff_wait_after_reset() contains calls to -\u003esff_dev_select(),\nexplicit call near the end of sata_sff_hardreset() is removed.\n\nThis change makes reset implementation simpler and more consistent.\n\nWhile at it, make the magical 150ms wait post-reset wait duration a\nconstant and ata_sff_wait_ready() and ata_sff_wait_after_reset() take\n@link instead of @ap. This is to make them consistent with other\nreset helpers and ease core changes.\n\npata_scc is updated accordingly.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\n" }, { "commit": "203c75b8245c5386044721d9c5eda5c6b71b3d14", "tree": "5a8c446c483a77dc86aca145b0b38c4a2b410dfa", "parents": [ "0aa1113d544226bc2c4a20d6ac1d71170512a361" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Apr 07 22:47:18 2008 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jgarzik@redhat.com", "time": "Thu Apr 17 15:44:22 2008 -0400" }, "message": "libata: separate out ata_std_postreset() from ata_sff_postreset()\n\nSeparate out generic ATA portion from ata_sff_postreset() into\nata_std_postreset() and implement ata_sff_postreset() using the std\nversion.\n\nata_base_port_ops now has ata_std_postreset() for its postreset and\nata_sff_port_ops overrides it to ata_sff_postreset().\n\nThis change affects pdc_adma, ahci, sata_fsl and sata_sil24. pdc_adma\nnow specifies postreset to ata_sff_postreset() explicitly. sata_fsl\nand sata_sil24 now use ata_std_postreset() which makes no difference\nto them. ahci now calls ata_std_postreset() from its own postreset\nmethod, which causes no behavior difference.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\n" }, { "commit": "5682ed33aae05d10a25c95633ef9d9c062825888", "tree": "1632d4d70f4fd2dc25596a5cde1183f70f162ac3", "parents": [ "9363c3825ea9ad76561eb48a395349dd29211ed6" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Apr 07 22:47:16 2008 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jgarzik@redhat.com", "time": "Thu Apr 17 15:44:22 2008 -0400" }, "message": "libata: rename SFF port ops\n\nAdd sff_ prefix to SFF specific port ops.\n\nThis rename is in preparation of separating SFF support out of libata\ncore layer. This patch strictly renames ops and doesn\u0027t introduce any\nbehavior difference.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\n" }, { "commit": "9363c3825ea9ad76561eb48a395349dd29211ed6", "tree": "abe89a0f7c82b805d84b1a211c97b317f6628d5f", "parents": [ "b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Apr 07 22:47:16 2008 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jgarzik@redhat.com", "time": "Thu Apr 17 15:44:21 2008 -0400" }, "message": "libata: rename SFF functions\n\nSFF functions have confusing names. Some have sff prefix, some have\nbmdma, some std, some pci and some none. Unify the naming by...\n\n* SFF functions which are common to both BMDMA and non-BMDMA are\n prefixed with ata_sff_.\n\n* SFF functions which are specific to BMDMA are prefixed with\n ata_bmdma_.\n\n* SFF functions which are specific to PCI but apply to both BMDMA and\n non-BMDMA are prefixed with ata_pci_sff_.\n\n* SFF functions which are specific to PCI and BMDMA are prefixed with\n ata_pci_bmdma_.\n\n* Drop generic prefixes from LLD specific routines. For example,\n bfin_std_dev_select -\u003e bfin_dev_select.\n\nThe following renames are noteworthy.\n\n ata_qc_issue_prot() -\u003e ata_sff_qc_issue()\n ata_pci_default_filter() -\u003e ata_bmdma_mode_filter()\n ata_dev_try_classify() -\u003e ata_sff_dev_classify()\n\nThis rename is in preparation of separating SFF support out of libata\ncore layer. This patch strictly renames functions and doesn\u0027t\nintroduce any behavior difference.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\n" }, { "commit": "a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5af", "tree": "6197c537892e0d887b2a90e369b74abf0500b9ac", "parents": [ "959471936241bd83da7d0a76411cef6772140fe6" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Tue Mar 25 12:22:50 2008 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jgarzik@redhat.com", "time": "Thu Apr 17 15:44:18 2008 -0400" }, "message": "libata: make reset related methods proper port operations\n\nCurrently reset methods are not specified directly in the\nata_port_operations table. If a LLD wants to use custom reset\nmethods, it should construct and use a error_handler which uses those\nreset methods. It\u0027s done this way for two reasons.\n\nFirst, the ops table already contained too many methods and adding\nfour more of them would noticeably increase the amount of necessary\nboilerplate code all over low level drivers.\n\nSecond, as -\u003eerror_handler uses those reset methods, it can get\nconfusing. ie. By overriding -\u003eerror_handler, those reset ops can be\nmade useless making layering a bit hazy.\n\nNow that ops table uses inheritance, the first problem doesn\u0027t exist\nanymore. The second isn\u0027t completely solved but is relieved by\nproviding default values - most drivers can just override what it has\nimplemented and don\u0027t have to concern itself about higher level\ncallbacks. In fact, there currently is no driver which actually\nmodifies error handling behavior. Drivers which override\n-\u003eerror_handler just wraps the standard error handler only to prepare\nthe controller for EH. I don\u0027t think making ops layering strict has\nany noticeable benefit.\n\nThis patch makes -\u003eprereset, -\u003esoftreset, -\u003ehardreset, -\u003epostreset and\ntheir PMP counterparts propoer ops. Default ops are provided in the\nbase ops tables and drivers are converted to override individual reset\nmethods instead of creating custom error_handler.\n\n* ata_std_error_handler() doesn\u0027t use sata_std_hardreset() if SCRs\n aren\u0027t accessible. sata_promise doesn\u0027t need to use separate\n error_handlers for PATA and SATA anymore.\n\n* softreset is broken for sata_inic162x and sata_sx4. As libata now\n always prefers hardreset, this doesn\u0027t really matter but the ops are\n forced to NULL using ATA_OP_NULL for documentation purpose.\n\n* pata_hpt374 needs to use different prereset for the first and second\n PCI functions. This used to be done by branching from\n hpt374_error_handler(). The proper way to do this is to use\n separate ops and port_info tables for each function. Converted.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\n" }, { "commit": "029cfd6b74fc5c517865fad78cf4a3ea8d9b664a", "tree": "4a40f44f29321e433497a51d2f6cfe1922ae1d58", "parents": [ "68d1d07b510bb57a504588adc2bd2758adea0965" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Tue Mar 25 12:22:49 2008 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jgarzik@redhat.com", "time": "Thu Apr 17 15:44:17 2008 -0400" }, "message": "libata: implement and use ops inheritance\n\nlibata lets low level drivers build ata_port_operations table and\nregister it with libata core layer. This allows low level drivers\nhigh level of flexibility but also burdens them with lots of\nboilerplate entries.\n\nThis becomes worse for drivers which support related similar\ncontrollers which differ slightly. They share most of the operations\nexcept for a few. However, the driver still needs to list all\noperations for each variant. This results in large number of\nduplicate entries, which is not only inefficient but also error-prone\nas it becomes very difficult to tell what the actual differences are.\n\nThis duplicate boilerplates all over the low level drivers also make\nupdating the core layer exteremely difficult and error-prone. When\ncompounded with multi-branched development model, it ends up\naccumulating inconsistencies over time. Some of those inconsistencies\ncause immediate problems and fixed. Others just remain there dormant\nmaking maintenance increasingly difficult.\n\nTo rectify the problem, this patch implements ata_port_operations\ninheritance. To allow LLDs to easily re-use their own ops tables\noverriding only specific methods, this patch implements poor man\u0027s\nclass inheritance. An ops table has -\u003einherits field which can be set\nto any ops table as long as it doesn\u0027t create a loop. When the host\nis started, the inheritance chain is followed and any operation which\nisn\u0027t specified is taken from the nearest ancestor which has it\nspecified. This operation is called finalization and done only once\nper an ops table and the LLD doesn\u0027t have to do anything special about\nit other than making the ops table non-const such that libata can\nupdate it.\n\nlibata provides four base ops tables lower drivers can inherit from -\nbase, sata, pmp, sff and bmdma. To avoid overriding these ops\naccidentaly, these ops are declared const and LLDs should always\ninherit these instead of using them directly.\n\nAfter finalization, all the ops table are identical before and after\nthe patch except for setting .irq_handler to ata_interrupt in drivers\nwhich didn\u0027t use to. The .irq_handler doesn\u0027t have any actual effect\nand the field will soon be removed by later patch.\n\n* sata_sx4 is still using old style EH and currently doesn\u0027t take\n advantage of ops inheritance.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\n" }, { "commit": "68d1d07b510bb57a504588adc2bd2758adea0965", "tree": "94e8788a8ca40017b33044329f98bbe6552cc526", "parents": [ "6bd99b4e0998571808fc1f09d5162348f21ff8c1" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Tue Mar 25 12:22:49 2008 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jgarzik@redhat.com", "time": "Thu Apr 17 15:44:17 2008 -0400" }, "message": "libata: implement and use SHT initializers\n\nlibata lets low level drivers build scsi_host_template and register it\nto the SCSI layer. This allows low level drivers high level of\nflexibility but also burdens them with lots of boilerplate entries.\n\nThis patch implements SHT initializers which can be used to initialize\nall the boilerplate entries in a sht. Three variants of them are\nimplemented - BASE, BMDMA and NCQ - for different types of drivers.\nNote that entries can be overriden by putting individual initializers\nafter the helper macro.\n\nAll sht tables are identical before and after this patch.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\n" }, { "commit": "6bd99b4e0998571808fc1f09d5162348f21ff8c1", "tree": "e338bd445aaa5cda4bbf1f5598acf70f0d6b68de", "parents": [ "358f9a77a668660729e705fde9c3cf69f013aa98" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Tue Mar 25 12:22:48 2008 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jgarzik@redhat.com", "time": "Thu Apr 17 15:44:17 2008 -0400" }, "message": "libata: normalize port_info, port_operations and sht tables\n\nOver the time, port info, ops and sht structures developed quite a bit\nof inconsistencies. This patch updates drivers.\n\n* Enable/disable_pm callbacks added to all ahci ops tables.\n\n* Every driver for SFF controllers now uses ata_sff_port_start()\n instead of ata_port_start() unless the driver has custom\n implementation.\n\n* Every driver for SFF controllers now uses ata_pci_default_filter()\n unless the driver has custom implementation.\n\n* Removed an odd port_info-\u003esht initialization from ata_piix.c.\n Likely a merge byproduct.\n\n* A port which has ATA_FLAG_SATA set doesn\u0027t need to set cable_detect\n to ata_cable_sata(). Remove it from via and mv port ops.\n\n* Some drivers had unnecessary .max_sectors initialization which is\n ignored and was missing .slave_destroy callback. Fixed.\n\n* Removed unnecessary sht initializations port_info\u0027s.\n\n* Removed onsolete scsi device suspend/resume callbacks from\n pata_bf54x.\n\n* No reason to set ata_pci_default_filter() and bmdma functions for\n PIO-only drivers. Remove those callbacks and replace\n ata_bmdma_irq_clear with ata_noop_irq_clear.\n\n* pata_platform sets port_start to ata_dummy_ret0. port_start can\n just be set to NULL.\n\n* sata_fsl supports NCQ but was missing qc_defer. Fixed.\n\n* pata_rb600_cf implements dummy port_start. Removed.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\n" }, { "commit": "358f9a77a668660729e705fde9c3cf69f013aa98", "tree": "a249660fdd9f252925eff9eaac3ed7836c839f91", "parents": [ "c1bc899f5805771926c9198e2ab4d77122c356a1" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Tue Mar 25 12:22:47 2008 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jgarzik@redhat.com", "time": "Thu Apr 17 15:44:16 2008 -0400" }, "message": "libata: implement and use ata_noop_irq_clear()\n\n-\u003eirq_clear() is used to clear IRQ bit of a SFF controller and isn\u0027t\nuseful for drivers which don\u0027t use libata SFF HSM implementation.\nHowever, it\u0027s a required callback and many drivers implement their own\nnoop version as placeholder. This patch implements ata_noop_irq_clear\nand use it to replace those custom placeholders.\n\nAlso, SFF drivers which don\u0027t support BMDMA don\u0027t need to use\nata_bmdma_irq_clear(). It becomes noop if BMDMA address isn\u0027t\ninitialized. Convert them to use ata_noop_irq_clear().\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\n" }, { "commit": "8cebf274dd1c955a6e03385a85fd6569ce445946", "tree": "c459cd20ef93413e063826bb99ca0bcaf67ec8d2", "parents": [ "672b2d65ba83a6f3f801fd3d58851aa9c0725a54" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Thu Jan 24 00:05:14 2008 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jgarzik@redhat.com", "time": "Thu Apr 17 15:44:16 2008 -0400" }, "message": "libata: kill ATA_LFLAG_SKIP_D2H_BSY\n\nSome controllers can\u0027t reliably record the initial D2H FIS after SATA\nlink is brought online for whatever reason. Advanced controllers\nwhich don\u0027t have traditional TF register based interface often have\nthis problem as they don\u0027t really have the TF registers to update\nwhile the controller and link are being initialized.\n\nSKIP_D2H_BSY works around the problem by skipping the wait for device\nreadiness before issuing SRST, so for such controllers libata issues\nSRST blindly and hopes for the best.\n\nNow that libata defaults to hardreset, this workaround is no longer\nnecessary. For controllers which have support for hardreset, SRST is\nnever issued by itself. It is only issued as follow-up SRST for\ndevice classification and PMP initialization, so there\u0027s no need to\nwait for it from prereset.\n\nKill ATA_LFLAG_SKIP_D2H_BSY.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\n" }, { "commit": "d692abd92f22a81b38d52c39601871003262841c", "tree": "4ff3f35d88762a52fb4d48adda1f39e1966b9f26", "parents": [ "cf48062658e7ab3bc55e10c65676c3c73c16f8bf" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Thu Jan 24 00:05:14 2008 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jgarzik@redhat.com", "time": "Thu Apr 17 15:44:15 2008 -0400" }, "message": "libata: kill ATA_LFLAG_HRST_TO_RESUME\n\nNow that hardreset is the preferred method of resetting, there\u0027s no\nneed for ATA_LFLAG_HRST_TO_RESUME flag. Kill it.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\n" }, { "commit": "cf48062658e7ab3bc55e10c65676c3c73c16f8bf", "tree": "9a50a016ceb6051d8a30a43ea39f2a4d3d25570e", "parents": [ "4b119e21d0c66c22e8ca03df05d9de623d0eb50f" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Thu Jan 24 00:05:14 2008 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jgarzik@redhat.com", "time": "Thu Apr 17 15:44:15 2008 -0400" }, "message": "libata: prefer hardreset\n\nWhen both soft and hard resets are available, libata preferred\nsoftreset till now. The logic behind it was to be softer to devices;\nhowever, this doesn\u0027t really help much. Rationales for the change:\n\n* BIOS may freeze lock certain things during boot and softreset can\u0027t\n unlock those. This by itself is okay but during operation PHY event\n or other error conditions can trigger hardreset and the device may\n end up with different configuration.\n\n For example, after a hardreset, previously unlockable HPA can be\n unlocked resulting in different device size and thus revalidation\n failure. Similar condition can occur during or after resume.\n\n* Certain ATAPI devices require hardreset to recover after certain\n error conditions. On PATA, this is done by issuing the DEVICE RESET\n command. On SATA, COMRESET has equivalent effect. The problem is\n that DEVICE RESET needs its own execution protocol.\n\n For SFF controllers with bare TF access, it can be easily\n implemented but more advanced controllers (e.g. ahci and sata_sil24)\n require specialized implementations. Simply using hardreset solves\n the problem nicely.\n\n* COMRESET initialization sequence is the norm in SATA land and many\n SATA devices don\u0027t work properly if only SRST is used. For example,\n some PMPs behave this way and libata works around by always issuing\n hardreset if the host supports PMP.\n\n Like the above example, libata has developed a number of mechanisms\n aiming to promote softreset to hardreset if softreset is not going\n to work. This approach is time consuming and error prone.\n\n Also, note that, dependingon how you read the specs, it could be\n argued that PMP fan-out ports require COMRESET to start operation.\n In fact, all the PMPs on the market except one don\u0027t work properly\n if COMRESET is not issued to fan-out ports after PMP reset.\n\n* COMRESET is an integral part of SATA connection and any working\n device should be able to handle COMRESET properly. After all, it\u0027s\n the way to signal hardreset during reboot. This is the most used\n and recommended (at least by the ahci spec) method of resetting\n devices.\n\nSo, this patch makes libata prefer hardreset over softreset by making\nthe following changes.\n\n* Rename ATA_EH_RESET_MASK to ATA_EH_RESET and use it whereever\n ATA_EH_{SOFT|HARD}RESET used to be used. ATA_EH_{SOFT|HARD}RESET is\n now only used to tell prereset whether soft or hard reset will be\n issued.\n\n* Strip out now unneeded promote-to-hardreset logics from\n ata_eh_reset(), ata_std_prereset(), sata_pmp_std_prereset() and\n other places.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\n" }, { "commit": "4cde32fc4b32e96a99063af3183acdfd54c563f0", "tree": "1aaf39e056f1f9470fae9e8e9bc84ee603afca64", "parents": [ "c07a9c4995827a4f4bcdbd07cec40ec87467f308" ], "author": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Mon Mar 24 22:40:40 2008 -0400" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Mon Mar 24 22:40:40 2008 -0400" }, "message": "[libata] ahci: SB600 workaround is suspect... play it safe for now\n\nAt least one report claims that a878539ef994787c447a98c2e3ba0fe3dad984ec\nfailed to solve lockups, whereas the old limit-to-32-bit trick worked.\n\nRestore the 32-bit limit, but also leave the 255-sector limit in place,\nbecause we know that\u0027s needed as well.\n\nSigned-off-by: Jeff Garzik \u003cjgarzik@redhat.com\u003e\n" }, { "commit": "c40e7cb89f9d36924131ef708ff1f16a76611add", "tree": "d5a9348c45c037e1c9224a00c2937f5c718fd8ed", "parents": [ "4a38e733a75d52e84772fc00d88e32032a235e75" ], "author": { "name": "Jose Alberto Reguero", "email": "jareguero@telefonica.net", "time": "Thu Mar 13 23:22:24 2008 +0100" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Mon Mar 17 08:30:32 2008 -0400" }, "message": "ahci: Add Marvell 6121 SATA support\n\nSigned-off-by: Jose Alberto Reguero \u003cjareguero@telefonica.net\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "a22e64443f0aa4aa4e3c56a49e5c060e90752c07", "tree": "cc9db844ba0099aced1ad1faf3859da84ab75a09", "parents": [ "dea55137634226fd74d5187a15dee1244ec252cb" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Mar 10 10:25:25 2008 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Mon Mar 17 08:26:50 2008 -0400" }, "message": "ahci: implement skip_host_reset parameter\n\nUnder certain circumstances (SSP turned off by the BIOS) and for\ndebugging purposes, skipping global controller reset is helpful. Add\na kernel parameter for it.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "dea55137634226fd74d5187a15dee1244ec252cb", "tree": "f7acf611f82a0af1194e0375fed462f536f13348", "parents": [ "916fbfb7ae5f8c8f86399794d89e6d273df8826b" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Tue Mar 11 19:52:31 2008 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Mon Mar 17 08:26:47 2008 -0400" }, "message": "ahci: request all PCI BARs\n\nahci is often implemented with accompanying SFF compatible interface\nand legacy IDE driver may attach to the legacy IO ports when the\ncontroller is already claimed by ahci and vice-versa. This patch\nmakes ahci use pcim_iomap_regions_request_all() so that all IO regions\nare claimed on attach.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "258cd8464b618d5ec3b836f02cce05e3faf226b4", "tree": "cec1247e939f818d3d0ab13fe895df3c3d425e31", "parents": [ "7afb42226a8eaa9ae3f6b9917ffb16902358e749" ], "author": { "name": "Roel Kluin", "email": "12o3l@tiscali.nl", "time": "Sun Mar 09 21:42:40 2008 +0100" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Mon Mar 10 20:51:16 2008 -0400" }, "message": "ahci: logical-bitwise and confusion in ahci_save_initial_config()\n\nlogical-bitwise \u0026 confusion\n\nSigned-off-by: Roel Kluin \u003c12o3l@tiscali.nl\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "70d562cf7853ea1bb53c1007075c5df958f11c90", "tree": "66e342103b1579f90e31cf2e081af8d0e973c71b", "parents": [ "f659f0e4480bb82e6dcf3db8ba1e8485444084e5" ], "author": { "name": "peerchen", "email": "peerchen@gmail.com", "time": "Thu Mar 06 21:22:41 2008 +0800" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Mon Mar 10 20:50:52 2008 -0400" }, "message": "ahci: add the Device IDs for nvidia MCP7B AHCI\n\nSigned-off-by: Peer Chen \u003cpeerchen@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "a878539ef994787c447a98c2e3ba0fe3dad984ec", "tree": "3c2b16121143c4dad805b048b2cee5d4c410384a", "parents": [ "6ddd68615ae9b21096545d7d6ab0f04113ae8b42" ], "author": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Thu Feb 28 15:43:48 2008 -0500" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Wed Mar 05 07:53:06 2008 -0500" }, "message": "ahci: work around ATI SB600 h/w quirk\n\nThis addresses the recent ATI SB600 errata, where the hardware does\nnot like 256-length PRD entries during FPDMA (aka NCQ).\n\nIt hurts performance on SB600, but it is more important to get a\ncorrect patch eliminating the data corruption/lockups, and then later\non tune for performance.\n\nWe simply limit each command to a maximum of 255 sectors, on SB600.\n\nSigned-off-by: Jeff Garzik \u003cjgarzik@redhat.com\u003e\n" }, { "commit": "e39fc8c9fd0bb6f4018186801e4a53a5eccaaf70", "tree": "a697763c7714bb8e44c841d03e074e9415919614", "parents": [ "39f25e70ca37b8a719e8274e6f3ec2ce2ea8df04" ], "author": { "name": "Shane Huang", "email": "ati.shane@gmail.com", "time": "Fri Feb 22 05:00:31 2008 -0800" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Sun Feb 24 00:28:44 2008 -0500" }, "message": "[libata] ahci: AMD SB700/SB800 SATA support 64bit DMA\n\nSB700 SATA controller can support 64 bit DMA, the previous commit\nbadc2341579511a247f5993865aa68379e283c5c was added with\ncareless reference to SB600, which should be modified by this patch.\n\nSigned-off-by: Shane Huang \u003cshane.huang@amd.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "3a2d5b700132f35401f1d9e22fe3c2cab02c2549", "tree": "ad991428c41aee92a5f78b06bf73430af0e6f7ae", "parents": [ "39273b58a409cd6d65c9732bdca00bacd1626672" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Sat Feb 23 19:13:25 2008 +0100" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@woody.linux-foundation.org", "time": "Sat Feb 23 10:40:04 2008 -0800" }, "message": "PM: Introduce PM_EVENT_HIBERNATE callback state\n\nDuring the last step of hibernation in the \"platform\" mode (with the\nhelp of ACPI) we use the suspend code, including the devices\u0027\n-\u003esuspend() methods, to prepare the system for entering the ACPI S4\nsystem sleep state.\n\nBut at least for some devices the operations performed by the\n-\u003esuspend() callback in that case must be different from its operations\nduring regular suspend.\n\nFor this reason, introduce the new PM event type PM_EVENT_HIBERNATE and\npass it to the device drivers\u0027 -\u003esuspend() methods during the last phase\nof hibernation, so that they can distinguish this case and handle it as\nappropriate. Modify the drivers that handle PM_EVENT_SUSPEND in a\nspecial way and need to handle PM_EVENT_HIBERNATE in the same way.\n\nThese changes are necessary to fix a hibernation regression related\nto the i915 driver (ref. http://lkml.org/lkml/2008/2/22/488).\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nAcked-by: Pavel Machek \u003cpavel@ucw.cz\u003e\nTested-by: Jeff Chua \u003cjeff.chua.linux@gmail.com\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "dde2020754aeb14e17052d61784dcb37f252aac2", "tree": "1b6d57c6eff2024fd13e4b3b115d0a6770d8cb80", "parents": [ "db0a2e0099be3a1cff55879225881465f16c67d3" ], "author": { "name": "James Bottomley", "email": "James.Bottomley@HansenPartnership.com", "time": "Tue Feb 19 11:36:56 2008 +0100" }, "committer": { "name": "Jens Axboe", "email": "jens.axboe@oracle.com", "time": "Tue Feb 19 11:36:56 2008 +0100" }, "message": "libata: eliminate the home grown dma padding in favour of\n\nthat provided by the block layer\n\nATA requires that all DMA transfers begin and end on word boundaries.\nBecause of this, a large amount of machinery grew up in ide to adjust\nscatterlists on this basis. However, as of 2.5, the block layer has a\ndma_alignment variable which ensures both the beginning and length of a\nDMA transfer are aligned on the dma_alignment boundary. Although the\nblock layer does adjust the beginning of the transfer to ensure this\nhappens, it doesn\u0027t actually adjust the length, it merely makes sure\nthat space is allocated for transfers beyond the declared length. The\nupshot of this is that scatterlists may be padded to any size between\nthe actual length and the length adjusted to the dma_alignment safely\nknowing that memory is allocated in this region.\n\nRight at the moment, SCSI takes the default dma_aligment which is on a\n512 byte boundary. Note that this aligment only applies to transfers\ncoming in from user space. However, since all kernel allocations are\nautomatically aligned on a minimum of 32 byte boundaries, it is safe to\nadjust them in this manner as well.\n\ntj: * Adjusting sg after padding is done in block layer. Make libata\n set queue alignment correctly for ATAPI devices and drop broken\n sg mangling from ata_sg_setup().\n * Use request-\u003eraw_data_len for ATAPI transfer chunk size.\n * Killed qc-\u003eraw_nbytes.\n * Separated out killing qc-\u003en_iter.\n\nSigned-off-by: James Bottomley \u003cJames.Bottomley@HansenPartnership.com\u003e\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jens Axboe \u003cjens.axboe@oracle.com\u003e\n" }, { "commit": "837f5f8fb98d4357d49e9631c9ee2815f3c328ca", "tree": "25c24b611fd66b0599d8145716513339d42a7bb3", "parents": [ "f351b2d638c3cb0b95adde3549b7bfaf3f991dfa" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Wed Feb 06 15:13:51 2008 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Wed Feb 06 06:59:27 2008 -0500" }, "message": "ahci: fix CAP.NP and PI handling\n\nAHCI uses CAP.NP to indicate the number of ports and PI to tell which\nports are enabled. The only requirement is that the number of ports\nindicated by CAP.NP should equal or be higher than the number of\nenabled ports in PI.\n\nCAP.NP and PI carry duplicate information and there have been some\ninteresting cases. Some early AHCI controllers didn\u0027t set PI at all\nand just implement from port 0 to CAP.NP. An ICH8 board which wired\nfour out of six available ports had 3 (4 ports) for CAP.NP and 0x33\nfor PI. While ESB2 has less bits set in PI than the value in CAP.NP.\n\nTill now, ahci driver assumed that PI is invalid if it doesn\u0027t match\nCAP.NP exactly. This violates AHCI standard and the driver ends up\naccessing unmimplemented ports on ESB2.\n\nThis patch updates CAP.NP and PI handling such that PI can have less\nnumber of bits set than indicated in CAP.NP and the highest port is\ndetermined as the maximum port of what CAP.NP and PI indicate.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nCc: Jan Beulich \u003cjbeulich@novell.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "16ad1ad9cbce153f4bfed22f9b9a6db4ae212fc7", "tree": "78dcdaa5f7effda33c6d93c8ef56fc5f0c8c0830", "parents": [ "da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0e" ], "author": { "name": "Jason Gaston", "email": "jason.d.gaston@intel.com", "time": "Mon Jan 28 17:34:14 2008 -0800" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Feb 01 11:29:48 2008 -0500" }, "message": "ahci: RAID mode SATA patch for Intel ICH10 DeviceID\u0027s\n\nThis patch adds the Intel ICH10 SATA RAID Controllers DeviceID\u0027s.\n\nSigned-off-by: Jason Gaston \u003cjason.d.gaston@intel.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "b710a1f4b34438b624e9c6c2dc8bcf54b0b0ba27", "tree": "f8bb87bd4cbc2591da8c0b9bdaf01b426902800b", "parents": [ "c729072459446885c5c200137de1db32da5db4dc" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Sat Jan 05 23:11:57 2008 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Wed Jan 23 05:24:16 2008 -0500" }, "message": "ahci: factor out AHCI enabling and enable AHCI before reading CAP\n\nFactor out AHCI enabling into ahci_enable_ahci() and enabling AHCI\nbefore reading CAP in ahci_save_initial_config() as the spec requires\nenabling AHCI mode before accessing any other registers.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "4ca4e439640cd1d3659cbcf60e7a73c2ae0450b3", "tree": "659dceb7469341dca95d7a96774e787c3b510872", "parents": [ "35a10a80daa04b7316d6bac1b1402cc347c35b1e" ], "author": { "name": "Al Viro", "email": "viro@ZenIV.linux.org.uk", "time": "Sun Dec 30 09:32:22 2007 +0000" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Wed Jan 23 05:24:15 2008 -0500" }, "message": "libata annotations and fixes\n\nSigned-off-by: Al Viro \u003cviro@zeniv.linux.org.uk\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "ff2aeb1eb64c8a4770a6304f9addbae9f9828646", "tree": "c6febbec290ec6c40bf3abc7bcdb7188f5039443", "parents": [ "f92a26365a72333f418abe82700c6030d4a1a807" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Wed Dec 05 16:43:11 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Wed Jan 23 05:24:14 2008 -0500" }, "message": "libata: convert to chained sg\n\nlibata used private sg iterator to handle padding sg. Now that sg can\nbe chained, padding can be handled using standard sg ops. Convert to\nchained sg.\n\n* s/qc-\u003e__sg/qc-\u003esg/\n\n* s/qc-\u003epad_sgent/qc-\u003eextra_sg[]/. Because chaining consumes one sg\n entry. There need to be two extra sg entries. The renaming is also\n for future addition of other extra sg entries.\n\n* Padding setup is moved into ata_sg_setup_extra() which is organized\n in a way that future addition of other extra sg entries is easy.\n\n* qc-\u003eorig_n_elem is unused and removed.\n\n* qc-\u003en_elem now contains the number of sg entries that LLDs should\n map. qc-\u003emapped_n_elem is added to carry the original number of\n mapped sgs for unmapping.\n\n* The last sg of the original sg list is used to chain to extra sg\n list. The original last sg is pointed to by qc-\u003elast_sg and the\n content is stored in qc-\u003esaved_last_sg. It\u0027s restored during\n ata_sg_clean().\n\n* All sg walking code has been updated. Unnecessary assertions and\n checks for conditions the core layer already guarantees are removed.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nCc: Jens Axboe \u003cjens.axboe@oracle.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "405e66b38797875e80669eaf72d313dbb76533c3", "tree": "a069f0bb4ae1e81a58bc8f8965a2443d25186f0d", "parents": [ "f20ded38aa54b92dd0af32578b8916d0aa2d9e05" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Tue Nov 27 19:28:53 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Wed Jan 23 05:24:10 2008 -0500" }, "message": "libata: implement protocol tests\n\nImplement protocol tests - ata_is_atapi(), ata_is_nodata(),\nata_is_pio(), ata_is_dma(), ata_is_ncq() and ata_is_data() and use\nthem to replace is_atapi_taskfile() and hard coded protocol tests.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "49f290903935612aadab3899a4aca884c1140348", "tree": "93e98e81a7d359c679ce081295d939be948c1c80", "parents": [ "51dbd490614e6228e9b2b198bd4f5f76ef961059" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Nov 19 16:03:44 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Wed Jan 23 05:24:10 2008 -0500" }, "message": "ahci: update PCS programming\n\nFor intel ones, ahci unconditionally OR\u0027d 0xf to PCS. This isn\u0027t\ncorrect for the following cases.\n\n* ich6/7m\u0027s which only implement P0 and P2 (0xf works fine tho)\n\n* ich8/9\u0027s which have six ports and needs 0x3f to enable all ports\n\nThis patch updates PCS programming such that...\n\n* port_map determined by ahci_save_initial_config() is OR\u0027d instead of 0xf\n\n* PCS is updated only if necessary (there are turned off enable bits)\n\nport_map is determined from PORTS_IMPL PCI register which is\nimplemented as write or write-once register. If the register isn\u0027t\nprogrammed, ahci automatically generates it from number of ports,\nwhich is good enough for PCS programming. ICH6/7M are probably the\nonly ones where non-contiguous enable bits are necessary \u0026\u0026 PORTS_IMPL\nisn\u0027t programmed properly but they\u0027re proven to work reliably with 0xf\nanyway.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "459ad68893a84fb0881e57919340b97edbbc3dc7", "tree": "04e7d419836214e3cb8a21f97a79697d0d9f0035", "parents": [ "c4f7792c021cda9bbf65d0bc2253a593fd652b91" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Fri Dec 07 12:46:23 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Dec 07 15:27:54 2007 -0500" }, "message": "libata: kill spurious NCQ completion detection\n\nSpurious NCQ completion detection implemented in ahci was incorrect.\nOn AHCI receving and processing FISes and raising interrupts are not\ninterlocked and spurious interrupts are expected.\n\nFor example, if an interrupt occurs while interrupt handler is running\nand the running interrupt handler handles the event the new IRQ\nindicated, after IRQ handler finishes, it will be executed again\nbecause IRQ pending bit is set by the new interrupt but there won\u0027t be\nanything to process.\n\nPlease read the following message for more information.\n\n http://article.gmane.org/gmane.linux.ide/26012\n\nThis patch...\n\n* Removes all spurious IRQ whining from ahci. Spurious NCQ completion\n detection was completely wrong. Spurious D2H Register FIS taught us\n that some early drives send spurious D2H Register FIS with I bit set\n while NCQ commands are in progress but none of recent drives does\n that and even the ones which show such behavior can do NCQ fine.\n\n* Kills all NCQ blacklist entries which were added because of spurious\n NCQ completions. I tracked down each commit and verified all\n removed ones are actually added because of spurious completions.\n\n WD740ADFD-00NLR1 wasn\u0027t deleted but moved upward because the drive\n not only had spurious NCQ completions but also is slow on sequential\n data transfers if NCQ is enabled.\n\n Maxtor 7V300F0 was added by 0e3dbc01d53940fe10e5a5cfec15ede3e929c918\n from Alan Cox. I can only find evidences that the drive only had\n troubles with spuruious completions by searching the mailing list.\n This entry needs to be verified and removed if it doesn\u0027t have other\n NCQ related problems.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nCc: Alan Cox \u003calan@lxorguk.ukuu.org.uk\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "c4f7792c021cda9bbf65d0bc2253a593fd652b91", "tree": "e0c727ba1bc934a8cbc58515c5b33e16eecde8a2", "parents": [ "d1aa690a7d1afa673c3383bfcd6e96ddb350939a" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Thu Dec 06 15:09:43 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Dec 07 15:27:54 2007 -0500" }, "message": "ahci: don\u0027t attach if ICH6 is in combined mode\n\nICH6 R/Ms share PCI ID between piix and ahci modes and we\u0027ve been\nallowing ahci to attach regardless of how BIOS configured it.\nHowever, enabling AHCI mode when the controller is in combined mode\ncan result in unexpected behavior. Don\u0027t attach if the controller is\nin combined mode.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nCc: Bill Nottingham \u003cnotting@redhat.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "994056d7aa884c742f58e2f2c17305bb01bf14e7", "tree": "41db117f56760ffb89dba6ae505799cf6ba27430", "parents": [ "2c5ea0f2d8c7d4883dd0d8ec3c7e3f3640b4f814" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Thu Dec 06 15:02:48 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Dec 07 15:27:53 2007 -0500" }, "message": "ahci: fix engine reset failed message\n\nThere isn\u0027t much point in reporting -EOPNOTSUPP as failure. Also the\nmessage was missing newline.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "6ba8695870a5a2ebf6f3d1ee3ac1e4d96d667cf6", "tree": "f272a1a157b23036751314f0ce885080a8b17677", "parents": [ "306b30f74d37f289033c696285e07ce0158a5d7b" ], "author": { "name": "peerchen", "email": "peerchen@gmail.com", "time": "Mon Dec 03 22:20:37 2007 +0800" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Tue Dec 04 14:10:14 2007 -0500" }, "message": "ahci: add the Device IDs of MCP79 AHCI controller to ahci.c\n\nAdd the device IDs of legacy mode of MCP79 AHCI controller to ahci.c\n\nSigned-off-by: Peer Chen \u003cpeerchen@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "31556594f913fa81d008cecfe46d7211c919a853", "tree": "424db37711a0805aef50f6e76b8686eb36ab5147", "parents": [ "ca77329fb713b7fea6a307068e0dd0248e7aa640" ], "author": { "name": "Kristen Carlson Accardi", "email": "kristen.c.accardi@intel.com", "time": "Thu Oct 25 01:33:26 2007 -0400" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Mon Oct 29 11:00:35 2007 -0400" }, "message": "[libata] AHCI: add hw link power management support\n\nThis patch will set the correct bits to turn on Aggressive\nLink Power Management (ALPM) for the ahci driver. This\nwill cause the controller and disk to negotiate a lower\npower state for the link when there is no activity (see\nthe AHCI 1.x spec for details). This feature is mutually\nexclusive with Hot Plug, so when ALPM is enabled, Hot Plug\nis disabled. ALPM will be enabled by default, but it is\nsettable via the scsi host syfs interface. Possible\nsettings for this feature are:\n\nSetting Effect\n----------------------------------------------------------\nmin_power ALPM is enabled, and link set to enter\n lowest power state (SLUMBER) when idle\n Hot plug not allowed.\n\nmax_performance ALPM is disabled, Hot Plug is allowed\n\nmedium_power ALPM is enabled, and link set to enter\n second lowest power state (PARTIAL) when\n idle. Hot plug not allowed.\n\nSigned-off-by: Kristen Carlson Accardi \u003ckristen.c.accardi@intel.com\u003e\nSigned-off-by: Jeff Garzik \u003cjgarzik@redhat.com\u003e\n" }, { "commit": "ab6fc95f609b372a19e18ea689986846ab1ba29c", "tree": "596c0139d5054bfe31b3c3ee36bcc8e6c50e8f9f", "parents": [ "360737a982b1ae09e1659e0bb27085c03f02f404" ], "author": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Mon Oct 29 10:43:55 2007 -0400" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Mon Oct 29 10:43:55 2007 -0400" }, "message": "[libata] AHCI: fix newly introduced host-reset bug\n\nThe recent fix to host reset introduced a problem, whereby AHCI-enable\nbit would be cleared upon reset, if it was not asserted prior to reset.\n\nUnconditionally enable AHCI-enable bit.\n\nSigned-off-by: Jeff Garzik \u003cjgarzik@redhat.com\u003e\n" }, { "commit": "88ff6eafbb2a1c55f0f0e2e16d72e7b10d8ae8a5", "tree": "ad6ab294a4f725540bfa24b7a451273b99fa71c1", "parents": [ "054a5fbaceb2eb3a31ea843c1cf0b8e10b91478c" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Tue Oct 16 14:21:24 2007 -0700" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Mon Oct 29 06:15:27 2007 -0400" }, "message": "libata: implement ata_wait_after_reset()\n\nOn certain device/controller combination, 0xff status is asserted\nafter reset and doesn\u0027t get cleared during 150ms post-reset wait. As\n0xff status is interpreted as no device (for good reasons), this can\nlead to misdetection on such cases.\n\nThis patch implements ata_wait_after_reset() which replaces the 150ms\nsleep and waits upto ATA_TMOUT_FF_WAIT if status is 0xff.\nATA_TMOUT_FF_WAIT is currently 800ms which is enough for\nHHD424020F7SV00 to get detected but not enough for Quantum GoVault\ndrive which is known to take upto 2s.\n\nWithout parallel probing, spending 2s on 0xff port would incur too\nmuch delay on ata_piix\u0027s which use 0xff to indicate empty port and\ndoesn\u0027t have SCR register, so GoVault needs to wait till parallel\nprobing.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "edc93052844c2032b2ec5910ace516da9078714d", "tree": "f99c1f1c529cdcbf93f12bf79583b287657abd49", "parents": [ "c15fcafe1c42daff212d78d4ce9619a52a74379f" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Thu Oct 25 14:59:16 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Thu Oct 25 02:06:59 2007 -0400" }, "message": "ahci: ahci: implement workaround for ASUS P5W-DH Deluxe ahci_broken_hardreset(), take #2\n\nP5W-DH Deluxe has ICH9 which doesn\u0027t have PMP support but SIMG 4726\nhardwired to the second port of AHCI controller at PCI device 1f.2.\nThe 4726 doesn\u0027t work as PMP but as a storage processor which can do\nhardware RAID on downstream ports.\n\nWhen no device is attached to the downstream port of the 4726, pseudo\nATA device for configuration appears. Unfortunately, ATA emulation on\nthe device is very lousy and causes long hang during boot.\n\nThis patch implements workaround for the board. If the mainboard is\nP5W-DH Deluxe (matched using DMI), only hardreset is used on the\nsecond port of AHCI controller @ 1f.2 and the hardreset doesn\u0027t depend\non receiving the first FIS and just proceed to IDENTIFY.\n\nThis workaround fixes bugzilla #8923.\n\n http://bugzilla.kernel.org/show_bug.cgi?id\u003d8923\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "2dcb407e61458ded17503d6bd12b8c064965368b", "tree": "6044e032197b84f9943a385b0c9dbb6656c3f97f", "parents": [ "01e7ae8c13bb06a2ce622ebace33bb7e28ef596c" ], "author": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 19 06:42:56 2007 -0400" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Tue Oct 23 20:59:42 2007 -0400" }, "message": "[libata] checkpatch-inspired cleanups\n\nTackle the relatively sane complaints of checkpatch --file.\n\nThe vast majority is indentation and whitespace changes, the rest are\n\n* #include fixes\n* printk KERN_xxx prefix addition\n* BSS/initializer cleanups\n\nSigned-off-by: Jeff Garzik \u003cjgarzik@redhat.com\u003e\n" }, { "commit": "3a4fa0a25da81600ea0bcd75692ae8ca6050d165", "tree": "a4de1662e645c029cf3cf58f0646cbb1959861dc", "parents": [ "18735dd8d2d37031b97f9e9e106acbaed01eb896" ], "author": { "name": "Robert P. J. Day", "email": "rpjday@mindspring.com", "time": "Fri Oct 19 23:10:43 2007 +0200" }, "committer": { "name": "Adrian Bunk", "email": "bunk@kernel.org", "time": "Fri Oct 19 23:10:43 2007 +0200" }, "message": "Fix misspellings of \"system\", \"controller\", \"interrupt\" and \"necessary\".\n\nFix the various misspellings of \"system\", controller\", \"interrupt\" and\n\"[un]necessary\".\n\nSigned-off-by: Robert P. J. Day \u003crpjday@mindspring.com\u003e\nSigned-off-by: Adrian Bunk \u003cbunk@kernel.org\u003e\n" }, { "commit": "b06ce3e51e3df4394a584c234f11240b1c6f8d5b", "tree": "6a6f5a1cccdc2972b236d376afeba4fd296d5400", "parents": [ "afaa5c373d2c49ee4865847031b82f1377f609d0" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Tue Oct 09 15:06:48 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:47 2007 -0400" }, "message": "libata: use ata_exec_internal() for PMP register access\n\nPMP registers used to be accessed with dedicated accessors -\u003epmp_read\nand -\u003epmp_write. During reset, those callbacks are called with the\nport frozen so they should be able to run without depending on\ninterrupt delivery. To achieve this, they were implemented polling.\n\nHowever, as resetting the host port makes the PMP to isolate fan-out\nports until SError.X is cleared, resetting fan-out ports while port is\nfrozen doesn\u0027t buy much additional safety.\n\nThis patch updates libata PMP support such that PMP registers are\naccessed using regular ata_exec_internal() mechanism and kills\n-\u003epmp_read/write() callbacks. The following changes are made.\n\n* PMP access helpers - sata_pmp_read_init_tf(), sata_pmp_read_val(),\n sata_pmp_write_init_tf() are folded into sata_pmp_read/write() which\n are now standalone PMP register access functions.\n\n* sata_pmp_read/write() returns err_mask instead of rc. This is\n consistent with other functions which issue internal commands and\n allows more detailed error reporting.\n\n* ahci interrupt handler is modified to ignore BAD_PMP and\n spurious/illegal completion IRQs while reset is in progress. These\n conditions are expected during reset.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "5f226c6bf78edab023ed1ea679531731d9df92a6", "tree": "01e0dff1224476aa52c240ee958ec7948bb85cc6", "parents": [ "1c954a4d9a9e351fa3509533fd8dd5f3821206cd" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Tue Oct 09 15:02:23 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:47 2007 -0400" }, "message": "ahci: fix notification handling\n\nAsynchronous notification on ICH9 didn\u0027t work because it didn\u0027t write\nAN FIS into the RX area - it only updates SNotification. Also,\nsnooping SDB_FIS RX area is racy against further SDB FIS receptions.\nLet sata_async_notification() determine using SNTF if it\u0027s available\nand snoop RX area iff SNTF isn\u0027t available\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nCc: Kristen Carlson Accardi \u003ckristen.c.accardi@intel.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "1c954a4d9a9e351fa3509533fd8dd5f3821206cd", "tree": "edc1571ab692de818543b9c5ddbd80e6bbbfca29", "parents": [ "75da6d2b8f518bec40546bc0b0696a2cebecf6cc" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Tue Oct 09 15:01:37 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:47 2007 -0400" }, "message": "ahci: clean up PORT_IRQ_BAD_PMP enabling\n\nNow that we have pp-\u003eintr_mask, move PORT_IRQ_BAD_PMP enabling to\nahci_pmp_attach/detach() where it belongs.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "75da6d2b8f518bec40546bc0b0696a2cebecf6cc", "tree": "2ee776da78cfc3dd9a42ebcfdc7864248982159f", "parents": [ "9073868376ed5fa1f247327ccb2e6f766d5b7eed" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Tue Oct 09 14:59:50 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:46 2007 -0400" }, "message": "ahci: kill leftover from enabling NCQ over PMP\n\nahci had problems with NCQ over PMP and NCQ used to be disabled while\nPMP was attached. After fixing the problem, the temporary NCQ\ndisabling code wasn\u0027t removed completely. Kill the remaining piece.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "7100819f5f9b99eb7c7dd5597f293388a405bf7b", "tree": "3a386aab745c01976318ada8559db7f1cb5b76d4", "parents": [ "1333e19434da116bc832e1b8925359d1565fedc9" ], "author": { "name": "Peer Chen", "email": "peerchen@gmail.com", "time": "Mon Sep 24 10:16:25 2007 +0800" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:45 2007 -0400" }, "message": "ahci: Add MCP79 support to AHCI driver\n\nSigned-off-by: Peer Chen \u003cpeerchen@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "6949b9148d3656afc13a2ccc06d13c071ec71bdc", "tree": "fc8021205536a67e7701ad413767a412449e51f7", "parents": [ "417a1a6d3d7abad4c5288135f640e6e38e7a65c5" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Sun Sep 23 13:19:55 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:44 2007 -0400" }, "message": "ahci: implement AHCI_HFLAG_NO_PMP\n\nOf course some controllers lie about PMP support. Black list them.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "417a1a6d3d7abad4c5288135f640e6e38e7a65c5", "tree": "87207680dbfb4b06f6267a49fbea68a880fba894", "parents": [ "7d50b60b5e38f910ad69f0187af00f5d6a8970d4" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Sun Sep 23 13:19:55 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:44 2007 -0400" }, "message": "ahci: move host flags over to pi.private_data\n\nPrivate pi.flags area is full and we need more private flags. Move\nhost private flags over to pi.private_data. During initialization,\nthese flags are copied to hpriv-\u003eflags.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "7d50b60b5e38f910ad69f0187af00f5d6a8970d4", "tree": "627c57902e588ad6e7f51a2df9f2b8f091e014c0", "parents": [ "238180343eff95697ed71eea137cf61ba3cea6ad" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Sun Sep 23 13:19:54 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:44 2007 -0400" }, "message": "ahci: implement PMP support\n\nImplement AHCI PMP support. ahci only supports command based\nswitching. Also, for some reason, NCQ over PMP doesn\u0027t work now.\nOther than that, everything works.\n\nTested on ICH9R, JMB360/363 + SIMG3726, 4726 and 5744.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nCc: Forrest Zhao \u003cforrest.zhao@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "3cc3eb1148e4b2dfabf7a1dcf36fd8be1331ca95", "tree": "5f987f613eb8dae6c170f97fe9acb47379902a32", "parents": [ "b90fe23bd51c6b1c298159591c833bdd24f55002" ], "author": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Wed Sep 26 00:02:41 2007 -0400" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:42 2007 -0400" }, "message": "[libata] AHCI: enable AHCI mode, before using AHCI reset\n\nAHCI spec says host-reset bit may only be set when the ahci-enable bit\nis also set.\n\nNoticed by Peer Chen \u003cpeerchen@gmail.com\u003e\n\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "7d77b247088fb360aa74bfdd9e19bce1e1987668", "tree": "add1b03309dd6fa82eb0f47e1a88766695f38f28", "parents": [ "e31e8531d668c9c4dc7883054788f89805188003" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Sun Sep 23 13:14:13 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:42 2007 -0400" }, "message": "libata-pmp-prep: implement sata_async_notification()\n\nAN serves multiple purposes. For ATAPI, it\u0027s used for media change\nnotification. For PMP, for downstream PHY status change notification.\nImplement sata_async_notification() which demultiplexes AN.\n\nTo avoid unnecessary port events, ATAPI AN is not enabled if PMP is\nattached but SNTF is not available.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nCc: Kriten Carlson Accardi \u003ckristen.c.accardi@intel.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "31cc23b34913bc173680bdc87af79e551bf8cc0d", "tree": "ec64421ead9259174f0de8b22c36449ece6d69a4", "parents": [ "fb7fd61454c8681cd2621051a710b78a00369203" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Sun Sep 23 13:14:12 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:41 2007 -0400" }, "message": "libata-pmp-prep: implement ops-\u003eqc_defer()\n\nControllers which support PMP have various restrictions on which\ncombinations of commands are allowed to what number of devices\nconcurrently. This patch implements ops-\u003eqc_defer() which determines\nwhether a qc can be issued at the moment or should be deferred.\n\nIf the function returns ATA_DEFER_LINK, the qc will be deferred until\na qc completes on the link. If ATA_DEFER_PORT, until a qc completes\non any link. The defer conditions are advisory and in general\nATA_DEFER_LINK can be considered as lower priority deferring than\nATA_DEFER_PORT.\n\nops-\u003eqc_defer() replaces fixed ata_scmd_need_defer(). For standard\nNCQ/non-NCQ exclusion, ata_std_qc_defer() is implemented. ahci and\nsata_sil24 are converted to use ata_std_qc_defer().\n\nops-\u003eqc_defer() is heavier than the original mechanism because full qc\nis prepped before determining to defer it, but various information is\nneeded to determine defer conditinos and fully translating a qc is the\nonly way to supply such information in generic manner.\n\nIMHO, this shouldn\u0027t cause any noticeable performance issues as\n\n* for most cases deferring occurs rarely (except for NCQ-aware\n cmd-switching PMP)\n* translation itself isn\u0027t that expensive\n* once deferred the command won\u0027t be repeated until another command\n completes which usually is a very long time cpu-wise.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "854c73a2f1c3bcc4aa88c25e208dc597e8efb795", "tree": "210569f3c4fa4f9413ceb0bc3fcf89648a9894b2", "parents": [ "c78968bb0f7714ceba1cdfa23714454fc98cefdf" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Sun Sep 23 13:14:11 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:40 2007 -0400" }, "message": "libata: misc updates for AN\n\nUpdate AN support in preparation of PMP support.\n\n* s/ata_id_has_AN/ata_id_has_atapi_AN/\n* add AN enabled reporting during configuration\n* add err_mask to AN configuration failure reporting\n* update LOCKING comment for ata_scsi_media_change_notify()\n* check whether ATA dev is attached to SCSI dev ata_scsi_media_change_notify()\n* set ATA_FLAG_AN in ahci and sata_sil24\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nCc: Kriten Carlson Accardi \u003ckristen.c.accardi@intel.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "d4155e6f13e931048036976d9fb47b5db53ee7a3", "tree": "cdcdc7161c2230cbf09339fc0979760bf90a02a5", "parents": [ "d7fbee050753e153622b5d41bc8bd1cb19cda9b9" ], "author": { "name": "Jason Gaston", "email": "jason.d.gaston@intel.com", "time": "Thu Sep 20 17:35:00 2007 -0400" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:39 2007 -0400" }, "message": "ahci: RAID mode SATA patch for Intel Tolapai\n\nSigned-off-by: Jason Gaston \u003cjason.d.gaston@intel.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "7a234aff3d83728fd83cf19df32d3df52566d2ac", "tree": "d991844bf7a7882eacd72a57a1465b25dc55e95d", "parents": [ "05027adccc09401a7e31d5ef51040dc75ab03c22" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Sep 03 12:44:57 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:39 2007 -0400" }, "message": "ahci: reimplement port_map handling\n\nReimplement port_map handling such that\n\n1. Non-zero PORTS_IMPL value is always examined and used if consistent\n with cap.n_ports.\n\n2. When PI and cat.n_ports are inconsistent, honor cap.n_ports and\n force port_map to be ((1 \u003c\u003c cap.n_ports) - 1).\n\n3. There were two separate places dealing with port_map. Unify them\n to one.\n\nAs all newer ahci chips seem to get PI correct and older ones usually\nhave zero PI. Controllers with holes in PI are very unlikely to screw\nup PI, so #2 makes more sense than following inconsistent PI.\n\nWithout this change, not setting ATA_FLAG_HONOR_PI when it\u0027s needed\nresults in weird detection failure. This changed logic should be able\nto handle all known cases correctly automatically.\n\nVerified on ICH6 (reports 0 PI), ICH8 (with holes in port_map), ICH9,\nJMB360 and JMB363.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "cbcdd87593a1d85c5c4b259945a3a09eee12814d", "tree": "ee03df963a12ec7f30f6c3a8742421daf2c34f50", "parents": [ "e923090ddd9fef1d4e06dc6c5295e29baced19f3" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Sat Aug 18 13:14:55 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:37 2007 -0400" }, "message": "libata: implement and use ata_port_desc() to report port configuration\n\nCurrently, port configuration reporting has the following problems.\n\n* iomapped address is reported instead of raw address\n* report contains irrelevant fields or lacks necessary fields for\n non-SFF controllers.\n* host-\u003eirq/irq2 are there just for reporting and hacky.\n\nThis patch implements and uses ata_port_desc() and\nata_port_pbar_desc(). ata_port_desc() is almost identical to\nata_ehi_push_desc() except that it takes @ap instead of @ehi, has no\nlocking requirement, can only be used during host initialization and \"\n\" is used as separator instead of \", \". ata_port_pbar_desc() is a\nhelper to ease reporting of a PCI BAR or an offsetted address into it.\n\nLLD pushes whatever description it wants using the above two\nfunctions. The accumulated description is printed on host\nregistration after \"[S/P]ATA max MAX_XFERMODE \".\n\nSFF init helpers and ata_host_activate() automatically add\ndescriptions for addresses and irq respectively, so only LLDs which\nisn\u0027t standard SFF need to add custom descriptions. In many cases,\nsuch controllers need to report different things anyway.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "ac8869d56d95a8c74403e6f7a47d74fcfcc1b988", "tree": "2f812aff4c6e559f3c093f9933960d09631375c8", "parents": [ "7d73a363dea186a864f6295bbe842da8044d42cd" ], "author": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Thu Aug 16 03:17:03 2007 -0400" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:35 2007 -0400" }, "message": "[libata] Remove -\u003eport_disable() hook\n\nIt was always set to ata_port_disable(). Removed the hook, and replaced\nthe very few ap-\u003eops-\u003eport_disable() callsites with direct calls to\nata_port_disable().\n\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "6d32d30f55020d766388df7515f771f68c973033", "tree": "ec0efe48460b5b3f177fed2698ccd04b7964359b", "parents": [ "cb94c1cf5a6beffbd8935eb91227df0dd1987644" ], "author": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Wed Aug 15 05:38:46 2007 -0400" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:34 2007 -0400" }, "message": "[libata] Remove -\u003eirq_ack() hook, and ata_dummy_irq_on()\n\n* -\u003eirq_ack() is redundant to what the irq handler already\n performs... chk-status + irq-clear. Furthermore, it is only\n called in one place, when screaming-irq-debugging is enabled,\n so we don\u0027t want to bother with a hook just for that.\n\n* ata_dummy_irq_on() is only ever used in drivers that have\n no callpath reaching -\u003eirq_on(). Remove .irq_on hook from\n those drivers, and the now-unused ata_dummy_irq_on()\n\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "a738492501eaf6e266acc53a064552b3fcc706b2", "tree": "8d24a2504530bf175279c294cfcac669ade575c8", "parents": [ "2f2949680ad89d606db838340b17c30216c0bb0f" ], "author": { "name": "Kristen Carlson Accardi", "email": "kristen.c.accardi@intel.com", "time": "Thu Aug 09 14:23:41 2007 -0700" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:33 2007 -0400" }, "message": "ahci: Store interrupt value\n\nUse a stored value for which interrupts to enable. Changing this allows\nus to selectively turn off certain interrupts later and have them\nstay off.\n\nSigned-off-by: Kristen Carlson Accardi \u003ckristen.c.accardi@intel.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "2f2949680ad89d606db838340b17c30216c0bb0f", "tree": "25d7918c7b846d151776bbdf6a111a1d241d6b05", "parents": [ "9f45cbd3f0fc597530aaf85cad7fe52cd63f1fd8" ], "author": { "name": "Kristen Carlson Accardi", "email": "kristen.c.accardi@intel.com", "time": "Wed Aug 15 04:11:25 2007 -0400" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:33 2007 -0400" }, "message": "[libata] ahci: send event when AN received\n\nWhen we get an SDB FIS with the \u0027N\u0027 bit set, we should send\nan event to user space to indicate that there has been a\nmedia change. This will be done via the scsi device.\n\nSigned-off-by: Kristen Carlson Accardi \u003ckristen.c.accardi@intel.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "0c88758b5a6325428aaadab619886242db20ceae", "tree": "bf84abbce984fa45c4ce927b65695f30a8ea3a43", "parents": [ "0260731f0187840e272bfa10d3ba0f3e417976f5" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Aug 06 18:36:23 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:31 2007 -0400" }, "message": "libata-link: make two port flags HRST_TO_RESUME and SKIP_D2H_BSY link flags\n\nHRST_TO_RESUME and SKIP_D2H_BSY are link attributes. Move them to\nata_link-\u003eflags. This will allow host and PMP links to have different\nattributes. ata_port_info-\u003elink_flags is added and used by LLDs to\nspecify these flags during initialization.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "cc0680a580b5be81a1ca321b58f8e9b80b5c1052", "tree": "57454cdfdc9890f4e8d9f532e9cd240c7361951f", "parents": [ "955e57dfde4ff75e4d7329ac7a3d645b16015309" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Aug 06 18:36:23 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:31 2007 -0400" }, "message": "libata-link: linkify reset\n\nMake reset methods and related functions deal with ata_link instead of\nata_port.\n\n* ata_do_reset()\n* ata_eh_reset()\n* all prereset/reset/postreset methods and related functions\n\nThis patch introduces no behavior change.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "936fd7328657884d5a69a55666c74a55aa83ca27", "tree": "83a78a02d2c65ce835fe33882dfe5043d3240bff", "parents": [ "f58229f8060055b08b34008ea08f31de1e2f003c" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Aug 06 18:36:23 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:30 2007 -0400" }, "message": "libata-link: linkify PHY-related functions\n\nMake the following PHY-related functions to deal with ata_link instead\nof ata_port.\n\n* sata_print_link_status()\n* sata_down_spd_limit()\n* ata_set_sata_spd_limit() and friends\n* sata_link_debounce/resume()\n* sata_scr_valid/read/write/write_flush()\n* ata_link_on/offline()\n\nThis patch introduces no behavior change.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "9af5c9c97dc9d599281778864c72b385f0c63341", "tree": "8359986bd42c4a9a5b1993078aa9ee4c7971ac3d", "parents": [ "640fdb504941fa2b9f6f274716fc9f97f2bf6bff" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Aug 06 18:36:22 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:30 2007 -0400" }, "message": "libata-link: introduce ata_link\n\nIntroduce ata_link. It abstracts PHY and sits between ata_port and\nata_device. This new level of abstraction is necessary to support\nSATA Port Multiplier, which basically adds a bunch of links (PHYs) to\na ATA host port. Fields related to command execution, spd_limit and\nEH are per-link and thus moved to ata_link.\n\nThis patch only defines the host link. Multiple link handling will be\nadded later. Also, a lot of ap-\u003elink derefences are added but many of\nthem will be removed as each part is converted to deal directly with\nata_link instead of ata_port.\n\nThis patch introduces no behavior change.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nCc: James Bottomley \u003cJames.Bottomley@SteelEye.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "c69c0892d8dd68b01a9fced5cab8527f0698c15e", "tree": "dc8711b7893651d7157e64333f196841bf0bb89a", "parents": [ "e1cc9de8361f267101402a1181cff4d3d3225a6d" ], "author": { "name": "henry su", "email": "henry.su.ati@gmail.com", "time": "Thu Sep 20 16:07:33 2007 -0400" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Thu Sep 20 16:07:33 2007 -0400" }, "message": "[libata] ahci: add ATI SB800 PCI IDs\n\nATI/AMD SB800 shares some device IDs with SB700,\nand SB800 adds two more device IDs:0x4394,0x4395.\n\nSigned-off-by: henry su \u003chenry.su.ati@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "badc2341579511a247f5993865aa68379e283c5c", "tree": "bcdd50d27969b247d2cb459a3cfdbb686ef2e34d", "parents": [ "203ef6c456ad70e660cca67921d3d872b13aa516" ], "author": { "name": "su henry", "email": "henry.su.ati@gmail.com", "time": "Fri Jul 20 08:07:46 2007 -0400" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Jul 20 08:07:46 2007 -0400" }, "message": "The SATA controller device ID is different according to\nthe onchip SATA type set in the system BIOS:\nDevice Device ID\nSATA in IDE mode 0x4390\nSATA in AHCI mode 0x4391\nSATA in non-raid5 driver 0x4392\nSATA in raid5 driver 0x4393\n\nAlthough the device ID is different, they use the same AHCI driver\n.The attached file is the patch for adding these device\nIDs for ATI SB700.\n\nSigned-off-by: henry.su.ati@gmail.com\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "203ef6c456ad70e660cca67921d3d872b13aa516", "tree": "5dfcc194492f9a1d561966042c858ba705ad6786", "parents": [ "274c1fde5c775a53331427d454745b9ecc5c783b" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Jul 16 14:29:40 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Jul 20 08:02:11 2007 -0400" }, "message": "ahci: implement SCR_NOTIFICATION r/w\n\nMake ahci_scr_read/write() handle SCR_NOTIFICATION if the controller\nsupports it. Also, print \"sntf\" in the cap line if supported.\n\nWhile at it, convert eight space into a tab in ahci_print_info().\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "274c1fde5c775a53331427d454745b9ecc5c783b", "tree": "df39d94ac51195e25a04a7365ab88e2eb536d261", "parents": [ "da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9d" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Jul 16 14:29:40 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Jul 20 08:02:11 2007 -0400" }, "message": "ahci: make NO_NCQ handling more consistent\n\nahci_save_initial_config() is responsible for reading, screening the\nhost CAP register and storing the modified result into hpriv-\u003ecap for\nthe rest of the driver. Move ATA_FLAG_NO_NCQ handling into\nahci_save_initial_config(). It\u0027s more consistent this way and the\nrest of the driver can always refer to hpriv-\u003ecap to determine\nconfigured capability.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9d", "tree": "289239e1eb60168321e905c545aa2e2f3a2b5475", "parents": [ "5335b729064e03319cd2d5219770451dbb1d7f67" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Jul 16 14:29:40 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Jul 20 08:02:11 2007 -0400" }, "message": "libata: make -\u003escr_read/write callbacks return error code\n\nConvert -\u003escr_read/write callbacks to return error code to better\nindicate failure. This will help handling of SCR_NOTIFICATION.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "b64bbc39f2122a2276578e40144af69ef01decd4", "tree": "bd760da68bc785490ecd31060d892eeb7123782d", "parents": [ "975530e8a33fdeb1ad80d82fde11d56bf9ed2760" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Jul 16 14:29:39 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Jul 20 08:02:11 2007 -0400" }, "message": "libata: improve EH report formatting\n\nRequiring LLDs to format multiple error description messages properly\ndoesn\u0027t work too well. Help LLDs a bit by making ata_ehi_push_desc()\ninsert \", \" on each invocation. __ata_ehi_push_desc() is the raw\nversion without the automatic separator.\n\nWhile at it, make ehi_desc interface proper functions instead of\nmacros.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "a9cf5e858100b2f82ad61028c26a1a3de11c4839", "tree": "3edaf851bc132d6b8e7ea6cd09eb7ca80156bde0", "parents": [ "91c4a2e09267b0ddc8e59d121e3748cd18675739" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Jul 16 14:29:39 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Jul 20 08:02:10 2007 -0400" }, "message": "ahci: separate out ahci_do_softreset()\n\nSeparate out ahci_do_softreset() which takes @pmp as its last\nargument. This will be used to implement ahci_pmp_softreset().\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "91c4a2e09267b0ddc8e59d121e3748cd18675739", "tree": "6f4d6adfddaf88f60fd2c1c29ce1785fda52cc52", "parents": [ "d2e75dfffbe9e86e1d646264792ac9bcd2cc4267" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Jul 16 14:29:39 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Jul 20 08:02:10 2007 -0400" }, "message": "ahci: separate out ahci_exec_polled_cmd()\n\nSeparate out ahci_exec_polled_cmd() from ahci_softreset(). This will\nbe used to implement ahci_pmp_read/write(). ahci_exec_polled_cmd()\nperforms reset_engine before returning if the command fails (times\nout). This is to improve robustness.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "d2e75dfffbe9e86e1d646264792ac9bcd2cc4267", "tree": "be742ccdbefc5ddb0db031d9fd95717d7641b950", "parents": [ "2cbb79ebbd4be07041368da5379a64f89f8ad518" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Jul 16 14:29:39 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Jul 20 08:02:10 2007 -0400" }, "message": "ahci: separate out ahci_kick_engine()\n\nSeparate out stop_engine - CLO - start_engine sequence from\nahci_softreset() and ahci_clo() into ahci_reset_engine() and use it in\nahci_softreset() and ahci_post_internal_cmd(). The function will also\nbe used to prepare for and clean up after PMP register access\ncommands.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "2cbb79ebbd4be07041368da5379a64f89f8ad518", "tree": "239d63fca15c2c3abd9f9ef5130a43f6289d0ad1", "parents": [ "9977126c4b65c1396b665f7a0eeb8c7dede336f9" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Jul 16 14:29:38 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Jul 20 08:02:10 2007 -0400" }, "message": "ahci: use deadline instead of fixed timeout for 1st FIS for SRST\n\nUse deadline instead of fixed timeout for 1st FIS for SRST to improve\nrobustness of SRST.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "9977126c4b65c1396b665f7a0eeb8c7dede336f9", "tree": "91901f1356a57ba311bc5c95c4825504642f7d04", "parents": [ "fe36cb53cfd82f3c0796a0826e1c9caf198c8f97" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Jul 16 14:29:38 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Jul 20 08:02:10 2007 -0400" }, "message": "libata: add @is_cmd to ata_tf_to_fis()\n\nAdd @is_cmd to ata_tf_to_fis(). This controls bit 7 of the second\nbyte which tells the device whether this H2D FIS is for a command or\nnot. This cleans up ahci a bit and will be used by PMP.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "028a2596336b19a7e3713cfa9fe04d0d32e95876", "tree": "879f9f0127a7caff7857f38593a93d344b73763e", "parents": [ "3fb6589ceaf06d9c65bdf2382249d818771e913b" ], "author": { "name": "Alexey Dobriyan", "email": "adobriyan@gmail.com", "time": "Tue Jul 17 23:48:48 2007 +0400" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Jul 20 07:16:24 2007 -0400" }, "message": "ahci.c: fix CONFIG_PM\u003dn compilation\n\nCommit df69c9c5438b4e396a64d42608b2a6c48a3e7475 moved only prototype of\nout of CONFIG_PM. Move function out as well. Box seems to boot fine.\n\nSigned-off-by: Alexey Dobriyan \u003cadobriyan@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "cd70c26617f4686355263be4533ce8030242740e", "tree": "20313e5c0a996b5c95ce46ba8ed796271316ef28", "parents": [ "469248abf00dfa813356b372ffe153b85f27f4bf" ], "author": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Sun Jul 08 02:29:42 2007 -0400" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Mon Jul 09 12:17:35 2007 -0400" }, "message": "[libata] AHCI: Add support for Marvell AHCI-like chips (initially 6145)\n\nAdd support for the SATA portion of Marvell\u0027s AHCI-compatible chips.\nThe PATA port capability, also available via AHCI, is disabled until\nsupport is completed.\n\nNCQ and PCI MSI are disabled by default. Marvell says \"we use NCQ\" in\ntheir drivers but \"we do not use PCI MSI.\" Theoretically that implies\nwe need to fix ahci.c to work with Marvell NCQ, but one wonders why\nMarvell NCQ is any different from other AHCI chips.\n\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "469248abf00dfa813356b372ffe153b85f27f4bf", "tree": "61d81524195c35195abc68d8cc437c93bd5036bc", "parents": [ "d26fc9551a15fdad0d5de8376a78816b8af44f00" ], "author": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Sun Jul 08 01:13:16 2007 -0400" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Mon Jul 09 12:17:35 2007 -0400" }, "message": "[libata] Clean up driver udma_mask initializers\n\n* Use ATA_UDMA*\n* Remove FIXME notations that once served to remind us to verify\n that these were indeed the correct UDMA masks. They are.\n\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "dab632e8c483532bd84e1f3401c72612e39a7c40", "tree": "43d70da1e30389457ac3cfb4f7ded5e5429fb4cc", "parents": [ "ab2181cf390902f0371f30e4ebeb407b4aaa7314" ], "author": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Mon May 28 08:33:01 2007 -0400" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Mon Jul 09 12:17:34 2007 -0400" }, "message": "[libata] ahci: minor internal cleanups\n\nMinor cleanups, in preparation for merging Marvell PATA AHCI support in\nthe future.\n\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "df69c9c5438b4e396a64d42608b2a6c48a3e7475", "tree": "a96728fe0d1f2714b574c8319344c584895963d0", "parents": [ "2bcd866be55f8fe259ccac8eef2b8a7f7721b1d5" ], "author": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Sat May 26 20:46:51 2007 -0400" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Mon Jul 09 12:17:33 2007 -0400" }, "message": "[libata] ahci: minor internal cleanups\n\nFunction renaming and factorization.\n\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "2bcd866be55f8fe259ccac8eef2b8a7f7721b1d5", "tree": "de87ba6f172b49a9674bb13a73a24eb8634cd109", "parents": [ "79b0bde157e71071320e7a723c5a669cb2c822cf" ], "author": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Mon May 28 07:45:27 2007 -0400" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Mon Jul 09 12:17:33 2007 -0400" }, "message": "[libata] ahci: Factor out SATA port init into a separate function\n\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "be5d82183f1ebb022f923b008acf3b760d3a571d", "tree": "1520884587829c909d618695d6702e7d602447b3", "parents": [ "a16abc0b5ff3ef655e40cb5e6671d57f5dde513d" ], "author": { "name": "Jens Axboe", "email": "jens.axboe@oracle.com", "time": "Tue May 22 09:45:39 2007 +0200" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Mon Jul 09 12:17:32 2007 -0400" }, "message": "use_clustering (sht) bit set to 0 in AHCI ?\n\nahci: enable sg segment clustering\n\nThe specification states that ahci supports segments up to 4MiB in size,\nso enable clustering.\n\nSigned-off-by: Jens Axboe \u003cjens.axboe@oracle.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "a3d2cc5e742f82a87fdf9e2b730f41ff381c0a73", "tree": "96dd7ab5c98198e634b9323dc4d903c9bf8548eb", "parents": [ "3fae450c68d06b8890e1530bdd0910e938e7251d" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Tue Jun 19 18:52:56 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Wed Jun 20 19:56:21 2007 -0400" }, "message": "ahci: fix PORTS_IMPL override\n\nIf PORTS_IMPL register is zero, ahci initialize it to full mask\ncorresponding to nr_ports in the CAP register. hpriv-\u003ecap, which is\ninitialized at the end of the function, is incorrectly used as value\nof CAP causing ahci to always override PORTS_IMPL to 0x1 if it\u0027s zero.\nFix it.\n\nThis fixes a bug where early ich6 ahci can only access the first port.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "0522b2869d89b095bf417c8cc6fa404842e91903", "tree": "f093ef64e435674cc562a6b1e26343689563ded1", "parents": [ "afe3cc51ba4be6b25b721c40f178ea4157751161" ], "author": { "name": "Peer Chen", "email": "peerchen@gmail.com", "time": "Thu Jun 07 18:05:12 2007 +0800" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Sat Jun 09 22:40:28 2007 -0400" }, "message": "ahci: Add MCP73/MCP77 support to AHCI driver\n\nAdd the MCP73/MCP77 support to ahci driver.\n\nSigned-off-by: Peer Chen \u003cpeerchen@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "8bc3fc470eb25af4d70c72485cbcb130cc657691", "tree": "b79e0068f46cca29a547786e5ee2cdc739386cca", "parents": [ "a617c09f6d646b60f31efc8afd9f81b752bf21b7" ], "author": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Mon May 21 20:26:38 2007 -0400" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Mon May 21 20:26:38 2007 -0400" }, "message": "libata: bump versions\n\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "c7a42156d99bcea7f8173ba7a6034bbaa2ecb77c", "tree": "7d84ead0d69602cc900e30355ec84132800dea93", "parents": [ "55b637c6a003a8c4850b41a2c2fd6942d8a7f530" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Fri May 18 16:23:19 2007 +0200" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Mon May 21 20:00:25 2007 -0400" }, "message": "ahci: disable 64bit dma on sb600\n\nSB600 claims it can do 64bit DMA but it can\u0027t. Disable it.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "3cadbcc09891b8544203f211dac13f9cc4e6832a", "tree": "ac85dba0648f6e2be0d057b9afca926d97e24828", "parents": [ "6ddcd3b0201a7ad72294347636d2b4028ddbd95d" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Tue May 15 03:28:15 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Wed May 16 01:18:31 2007 -0400" }, "message": "libata-acpi: add ATA_FLAG_ACPI_SATA port flag\n\nWhether a controller needs IDE or SATA ACPI hierarchy is determined by\nthe programming interface of the controller not by whether the\ncontroller is SATA or PATA, or it supports slave device or not. This\npatch adds ATA_FLAG_ACPI_SATA port flags which tells libata-acpi that\nthe port needs SATA ACPI nodes, and sets the flag for ahci and\nsata_sil24.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" } ], "next": "2bcfdde6767f2f07891d2753c25220012fe5e6d2" }