)]}' { "log": [ { "commit": "d30492adea3a82e7120bcf60893aaaab711f90a6", "tree": "082d1dff4d71ccbd722b5edd47411acad110b636", "parents": [ "f1499382f114231cbd1e3dee7e656b50ce9d8236", "fd3fdaf09f26cd4f53fd4d7cdfe8e3dbb55a4dda" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue Jan 28 18:44:53 2014 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue Jan 28 18:44:53 2014 -0800" }, "message": "Merge tag \u0027clk-for-linus-3.14-part2\u0027 of git://git.linaro.org/people/mike.turquette/linux\n\nPull more clock framework changes from Mike Turquette:\n \"The second half of the clock framework pull requeust for 3.14 is\n dominated by platform support for Qualcomm\u0027s MSM SoCs, DT binding\n updates for TI\u0027s OMAP-ish processors and additional support for\n Samsung chips.\n\n Additionally there are other smaller clock driver changes and several\n last minute fixes. This pull request also includes the HiSilicon\n support that depends on the already-merged arm-soc pull request\"\n\n[ Fix up stupid compile error in the source tree with evil merge - Grumpy Linus ]\n\n* tag \u0027clk-for-linus-3.14-part2\u0027 of git://git.linaro.org/people/mike.turquette/linux: (49 commits)\n clk: sort Makefile\n clk: sunxi: fix overflow when setting up divided factors\n clk: Export more clk-provider functions\n dt-bindings: qcom: Fix warning with duplicate dt define\n clk: si5351: remove variant from platform_data\n clk: samsung: Remove unneeded semicolon\n clk: qcom: Fix modular build\n ARM: OMAP3: use DT clock init if DT data is available\n ARM: AM33xx: remove old clock data and link in new clock init code\n ARM: AM43xx: Enable clock init\n ARM: OMAP: DRA7: Enable clock init\n ARM: OMAP4: remove old clock data and link in new clock init code\n ARM: OMAP2+: io: use new clock init API\n ARM: OMAP2+: PRM: add support for initializing PRCM clock modules from DT\n ARM: OMAP3: hwmod: initialize clkdm from clkdm_name\n ARM: OMAP: hwmod: fix an incorrect clk type cast with _get_clkdm\n ARM: OMAP2+: clock: use driver API instead of direct memory read/write\n ARM: OMAP2+: clock: add support for indexed memmaps\n ARM: dts: am43xx clock data\n ARM: dts: AM35xx: use DT clock data\n ...\n" }, { "commit": "fd3fdaf09f26cd4f53fd4d7cdfe8e3dbb55a4dda", "tree": "b738663769b371cd494779c9e79d2e6e49d8bb76", "parents": [ "d1933689aa9ce2e07fe9e7e2ff77358f8bb11864" ], "author": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Mon Jan 27 13:04:49 2014 -0800" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Mon Jan 27 13:16:37 2014 -0800" }, "message": "clk: sort Makefile\n\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "d1933689aa9ce2e07fe9e7e2ff77358f8bb11864", "tree": "ec8199bbfd812cf7b144d6df6c8408a34c462c48", "parents": [ "0b7f04b868ec1230cf2dd698697dbc32a509ea4d" ], "author": { "name": "Emilio López", "email": "emilio@elopez.com.ar", "time": "Fri Jan 24 22:32:41 2014 -0300" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Mon Jan 27 12:28:23 2014 -0800" }, "message": "clk: sunxi: fix overflow when setting up divided factors\n\nCurrently, we are allocating space for two pointers, when we actually\nmay need to store three of them (two divisors plus the original clock).\nFix this, and change sizeof(type) to sizeof(*var) to keep checkpatch.pl\nhappy.\n\nReported-by: Dan Carpenter \u003cdan.carpenter@oracle.com\u003e\nSigned-off-by: Emilio López \u003cemilio@elopez.com.ar\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "0b7f04b868ec1230cf2dd698697dbc32a509ea4d", "tree": "30007a7d1486e85ed30a54f5511e6c3a090ae85c", "parents": [ "88d5fe037dad80bbaf64a5c6eccd9605fcedf2e0" ], "author": { "name": "Stephen Boyd", "email": "sboyd@codeaurora.org", "time": "Fri Jan 17 19:47:17 2014 -0800" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Mon Jan 27 11:43:19 2014 -0800" }, "message": "clk: Export more clk-provider functions\n\nAllow drivers to be compiled as modules by exporting more clock\nprovider functions.\n\nReported-by: kbuild test robot \u003cfengguang.wu@intel.com\u003e\nSigned-off-by: Stephen Boyd \u003csboyd@codeaurora.org\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "9d43dc7f403dbe5da25c7eb488a5975b08d95496", "tree": "ed6f88dedda06a1a6d25ebbf5c75eea0e0a6e692", "parents": [ "8e31d19b93377e2e6ad67bc2e898186327cb0308" ], "author": { "name": "Sebastian Hesselbarth", "email": "sebastian.hesselbarth@gmail.com", "time": "Sat Jan 25 21:48:31 2014 +0100" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Mon Jan 27 11:20:22 2014 -0800" }, "message": "clk: si5351: remove variant from platform_data\n\nCommit 9807362bfe1748d9bb48eecb9261f1b1aaafea1c\n \"clk: si5351: declare all device IDs for module loading\"\nremoved the common i2c_device_id and introduced new ones for each variant\nof the clock generator. Instead of exploiting that information in the driver,\nit still depends on platform_data passing the chips .variant.\n\nThis removes the now redundant .variant from the platform_data and puts it in\ni2c_device_id\u0027s .driver_data instead.\n\nSigned-off-by: Sebastian Hesselbarth \u003csebastian.hesselbarth@gmail.com\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "7e21774db5cc9cf8fe93a64a2f0c6cf47db8ab24", "tree": "460812792bc3b23789a83968b7bad840cc3eb047", "parents": [ "0ba3307a8ec35252f7b1e222e32889a6f3d9ceb3", "2e84d75116c17c2034e917b411250d2d11755435" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Jan 23 18:56:08 2014 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Jan 23 18:56:08 2014 -0800" }, "message": "Merge tag \u0027clk-for-linus-3.14-part1\u0027 of git://git.linaro.org/people/mike.turquette/linux\n\nPull clk framework changes from Mike Turquette:\n \"The first half of the clk framework pull request is made up almost\n entirely of new platform/driver support. There are some conversions\n of existing drivers to the common-clock Device Tree binding, and a few\n non-critical fixes to the framework.\n\n Due to an entirely unnecessary cyclical dependency with the arm-soc\n tree this pull request is broken into two pieces. The second piece\n will be sent out after arm-soc sends you the pull request that merged\n in core support for the HiSilicon 3620 platform. That same pull\n request from arm-soc depends on this pull request to merge in those\n HiSilicon bits without causing build failures\"\n\n[ Just did the ARM SoC merges, so getting ready for the second clk tree\n pull request - Linus ]\n\n* tag \u0027clk-for-linus-3.14-part1\u0027 of git://git.linaro.org/people/mike.turquette/linux: (97 commits)\n devicetree: bindings: Document qcom,mmcc\n devicetree: bindings: Document qcom,gcc\n clk: qcom: Add support for MSM8660\u0027s global clock controller (GCC)\n clk: qcom: Add support for MSM8974\u0027s multimedia clock controller (MMCC)\n clk: qcom: Add support for MSM8974\u0027s global clock controller (GCC)\n clk: qcom: Add support for MSM8960\u0027s multimedia clock controller (MMCC)\n clk: qcom: Add support for MSM8960\u0027s global clock controller (GCC)\n clk: qcom: Add reset controller support\n clk: qcom: Add support for branches/gate clocks\n clk: qcom: Add support for root clock generators (RCGs)\n clk: qcom: Add support for phase locked loops (PLLs)\n clk: qcom: Add a regmap type clock struct\n clk: Add set_rate_and_parent() op\n reset: Silence warning in reset-controller.h\n clk: sirf: re-arch to make the codes support both prima2 and atlas6\n clk: composite: pass mux_hw into determine_rate\n clk: shmobile: Fix MSTP clock array initialization\n clk: shmobile: Fix MSTP clock index\n ARM: dts: Add clock provider specific properties to max77686 node\n clk: max77686: Register OF clock provider\n ...\n" }, { "commit": "0ba3307a8ec35252f7b1e222e32889a6f3d9ceb3", "tree": "26126ed7a2080a706f0488c215549fc9f5f76a59", "parents": [ "903a9f77d1d00c8621bc37afd959ac45a4b3ebec", "cd2f43a1f7400a74a084094502f70df2e169c6e8" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Jan 23 18:49:36 2014 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Jan 23 18:49:36 2014 -0800" }, "message": "Merge tag \u0027drivers-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc\n\nPull ARM driver updates from Olof Johansson:\n \"Updates of SoC-near drivers and other driver updates that makes more\n sense to take through our tree.\n\n The largest part of this is a conversion of device registration for\n some renesas shmobile/sh devices over to use resources. This has\n required coordination with the corresponding arch/sh changes, and\n we\u0027ve agreed to merge the arch/sh changes through our tree.\n\n Added in this branch is support for Trusted Foundations secure\n firmware, which is what is used on many of the commercial Nvidia Tegra\n products that are in the market, including the Nvidia Shield. The\n code is local to arch/arm at this time since it\u0027s uncertain whether it\n will be shared with arm64 longer-term, if needed we will refactor\n later.\n\n A couple of new RTC drivers used on ARM boards, merged through our\n tree on request by the RTC maintainer.\n\n ... plus a bunch of smaller updates across the board, gpio conversions\n for davinci, etc\"\n\n* tag \u0027drivers-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (45 commits)\n watchdog: davinci: rename platform driver to davinci-wdt\n tty: serial: Limit msm_serial_hs driver to platforms that use it\n mmc: msm_sdcc: Limit driver to platforms that use it\n usb: phy: msm: Move mach dependent code to platform data\n clk: versatile: fixup IM-PD1 clock implementation\n clk: versatile: pass a name to ICST clock provider\n ARM: integrator: pass parent IRQ to the SIC\n irqchip: versatile FPGA: support cascaded interrupts from DT\n gpio: davinci: don\u0027t create irq_domain in case of unbanked irqs\n gpio: davinci: use chained_irq_enter/chained_irq_exit API\n gpio: davinci: add OF support\n gpio: davinci: remove unused variable intc_irq_num\n gpio: davinci: convert to use irqdomain support.\n gpio: introduce GPIO_DAVINCI kconfig option\n gpio: davinci: get rid of DAVINCI_N_GPIO\n gpio: davinci: use {readl|writel}_relaxed() instead of __raw_*\n serial: sh-sci: Add OF support\n serial: sh-sci: Add device tree bindings documentation\n serial: sh-sci: Remove platform data mapbase and irqs fields\n serial: sh-sci: Remove platform data scbrr_algo_id field\n ...\n" }, { "commit": "9b6d351a75dae25430383b29a3764ae7921f6c47", "tree": "605b1ec9f90138553cb7efedf9dbb3df93bef3a8", "parents": [ "dfd10e7ae60c6c1b24b5d601744b4fd1ecab2f31", "310c85476d5047f5ace4d1c527e1bbbc0c7ad672" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Jan 23 18:45:38 2014 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Jan 23 18:45:38 2014 -0800" }, "message": "Merge tag \u0027dt-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc\n\nPull ARM SoC DT updates from Olof Johansson:\n \"DT and DT-conversion-related changes for various ARM platforms. Most\n of these are to enable various devices on various boards, etc, and not\n necessarily worth enumerating.\n\n New boards and systems continue to come in as new devicetree files\n that don\u0027t require corresponding C changes any more, which is\n indicating that the system is starting to work fairly well.\n\n A few things worth pointing out:\n\n * ST Ericsson ux500 platforms have made the major push to move over\n to fully support the platform with DT\n * Renesas platforms continue their conversion over from legacy\n platform devices to DT-based for hardware description\"\n\n* tag \u0027dt-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (327 commits)\n ARM: dts: SiRF: add pin group for USP0 with only RX or TX frame sync\n ARM: dts: SiRF: add lost usp1_uart_nostreamctrl pin group for atlas6\n ARM: dts: sirf: add lost minigpsrtc device node\n ARM: dts: sirf: add clock, frequence-voltage table for CPU0\n ARM: dts: sirf: add lost bus_width, clock and status for sdhci\n ARM: dts: sirf: add lost clocks for cphifbg\n ARM: dts: socfpga: add pl330 clock\n ARM: dts: socfpga: update L2 tag and data latency\n arm: sun7i: cubietruck: Enable the i2c controllers\n ARM: dts: add support for EXYNOS4412 based TINY4412 board\n ARM: dts: Add initial support for Arndale Octa board\n ARM: bcm2835: add USB controller to device tree\n ARM: dts: MSM8974: Add MMIO architected timer node\n ARM: dts: MSM8974: Add restart node\n ARM: dts: sun7i: external clock outputs\n ARM: dts: sun7i: Change 32768 Hz oscillator node name to clk@N style\n ARM: dts: sun7i: Add pin muxing options for clock outputs\n ARM: dts: sun7i: Add rtp controller node\n ARM: dts: sun5i: Add rtp controller node\n ARM: dts: sun4i: Add rtp controller node\n ...\n" }, { "commit": "f2c73464d7b399cf4e0c601c1c7d7b079080fa52", "tree": "902decd0c280757075bce5068fee679e0ccc261e", "parents": [ "93abdb7785503c269e73e811f3c7fd23a9243b14", "273c2279ca502267fac40bcaecb35942380c429c" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Jan 23 18:36:55 2014 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Jan 23 18:36:55 2014 -0800" }, "message": "Merge tag \u0027cleanup-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc\n\nPull ARM SoC cleanups from Olof Johansson:\n \"This is the branch where we usually queue up cleanup efforts, moving\n drivers out of the architecture directory, header file restructuring,\n etc. Sometimes they tangle with new development so it\u0027s hard to keep\n it strictly to cleanups.\n\n Some of the things included in this branch are:\n\n * Atmel SAMA5 conversion to common clock\n * Reset framework conversion for tegra platforms\n - Some of this depends on tegra clock driver reworks that are shared\n with Mike Turquette\u0027s clk tree.\n * Tegra DMA refactoring, which are shared branches with the DMA tree.\n * Removal of some header files on exynos to prepare for\n multiplatform\"\n\n* tag \u0027cleanup-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (169 commits)\n ARM: mvebu: move Armada 370/XP specific definitions to armada-370-xp.h\n ARM: mvebu: remove prototypes of non-existing functions from common.h\n ARM: mvebu: move ARMADA_XP_MAX_CPUS to armada-370-xp.h\n serial: sh-sci: Rework baud rate calculation\n serial: sh-sci: Compute overrun_bit without using baud rate algo\n serial: sh-sci: Remove unused GPIO request code\n serial: sh-sci: Move overrun_bit and error_mask fields out of pdata\n serial: sh-sci: Support resources passed through platform resources\n serial: sh-sci: Don\u0027t check IRQ in verify port operation\n serial: sh-sci: Set the UPF_FIXED_PORT flag\n serial: sh-sci: Remove duplicate interrupt check in verify port op\n serial: sh-sci: Simplify baud rate calculation algorithms\n serial: sh-sci: Remove baud rate calculation algorithm 5\n serial: sh-sci: Sort headers alphabetically\n ARM: EXYNOS: Kill exynos_pm_late_initcall()\n ARM: EXYNOS: Consolidate selection of PM_GENERIC_DOMAINS for Exynos4\n ARM: at91: switch Calao QIL-A9260 board to DT\n clk: at91: fix pmc_clk_ids data type attriubte\n PM / devfreq: use inclusion \u003cmach/map.h\u003e instead of \u003cplat/map-s5p.h\u003e\n ARM: EXYNOS: remove \u003cmach/regs-clock.h\u003e for exynos\n ...\n" }, { "commit": "93abdb7785503c269e73e811f3c7fd23a9243b14", "tree": "2ec2630824a9b75c8658b1e275e2032541652e63", "parents": [ "f341535193c338b4ce4af8e32be51e6aae7f22a6", "099c2e9ef671519d4c7f9d49782845adc4f54a39" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Jan 23 18:36:01 2014 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Jan 23 18:36:01 2014 -0800" }, "message": "Merge tag \u0027fixes-nc-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc\n\nPull ARM SoC non-critical fixes from Olof Johansson:\n \"As usual, we have a batch of fixes that weren\u0027t considered significant\n enough to warrant going into the later -rcs for previous release, so\n they are queued up on this branch.\n\n A handful of these are for various DT fixups for Samsung platforms,\n and a handful of other minor things.\n\n There are also a couple of stable-marked patches for mvebu -- they\n came in quite late and we decided to keep them deferred until the\n first -stable release to get more coverage instead of squeezing them\n into 3.13\"\n\n* tag \u0027fixes-nc-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (32 commits)\n ARM: at91: smc: bug fix in sam9_smc_cs_read()\n i2c: mv64xxx: Document the newly introduced Armada XP A0 compatible\n i2c: mv64xxx: Fix bus hang on A0 version of the Armada XP SoCs\n ARM: mvebu: Add quirk for i2c for the OpenBlocks AX3-4 board\n ARM: mvebu: Add support to get the ID and the revision of a SoC\n ARM: dts: msm: Fix gpio interrupt and reg length\n irqchip: sirf: set IRQ_LEVEL status_flags\n ARM: OMAP2+: gpmc: Move legacy GPMC width setting\n ARM: OMAP2+: gpmc: Introduce gpmc_set_legacy()\n ARM: OMAP2+: gpmc: Move initialization outside the gpmc_t condition\n ARM: OMAP2+: board-generic: update SoC compatibility strings\n Documentation: dt: OMAP: explicitly state SoC compatible strings\n ARM: OMAP2+: enable AM33xx SOC EVM audio\n ARM: OMAP2+: Select USB PHY for AM335x SoC\n ARM: bcm2835: Fix grammar in help message\n ARM: msm: trout: fix uninit var warning\n ARM: dts: Use MSHC controller for eMMC memory for exynos4412-trats2\n ARM: dts: Fix definition of MSHC device tree nodes for exynos4x12\n ARM: dts: add clock provider for mshc node for Exynos4412 SOC\n clk: samsung: exynos4: Fix definition of div_mmc_pre4 divider\n ...\n" }, { "commit": "258753361534a40ad7180c742da813fc659e427b", "tree": "58517f6ce46ab2c897d427b7d1bf29850be314fa", "parents": [ "315fba80a664e4bd928e0b85a38d26e60645b96a", "2aff4c9ce898b9079658650c1ab33c44b100a203" ], "author": { "name": "Takashi Iwai", "email": "tiwai@suse.de", "time": "Mon Jan 20 10:20:14 2014 +0100" }, "committer": { "name": "Takashi Iwai", "email": "tiwai@suse.de", "time": "Mon Jan 20 10:20:14 2014 +0100" }, "message": "Merge branch \u0027for-next\u0027 into for-linus\n" }, { "commit": "8e31d19b93377e2e6ad67bc2e898186327cb0308", "tree": "d6925591bc5f4ed567e53b705cd27d7c06606385", "parents": [ "051c8d0b667400b00dc0e53c3cf61ad6991bfefb" ], "author": { "name": "Sachin Kamat", "email": "sachin.kamat@linaro.org", "time": "Fri Jan 17 17:05:52 2014 +0530" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Fri Jan 17 15:00:25 2014 -0800" }, "message": "clk: samsung: Remove unneeded semicolon\n\nSemicolon not needed after switch statement.\n\nSigned-off-by: Sachin Kamat \u003csachin.kamat@linaro.org\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "051c8d0b667400b00dc0e53c3cf61ad6991bfefb", "tree": "eb7769313f2b5e44e21cf5403d31fe9e0956f4d9", "parents": [ "3e049157911ad0126b6e21460251f84fb38aad63" ], "author": { "name": "Stephen Boyd", "email": "sboyd@codeaurora.org", "time": "Fri Jan 17 12:09:40 2014 -0800" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Fri Jan 17 13:39:42 2014 -0800" }, "message": "clk: qcom: Fix modular build\n\nAccording to Documentation/kbuild/makefiles.txt these symbols\nshould be clk-qcom-y. Otherwise the build will fail if\nCONFIG_COMMON_CLK_QCOM\u003dm. Fix it.\n\nReported-by: kbuild test robot \u003cfengguang.wu@intel.com\u003e\nSigned-off-by: Stephen Boyd \u003csboyd@codeaurora.org\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "ffab239956613be7b81d00999128fd05fd096762", "tree": "40fc65d7b253b18ed5a23e13d03ca418789fa194", "parents": [ "aafd900cab87d339dc3004c241eebc854005124b" ], "author": { "name": "Tero Kristo", "email": "t-kristo@ti.com", "time": "Fri Sep 20 17:02:40 2013 +0300" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Fri Jan 17 12:35:52 2014 -0800" }, "message": "CLK: TI: add am43xx clock init file\n\nclk-43xx.c now contains the clock init functionality for am43xx, including\nDT clock registration and adding of static clkdev entries.\n\nSigned-off-by: Tero Kristo \u003ct-kristo@ti.com\u003e\nTested-by: Nishanth Menon \u003cnm@ti.com\u003e\nAcked-by: Tony Lindgren \u003ctony@atomide.com\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "aafd900cab87d339dc3004c241eebc854005124b", "tree": "3651529963ae709cc9c22ee709a6a238a587aca4", "parents": [ "24582b3407775d57f06becfccd8cd202bc01eda6" ], "author": { "name": "Tero Kristo", "email": "t-kristo@ti.com", "time": "Fri Aug 02 14:04:19 2013 +0300" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Fri Jan 17 12:35:48 2014 -0800" }, "message": "CLK: TI: add omap3 clock init file\n\nclk-3xxx.c now contains the clock init functionality for omap3, including\nDT clock registration and adding of static clkdev entries.\n\nSigned-off-by: Tero Kristo \u003ct-kristo@ti.com\u003e\nTested-by: Nishanth Menon \u003cnm@ti.com\u003e\nAcked-by: Tony Lindgren \u003ctony@atomide.com\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "24582b3407775d57f06becfccd8cd202bc01eda6", "tree": "d365fb760c6433fcc2dcc6a3dd0c53078445ad58", "parents": [ "45622e2162b6d5907006f4595f2ac862afe1dfb5" ], "author": { "name": "Tero Kristo", "email": "t-kristo@ti.com", "time": "Mon Jul 15 13:14:20 2013 +0300" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Fri Jan 17 12:35:45 2014 -0800" }, "message": "CLK: TI: add interface clock support for OMAP3\n\nOMAP3 has interface clocks in addition to functional clocks, which\nrequire special handling for the autoidle and idle status register\noffsets mainly.\n\nSigned-off-by: Tero Kristo \u003ct-kristo@ti.com\u003e\nAcked-by: Tony Lindgren \u003ctony@atomide.com\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "45622e2162b6d5907006f4595f2ac862afe1dfb5", "tree": "93b492bc3c97404b7cd4f798440cf088e72425e9", "parents": [ "251a449dd3290d5af35da1113e155a37bf8b3ece" ], "author": { "name": "Tero Kristo", "email": "t-kristo@ti.com", "time": "Fri Jul 19 11:36:01 2013 +0300" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Fri Jan 17 12:35:41 2014 -0800" }, "message": "CLK: TI: add am33xx clock init file\n\nclk-33xx.c now contains the clock init functionality for am33xx, including\nDT clock registration and adding of static clkdev entries.\n\nThis patch also moves the omap2_clk_enable_init_clocks declaration to\nthe driver include, as this is needed by the am33xx clock init code.\n\nSigned-off-by: Tero Kristo \u003ct-kristo@ti.com\u003e\nTested-by: Nishanth Menon \u003cnm@ti.com\u003e\nAcked-by: Tony Lindgren \u003ctony@atomide.com\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "251a449dd3290d5af35da1113e155a37bf8b3ece", "tree": "4af5e1393c3ba48aae9043512d40fa46050c54c5", "parents": [ "3cf467a9969db8297dcf783c5b09b0df8fda863b" ], "author": { "name": "Tero Kristo", "email": "t-kristo@ti.com", "time": "Thu Jul 18 17:41:00 2013 +0300" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Fri Jan 17 12:35:37 2014 -0800" }, "message": "CLK: TI: add dra7 clock init file\n\nclk-7xx.c now contains the clock init functionality for dra7, including\nDT clock registration and adding of static clkdev entries.\n\nSigned-off-by: Tero Kristo \u003ct-kristo@ti.com\u003e\nTested-by: Nishanth Menon \u003cnm@ti.com\u003e\nAcked-by: Tony Lindgren \u003ctony@atomide.com\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "3cf467a9969db8297dcf783c5b09b0df8fda863b", "tree": "bc17da1cc3f192ade4e939e0ae1193a9a66a0bb0", "parents": [ "62125a46cd717ad8fa6a64d260d46a0a108e6222" ], "author": { "name": "J Keerthy", "email": "j-keerthy@ti.com", "time": "Tue Jul 23 12:05:37 2013 +0530" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Fri Jan 17 12:35:31 2014 -0800" }, "message": "CLK: TI: DRA7: Add APLL support\n\nThe patch adds support for DRA7 PCIe APLL. The APLL\nsources the optional functional clocks for PCIe module.\n\nAPLL stands for Analog PLL. This is different when comapred\nwith DPLL meaning Digital PLL, the phase detection is done\nusing an analog circuit.\n\nSigned-off-by: J Keerthy \u003cj-keerthy@ti.com\u003e\nSigned-off-by: Tero Kristo \u003ct-kristo@ti.com\u003e\nAcked-by: Tony Lindgren \u003ctony@atomide.com\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "62125a46cd717ad8fa6a64d260d46a0a108e6222", "tree": "d77f91368cf32c9b3c54c84e400284e546bb6b06", "parents": [ "52b14728dd890f8a62bffce8dfece496434c2b41" ], "author": { "name": "Roger Quadros", "email": "rogerq@ti.com", "time": "Wed Jul 24 16:30:55 2013 +0300" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Fri Jan 17 12:35:27 2014 -0800" }, "message": "CLK: TI: omap5: Initialize USB_DPLL at boot\n\nUSB_DPLL must be initialized and locked at boot so that\nUSB modules can work.\n\nSigned-off-by: Roger Quadros \u003crogerq@ti.com\u003e\nSigned-off-by: Tero Kristo \u003ct-kristo@ti.com\u003e\nTested-by: Nishanth Menon \u003cnm@ti.com\u003e\nAcked-by: Tony Lindgren \u003ctony@atomide.com\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "52b14728dd890f8a62bffce8dfece496434c2b41", "tree": "b882891304c13e60902443d03d454bca337fa3d3", "parents": [ "21876ea566fedadd56453af5a1a91eb667c25422" ], "author": { "name": "Tero Kristo", "email": "t-kristo@ti.com", "time": "Thu Jul 18 17:15:51 2013 +0300" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Fri Jan 17 12:35:24 2014 -0800" }, "message": "CLK: TI: add omap5 clock init file\n\nclk-54xx.c now contains the clock init functionality for omap5, including\nDT clock registration and adding of static clkdev entries.\n\nSigned-off-by: Tero Kristo \u003ct-kristo@ti.com\u003e\nTested-by: Nishanth Menon \u003cnm@ti.com\u003e\nAcked-by: Tony Lindgren \u003ctony@atomide.com\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "21876ea566fedadd56453af5a1a91eb667c25422", "tree": "6f6d03d5923100c86a9c3cd908845bc888f54942", "parents": [ "6a369c584fbe98264458b9442e780f8078f2f7ad" ], "author": { "name": "Tero Kristo", "email": "t-kristo@ti.com", "time": "Thu Jul 18 15:57:51 2013 +0300" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Fri Jan 17 12:35:20 2014 -0800" }, "message": "CLK: TI: add omap4 clock init file\n\nclk-44xx.c now contains the clock init functionality for omap4, including\nDT clock registration and adding of static clkdev entries.\n\nSigned-off-by: Tero Kristo \u003ct-kristo@ti.com\u003e\nTested-by: Nishanth Menon \u003cnm@ti.com\u003e\nAcked-by: Tony Lindgren \u003ctony@atomide.com\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "6a369c584fbe98264458b9442e780f8078f2f7ad", "tree": "d80be958f33b501a128599a0e31bec400b51fa58", "parents": [ "3cd4a596224565cff00b69a02d4b5fa7432ea6d3" ], "author": { "name": "Tero Kristo", "email": "t-kristo@ti.com", "time": "Fri Sep 13 20:22:27 2013 +0300" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Fri Jan 17 12:35:17 2014 -0800" }, "message": "clk: ti: add support for basic mux clock\n\nti,mux-clock provides now a binding for basic mux support. This is just\nusing the basic clock type.\n\nSigned-off-by: Tero Kristo \u003ct-kristo@ti.com\u003e\nAcked-by: Tony Lindgren \u003ctony@atomide.com\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "3cd4a596224565cff00b69a02d4b5fa7432ea6d3", "tree": "66ec0ab2c879ccb9715f335af51897376148b2a6", "parents": [ "f60b1ea5ea7ab1aee34a5ba55520b84b6e6d482e" ], "author": { "name": "Tero Kristo", "email": "t-kristo@ti.com", "time": "Wed Aug 21 19:39:15 2013 +0300" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Fri Jan 17 12:35:13 2014 -0800" }, "message": "CLK: TI: add support for clockdomain binding\n\nSome OMAP clocks require knowledge about their parent clockdomain for\nbook keeping purposes. This patch creates a new DT binding for TI\nclockdomains, which act as a collection of device clocks. Clockdomain\nitself is rather misleading name for the hardware functionality, as at\nleast on OMAP4 / OMAP5 / DRA7 the clockdomains can be collections of either\nclocks and/or IP blocks, thus idle-domain or such might be more appropriate.\nFor most cases on these SoCs, the kernel doesn\u0027t even need the information\nand the mappings can be ignored.\n\nSigned-off-by: Tero Kristo \u003ct-kristo@ti.com\u003e\nAcked-by: Tony Lindgren \u003ctony@atomide.com\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "f60b1ea5ea7ab1aee34a5ba55520b84b6e6d482e", "tree": "f7afada378e4ebac7fb02cd05adb653b4fec760d", "parents": [ "1f847c65fd569c1d822800ba3e7e18c6411a7d50" ], "author": { "name": "Tero Kristo", "email": "t-kristo@ti.com", "time": "Tue Jun 18 18:55:59 2013 +0300" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Fri Jan 17 12:35:10 2014 -0800" }, "message": "CLK: TI: add support for gate clock\n\nThis patch adds support for TI specific gate clocks. These behave as basic\ngate-clock, but have different ops / hw-ops for controlling the actual\ngate, for example waiting until the clock is ready. Several sub-types\nare supported:\n- ti,gate-clock: basic gate clock with default ops/hwops\n- ti,clkdm-gate-clock: clockdomain level gate control\n- ti,dss-gate-clock: gate clock with DSS specific hardware handling\n- ti,am35xx-gate-clock: gate clock with AM35xx specific hardware handling\n- ti,hsdiv-gate-clock: gate clock with OMAP36xx hardware errata handling\n\nSigned-off-by: Tero Kristo \u003ct-kristo@ti.com\u003e\nAcked-by: Tony Lindgren \u003ctony@atomide.com\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "1f847c65fd569c1d822800ba3e7e18c6411a7d50", "tree": "b735f09c69ac53da98cd4ffe8bb32a53abca573d", "parents": [ "b4761198bfaf29649dc58a48e8b123ea4174ba95" ], "author": { "name": "Tero Kristo", "email": "t-kristo@ti.com", "time": "Fri Sep 13 14:57:59 2013 +0300" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Fri Jan 17 12:35:07 2014 -0800" }, "message": "clk: ti: add support for TI fixed factor clock\n\nThis behaves exactly in similar manner to basic fixed-factor-clock, but\nadds a few properties on top for handling clock hardware autoidling.\n\nSigned-off-by: Tero Kristo \u003ct-kristo@ti.com\u003e\nAcked-by: Tony Lindgren \u003ctony@atomide.com\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "b4761198bfaf29649dc58a48e8b123ea4174ba95", "tree": "7c350ec98d991e2e6035a6e0098002d28ea3223c", "parents": [ "975e15487d5abfd5f33fea9c1ba0b987604f0d0f" ], "author": { "name": "Tero Kristo", "email": "t-kristo@ti.com", "time": "Fri Sep 13 12:02:15 2013 +0300" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Fri Jan 17 12:35:04 2014 -0800" }, "message": "CLK: ti: add support for ti divider-clock\n\nThis patch adds support for TI divider clock binding, which simply uses\nthe basic clock divider to provide the features needed.\n\nSigned-off-by: Tero Kristo \u003ct-kristo@ti.com\u003e\nAcked-by: Tony Lindgren \u003ctony@atomide.com\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "975e15487d5abfd5f33fea9c1ba0b987604f0d0f", "tree": "6578c984956a1ed41077669c9eb88696be2f616c", "parents": [ "b1a07b478b63f0a8f971b3a82ce34a67a9324547" ], "author": { "name": "Tero Kristo", "email": "t-kristo@ti.com", "time": "Mon Sep 09 15:46:45 2013 +0300" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Fri Jan 17 12:35:01 2014 -0800" }, "message": "clk: ti: add composite clock support\n\nThis is a multipurpose clock node, which contains support for multiple\nsub-clocks. Uses basic composite clock type to implement the actual\nfunctionality, and TI specific gate, mux and divider clocks.\n\nSigned-off-by: Tero Kristo \u003ct-kristo@ti.com\u003e\nAcked-by: Tony Lindgren \u003ctony@atomide.com\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "b1a07b478b63f0a8f971b3a82ce34a67a9324547", "tree": "dc5d86884961efff9caaa25c277eac3b0d3c58df", "parents": [ "f38b0dd63f0d0cca753bf0997eefdfb23dcc9518" ], "author": { "name": "Tero Kristo", "email": "t-kristo@ti.com", "time": "Tue Jun 18 16:27:57 2013 +0300" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Fri Jan 17 12:34:59 2014 -0800" }, "message": "CLK: TI: add autoidle support\n\nTI clk driver now routes some of the basic clocks through own\nregistration routine to allow autoidle support. This routine just\nchecks a couple of device node properties and adds autoidle support\nif required, and just passes the registration forward to basic clocks.\n\nSigned-off-by: Tero Kristo \u003ct-kristo@ti.com\u003e\nAcked-by: Tony Lindgren \u003ctony@atomide.com\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "f38b0dd63f0d0cca753bf0997eefdfb23dcc9518", "tree": "9945b442a5015de45cefcf9d3d91bcd8c2a28016", "parents": [ "819b4861c18d602463cfe815041d11fd81002654" ], "author": { "name": "Tero Kristo", "email": "t-kristo@ti.com", "time": "Wed Jun 12 16:04:34 2013 +0300" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Fri Jan 17 12:34:55 2014 -0800" }, "message": "CLK: TI: Add DPLL clock support\n\nThe OMAP clock driver now supports DPLL clock type. This patch also\nadds support for DT DPLL nodes.\n\nSigned-off-by: Tero Kristo \u003ct-kristo@ti.com\u003e\nAcked-by: Tony Lindgren \u003ctony@atomide.com\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "819b4861c18d602463cfe815041d11fd81002654", "tree": "b9b83374a962896f3d3903dc16345a9dfa53ecca", "parents": [ "a8aceccb4d5db0acb476b74051525fb26f57f8ae" ], "author": { "name": "Tero Kristo", "email": "t-kristo@ti.com", "time": "Tue Oct 22 11:39:36 2013 +0300" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Fri Jan 17 12:34:52 2014 -0800" }, "message": "CLK: ti: add init support for clock IP blocks\n\nti_dt_clk_init_provider() can now be used to initialize the contents of\na single clock IP block. This parses all the clocks under the IP block\nand calls the corresponding init function for them.\n\nThis patch also introduces a helper function for the TI clock drivers\nto get register info from DT and append the master IP info to this.\n\nSigned-off-by: Tero Kristo \u003ct-kristo@ti.com\u003e\nAcked-by: Tony Lindgren \u003ctony@atomide.com\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "a8aceccb4d5db0acb476b74051525fb26f57f8ae", "tree": "1ea3c1b912f065fab116417d750d208de1973454", "parents": [ "68b9f608679424ea08e6fbead5dc82599bfe667f" ], "author": { "name": "Tero Kristo", "email": "t-kristo@ti.com", "time": "Thu Jul 18 11:52:33 2013 +0300" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Fri Jan 17 12:32:38 2014 -0800" }, "message": "CLK: TI: add DT alias clock registration mechanism\n\nSome devices require their clocks to be available with a specific\ndev-id con-id mapping. With DT, the clocks can be found by default\nonly with their name, or alternatively through the device node of\nthe consumer. With drivers, that don\u0027t support DT fully yet, add\nmechanism to register specific clock names.\n\nSigned-off-by: Tero Kristo \u003ct-kristo@ti.com\u003e\nAcked-by: Tony Lindgren \u003ctony@atomide.com\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "0099d8851681a550065e36fe89719616ab5f63d4", "tree": "8881a7064ff68cc97c71abd4b5bd1a67de314871", "parents": [ "d6e0a2dd12f4067a5bcefb8bbd8ddbeff800afbc", "2e84d75116c17c2034e917b411250d2d11755435" ], "author": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Thu Jan 16 13:13:46 2014 -0800" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Thu Jan 16 13:13:46 2014 -0800" }, "message": "Merge remote-tracking branch \u0027linaro/clk-next\u0027 into clk-next\n" }, { "commit": "0eeff27b49b78979bb4d37d1ff8dda6751fa0ad8", "tree": "9a8c07ca3144228c9efb74b9d20413b18f8b6e6b", "parents": [ "d8b212014e69d6b6323773ce6898f224ef4ed0d6" ], "author": { "name": "Stephen Boyd", "email": "sboyd@codeaurora.org", "time": "Wed Jan 15 10:47:32 2014 -0800" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Thu Jan 16 12:01:05 2014 -0800" }, "message": "clk: qcom: Add support for MSM8660\u0027s global clock controller (GCC)\n\nAdd a driver for the global clock controller found on MSM8660\nbased platforms. This should allow most non-multimedia device\ndrivers to probe and control their clocks.\n\nSigned-off-by: Stephen Boyd \u003csboyd@codeaurora.org\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "d8b212014e69d6b6323773ce6898f224ef4ed0d6", "tree": "8f8304d17e8880b4c6cb6ed77ae08090212d258b", "parents": [ "d33faa9ead8da261e75815b74b41ac7ff265da9a" ], "author": { "name": "Stephen Boyd", "email": "sboyd@codeaurora.org", "time": "Wed Jan 15 10:47:31 2014 -0800" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Thu Jan 16 12:01:05 2014 -0800" }, "message": "clk: qcom: Add support for MSM8974\u0027s multimedia clock controller (MMCC)\n\nAdd a driver for the global clock controller found on MSM 8974\nbased platforms. This should allow most multimedia device drivers\nto probe and control their clocks.\n\nSigned-off-by: Stephen Boyd \u003csboyd@codeaurora.org\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "d33faa9ead8da261e75815b74b41ac7ff265da9a", "tree": "da3941b0bf6c55f19dd6fd250a169342b711bab7", "parents": [ "6d00b56fe8c6f10076c9477e1cce99caf4568760" ], "author": { "name": "Stephen Boyd", "email": "sboyd@codeaurora.org", "time": "Wed Jan 15 10:47:30 2014 -0800" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Thu Jan 16 12:01:04 2014 -0800" }, "message": "clk: qcom: Add support for MSM8974\u0027s global clock controller (GCC)\n\nAdd a driver for the global clock controller found on MSM 8974\nbased platforms. This should allow most non-multimedia device\ndrivers to probe and control their clocks.\n\nSigned-off-by: Stephen Boyd \u003csboyd@codeaurora.org\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "6d00b56fe8c6f10076c9477e1cce99caf4568760", "tree": "ed9acf11a5b7c316a70eac4bf3a4686d70926cb0", "parents": [ "2ec941304df9e1cd5e2f2404303a5fab0929969a" ], "author": { "name": "Stephen Boyd", "email": "sboyd@codeaurora.org", "time": "Wed Jan 15 10:47:29 2014 -0800" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Thu Jan 16 12:01:03 2014 -0800" }, "message": "clk: qcom: Add support for MSM8960\u0027s multimedia clock controller (MMCC)\n\nAdd a driver for the multimedia clock controller found on MSM\n8960 based platforms. This should allow multimedia device drivers\nto probe and control their clocks.\n\nSigned-off-by: Stephen Boyd \u003csboyd@codeaurora.org\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "2ec941304df9e1cd5e2f2404303a5fab0929969a", "tree": "f2abf4b8b889484c16b376256add03e705b8ac18", "parents": [ "b36ba30c8ac66249915c57be101180cc58c42085" ], "author": { "name": "Stephen Boyd", "email": "sboyd@codeaurora.org", "time": "Wed Jan 15 10:47:28 2014 -0800" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Thu Jan 16 12:01:02 2014 -0800" }, "message": "clk: qcom: Add support for MSM8960\u0027s global clock controller (GCC)\n\nAdd a driver for the global clock controller found on MSM8960\nbased platforms. This should allow most non-multimedia device\ndrivers to probe and control their clocks.\n\nSigned-off-by: Stephen Boyd \u003csboyd@codeaurora.org\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "b36ba30c8ac66249915c57be101180cc58c42085", "tree": "4dc542affa7a2a416e8f62f88f0adb16b6ba937f", "parents": [ "6e0ad1b6c1c9809a8ea9ca647cbc0471e8b4164d" ], "author": { "name": "Stephen Boyd", "email": "sboyd@codeaurora.org", "time": "Wed Jan 15 10:47:27 2014 -0800" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Thu Jan 16 12:01:02 2014 -0800" }, "message": "clk: qcom: Add reset controller support\n\nReset controllers and clock controllers are combined into one IP\nblock on Qualcomm chipsets. Usually a reset signal is associated\nwith each clock branch but sometimes a reset signal is associated\nwith a handful of clocks. Either way the register interface is\nthe same; set a bit to assert a reset and clear a bit to deassert\na reset. Add support for these types of resets signals.\n\nSigned-off-by: Stephen Boyd \u003csboyd@codeaurora.org\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "6e0ad1b6c1c9809a8ea9ca647cbc0471e8b4164d", "tree": "c6e6357fa0d38b8cab82030f0c997afe5058598f", "parents": [ "bcd61c0f535a04a2aaa3f3ba27e60fae681fc88f" ], "author": { "name": "Stephen Boyd", "email": "sboyd@codeaurora.org", "time": "Wed Jan 15 10:47:26 2014 -0800" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Thu Jan 16 12:01:01 2014 -0800" }, "message": "clk: qcom: Add support for branches/gate clocks\n\nSigned-off-by: Stephen Boyd \u003csboyd@codeaurora.org\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "bcd61c0f535a04a2aaa3f3ba27e60fae681fc88f", "tree": "81fbb7830130ed91c207a3f088a9b5683a9f089e", "parents": [ "9e2631313c463c11645db046beb9bdecaf28b62f" ], "author": { "name": "Stephen Boyd", "email": "sboyd@codeaurora.org", "time": "Wed Jan 15 10:47:25 2014 -0800" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Thu Jan 16 12:01:00 2014 -0800" }, "message": "clk: qcom: Add support for root clock generators (RCGs)\n\nAdd support for the root clock generators on Qualcomm devices.\nRCGs are highly customizable mux/divider/counter clocks that can\nbe used to generate almost any rate desired given some input\nsource that is faster than the desired rate.\n\nSigned-off-by: Stephen Boyd \u003csboyd@codeaurora.org\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "9e2631313c463c11645db046beb9bdecaf28b62f", "tree": "e5af54c695abf7a218b7af55c5fcc40bcf9076e3", "parents": [ "085d7a455444f4d425371ee3c8a273c6e1b522db" ], "author": { "name": "Stephen Boyd", "email": "sboyd@codeaurora.org", "time": "Wed Jan 15 10:47:24 2014 -0800" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Thu Jan 16 12:00:59 2014 -0800" }, "message": "clk: qcom: Add support for phase locked loops (PLLs)\n\nAdd support for Qualcomm\u0027s PLLs (phase locked loops). This is\nsufficient enough to be able to determine the rate the PLL is\nrunning at. We can add rate setting support later when it\u0027s\nneeded.\n\nSigned-off-by: Stephen Boyd \u003csboyd@codeaurora.org\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "085d7a455444f4d425371ee3c8a273c6e1b522db", "tree": "77367862a144e00868d3bd8d08d6f41c1bfd7f5c", "parents": [ "3fa2252b7a78a8057017471a28f47b306e95ee26" ], "author": { "name": "Stephen Boyd", "email": "sboyd@codeaurora.org", "time": "Wed Jan 15 10:47:23 2014 -0800" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Thu Jan 16 12:00:58 2014 -0800" }, "message": "clk: qcom: Add a regmap type clock struct\n\nAdd a clock type that associates a regmap pointer and some\nenable/disable bits with a clk_hw struct. This will be the struct\nthat a hw specific implementation wraps if it wants to use the\nregmap helper functions.\n\nSigned-off-by: Stephen Boyd \u003csboyd@codeaurora.org\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "3fa2252b7a78a8057017471a28f47b306e95ee26", "tree": "e3cf04e4099a9414b15d27f6428f7726f29d7a05", "parents": [ "d0d44dd4ac58bc547646a9d0e65b4648f97cb533" ], "author": { "name": "Stephen Boyd", "email": "sboyd@codeaurora.org", "time": "Wed Jan 15 10:47:22 2014 -0800" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Thu Jan 16 12:00:57 2014 -0800" }, "message": "clk: Add set_rate_and_parent() op\n\nSome of Qualcomm\u0027s clocks can change their parent and rate at the\nsame time with a single register write. Add support for this\nhardware to the common clock framework by adding a new\nset_rate_and_parent() op. When the clock framework determines\nthat both the parent and the rate are going to change during\nclk_set_rate() it will call the .set_rate_and_parent() op if\navailable and fall back to calling .set_parent() followed by\n.set_rate() otherwise.\n\nReviewed-by: James Hogan \u003cjames.hogan@imgtec.com\u003e\nSigned-off-by: Stephen Boyd \u003csboyd@codeaurora.org\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "7bf21bc81f28cefa61250cfd9de2c884bbe1f3db", "tree": "4ebe55e17d9a341ae339deb92bca1a83d5a129fc", "parents": [ "5d2043fbe4ddc6cc16ba71b49c2c13f4cb2fe932" ], "author": { "name": "Barry Song", "email": "Baohua.Song@csr.com", "time": "Wed Jan 15 14:11:34 2014 +0800" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Thu Jan 16 12:00:53 2014 -0800" }, "message": "clk: sirf: re-arch to make the codes support both prima2 and atlas6\n\nsirfprima2 and sirfatlas6 are two different SoCs in CSR SiRF series. for\nprima2 and atlas6, there are many shared clocks but there are still\nsome different register layout and hardware clocks, then result in\ndifferent clock table.\n\nhere we re-arch the driver to\n1. clk-common.c provides common clocks for prima2 and atlas6,\n2. clk-prima2.h describles registers of prima2 and clk-prima2.c provides\nprima2 specific clocks and clock table.\n3. clk-atlas6.h describles registers of atlas6 and clk-atlas6.c provides\natlas6 specific clocks and clock table.\n4. clk.h and clk.c expose external interfaces and provide uniform entry\nfor both prima2 and atlas6.\n\nso both prima2 and atlas6 will get support by drivers/clk/sirf.\n\nSigned-off-by: Barry Song \u003cBaohua.Song@csr.com\u003e\nSigned-off-by: Rongjun Ying \u003cRongjun.Ying@csr.com\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "5d2043fbe4ddc6cc16ba71b49c2c13f4cb2fe932", "tree": "7252db3f4c513e4184970a0b838a56634f0e9268", "parents": [ "119754e57609113818f1226925046bfd54d6dc53" ], "author": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Tue Jan 14 12:56:01 2014 -0800" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Wed Jan 15 07:48:03 2014 -0800" }, "message": "clk: composite: pass mux_hw into determine_rate\n\nThe composite clock\u0027s .determine_rate implementation can call the\nunderyling .determine_rate callback corresponding to rate_hw or the\nunderlying .determine_rate callback corresponding to mux_hw. In both\ncases we pass in rate_hw, which is wrong. Fixed by passing mux_hw into\nthe correct callback.\n\nReported-by: Lemon Dai \u003cdailemon.gl@gmail.com\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "273c2279ca502267fac40bcaecb35942380c429c", "tree": "d062ef1ef525a7a6d4904eeabe52ae6221249846", "parents": [ "26d5f92adf87b1267feb8727ec59c4d0c0d933be", "e91a5555df5883bbc204b0e1f8e0489d3f7f3f2e" ], "author": { "name": "Kevin Hilman", "email": "khilman@linaro.org", "time": "Tue Jan 14 15:41:48 2014 -0800" }, "committer": { "name": "Kevin Hilman", "email": "khilman@linaro.org", "time": "Tue Jan 14 15:41:57 2014 -0800" }, "message": "Merge tag \u0027at91-cleanup2\u0027 of git://github.com/at91linux/linux-at91 into next/cleanup\n\nFrom Nicolas Ferre:\nSecond cleanup pull-request for 3.14:\n- a tiny fix for the recent AT91 CCF implementation\n- the switch of one platform to DT with board file removal\n\n* tag \u0027at91-cleanup2\u0027 of git://github.com/at91linux/linux-at91:\n ARM: at91: switch Calao QIL-A9260 board to DT\n clk: at91: fix pmc_clk_ids data type attriubte\n\nSigned-off-by: Kevin Hilman \u003ckhilman@linaro.org\u003e\n" }, { "commit": "099c2e9ef671519d4c7f9d49782845adc4f54a39", "tree": "6b2f2bed35151959b278d687a71c904da61cce17", "parents": [ "d267aae2f30ec7739adce351f6d20cd7f4eb6448", "bbc28cdbd003be5ceeaf644be3533e898c25da2b" ], "author": { "name": "Kevin Hilman", "email": "khilman@linaro.org", "time": "Tue Jan 14 14:20:19 2014 -0800" }, "committer": { "name": "Kevin Hilman", "email": "khilman@linaro.org", "time": "Tue Jan 14 14:20:19 2014 -0800" }, "message": "Merge tag \u0027omap-for-v3.14/fixes-not-urgent-signed\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/fixes-non-critical\n\nFrom Tony Lindgren:\nSome non-urgent fixes to enable am335x features, update documentation,\nand to remove unnecessary double initialization for the GPMC code.\n\n* tag \u0027omap-for-v3.14/fixes-not-urgent-signed\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (238 commits)\n ARM: OMAP2+: gpmc: Move legacy GPMC width setting\n ARM: OMAP2+: gpmc: Introduce gpmc_set_legacy()\n ARM: OMAP2+: gpmc: Move initialization outside the gpmc_t condition\n ARM: OMAP2+: board-generic: update SoC compatibility strings\n Documentation: dt: OMAP: explicitly state SoC compatible strings\n ARM: OMAP2+: enable AM33xx SOC EVM audio\n ARM: OMAP2+: Select USB PHY for AM335x SoC\n +Linux 3.13-rc5\n" }, { "commit": "119754e57609113818f1226925046bfd54d6dc53", "tree": "988dc5d248718b4b3eee702b8aa40bad35c37f8e", "parents": [ "baa39cd20ece9705e7e42015a1c7a898a36c31c8", "209f4fedcfdeeecfc9e87c045990230cc2162169" ], "author": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Tue Jan 14 11:41:26 2014 -0800" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Tue Jan 14 11:41:26 2014 -0800" }, "message": "Merge branch \u0027clk-next-shmobile\u0027 into clk-next\n" }, { "commit": "209f4fedcfdeeecfc9e87c045990230cc2162169", "tree": "ad19af7b435d79c4983522fb6a5c7c3079ce54e2", "parents": [ "6413b090dedd8da4753453d25668098e5bc1f4e4" ], "author": { "name": "Valentine Barshak", "email": "valentine.barshak@cogentembedded.com", "time": "Sat Dec 28 16:09:09 2013 +0400" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Tue Jan 14 11:35:57 2014 -0800" }, "message": "clk: shmobile: Fix MSTP clock array initialization\n\nThe clks member of the clk_onecell_data structure should\npoint to a valid clk array (no NULL entries allowed),\nand the clk_num should be equal to the number\nof elements in the clks array.\n\nThe MSTP driver fails to satisfy the above conditions.\nThe clks array may contain NULL entries if not all\nclock-indices are initialized in the device tree.\nThus, if the clock indices are interleaved we end up\nwith NULL pointers in-between.\n\nThe other problem is the driver uses maximum clock index\nas the number of clocks, which is incorrect (less than\nthe actual number of clocks by 1).\n\nFix the first issue by pre-setting the whole clks array\nwith ERR_PTR(-ENOENT) pointers instead of zeros; and\nuse maximum clkidx + 1 as the number of clocks to fix\nthe other one.\n\nThis should make of_clk_src_onecell_get() return the following:\n* valid clk pointers for all clocks registered;\n* ERR_PTR(-EINVAL) if (idx \u003e\u003d clk_data-\u003eclk_num);\n* ERR_PTR(-ENOENT) if the clock at the selected index was not\n initialized in the device tree (and was not registered).\n\nChanges in V2:\n* removed brackets from the one-line for loop\n\nSigned-off-by: Valentine Barshak \u003cvalentine.barshak@cogentembedded.com\u003e\nAcked-by: Laurent Pinchart \u003claurent.pinchart@ideasonboard.com\u003e\nTested-by: Ben Dooks \u003cben.dooks@codethink.co.uk\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "6413b090dedd8da4753453d25668098e5bc1f4e4", "tree": "bd246d004a79b8b282feb02db284a7ee3cf8c581", "parents": [ "6b71e0d9d6bfd24d2426a4ea7edf3c01d872903f" ], "author": { "name": "Valentine Barshak", "email": "valentine.barshak@cogentembedded.com", "time": "Sat Dec 28 16:09:08 2013 +0400" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Tue Jan 14 11:35:45 2014 -0800" }, "message": "clk: shmobile: Fix MSTP clock index\n\nUse clkidx when registering MSTP clocks instead of loop counter\nsince the value is then used to access the specific clock index bit\nin the mstp register.\n\nThe issue was introduced by the following commit:\nf94859c215b6d977 \"clk: shmobile: Add MSTP clock support\"\n\nChanges in V2:\n* none\n\nSigned-off-by: Valentine Barshak \u003cvalentine.barshak@cogentembedded.com\u003e\nAcked-by: Laurent Pinchart \u003claurent.pinchart@ideasonboard.com\u003e\nTested-by: Ben Dooks \u003cben.dooks@codethink.co.uk\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "baa39cd20ece9705e7e42015a1c7a898a36c31c8", "tree": "6f5cc02889c1d4f8b29716e48b7784d326e6e54f", "parents": [ "ada12c4798bcd01128e8e30f45e889083bb68730", "59d711e9ddd2f68822a2a99fc939e11a9288b73e" ], "author": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Wed Jan 08 16:38:10 2014 -0800" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Wed Jan 08 16:38:10 2014 -0800" }, "message": "Merge tag \u0027for_3.14/samsung-clk\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk into clk-next-samsung\n\n(A bit late) first round of Samsung clock patches for v3.14.\n" }, { "commit": "b06c698716476dffb9537b06b0406a55d6fe4cd8", "tree": "4ba6c8137d4a6a102f1f159a258fe3eb9baa9164", "parents": [ "3966c947f45911e093114371462687134d5e8d40" ], "author": { "name": "Tomasz Figa", "email": "t.figa@samsung.com", "time": "Thu Dec 12 17:07:20 2013 +0100" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Wed Jan 08 09:57:07 2014 -0800" }, "message": "clk: max77686: Register OF clock provider\n\nIf max77686 chip is instantiated from device tree, it is desirable to\nhave an OF clock provider to allow device tree based look-up of clocks.\nThis patch adds OF clock provider registration to the clk-max77686\ndriver.\n\nSigned-off-by: Tomasz Figa \u003ct.figa@samsung.com\u003e\nAcked-by: Kyungmin Park \u003ckyungmin.park@samsung.com\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "3966c947f45911e093114371462687134d5e8d40", "tree": "d83e0faef3d02d6fd89aeca672794ac9ad7f3b22", "parents": [ "d73ac4ca66676d0b0d57a8828d10d479ad054d0c" ], "author": { "name": "Tomasz Figa", "email": "t.figa@samsung.com", "time": "Thu Dec 12 17:07:19 2013 +0100" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Wed Jan 08 09:57:07 2014 -0800" }, "message": "clk: max77686: Refactor driver data handling\n\nAs a prerequisite for further patch adding OF clock provider support to\nthe driver, this patch changes the driver to store an array of struct\nclk * as driver data.\n\nSigned-off-by: Tomasz Figa \u003ct.figa@samsung.com\u003e\nAcked-by: Kyungmin Park \u003ckyungmin.park@samsung.com\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "d73ac4ca66676d0b0d57a8828d10d479ad054d0c", "tree": "e00fc507eb388a92c1593a96b5523f5e010bdd79", "parents": [ "badbc542f970a40f4c15014501016584f783782d" ], "author": { "name": "Tomasz Figa", "email": "t.figa@samsung.com", "time": "Thu Dec 12 17:07:18 2013 +0100" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Wed Jan 08 09:53:52 2014 -0800" }, "message": "clk: max77686: Fix clean-up in error and remove paths\n\nThis patch fixes invalid kfree() and adds missing call to clk_unregister()\nin error and remove paths in max77686_clk_probe(). While at it, error\nhandling is also cleaned up.\n\nSigned-off-by: Tomasz Figa \u003ct.figa@samsung.com\u003e\nAcked-by: Kyungmin Park \u003ckyungmin.park@samsung.com\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "badbc542f970a40f4c15014501016584f783782d", "tree": "3e035079ec87213154906ac573bac214b88d03ea", "parents": [ "b0f851777131b9fbd6f5853bea1f6144e88c1c72" ], "author": { "name": "Tomasz Figa", "email": "t.figa@samsung.com", "time": "Thu Dec 12 17:07:17 2013 +0100" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Wed Jan 08 09:46:03 2014 -0800" }, "message": "clk: max77686: Make max77686_clk_register() return struct clk *\n\nAs a preparation for further patches, this patch modifies the clock\nregistration helper function to return a pointer to the newly registered\nclock. No functional change is done to the driver.\n\nSigned-off-by: Tomasz Figa \u003ct.figa@samsung.com\u003e\nAcked-by: Kyungmin Park \u003ckyungmin.park@samsung.com\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "b0f851777131b9fbd6f5853bea1f6144e88c1c72", "tree": "9f22b59eba56f8517612964a106a45f5e5fbe724", "parents": [ "cf7d4a6f845ea9e57fb6dacccf823b7c7eff4e8a" ], "author": { "name": "Tomasz Figa", "email": "t.figa@samsung.com", "time": "Thu Dec 12 17:07:16 2013 +0100" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Wed Jan 08 09:46:03 2014 -0800" }, "message": "clk: max77686: Refactor successful exit of probe function\n\nThe function can simply return 0, without jumping to a separate label,\nwhich does exactly the same. This patch does not introduce any\nfunctional change, just a clean-up.\n\nSigned-off-by: Tomasz Figa \u003ct.figa@samsung.com\u003e\nAcked-by: Kyungmin Park \u003ckyungmin.park@samsung.com\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "cf7d4a6f845ea9e57fb6dacccf823b7c7eff4e8a", "tree": "21cfb9283bb05221e86cc3b25cf6596fe3c8eae5", "parents": [ "21c8ed2dc05bc5477d55000c5e96a4f3e95f408e" ], "author": { "name": "Tomasz Figa", "email": "t.figa@samsung.com", "time": "Thu Dec 12 17:07:15 2013 +0100" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Wed Jan 08 09:46:03 2014 -0800" }, "message": "clk: max77686: Provide .recalc_rate() operation\n\nIt is usually nice to know frequency of a clock, so this patch adds a\n.recalc_rate() callback returning rates of provided clocks.\n\nSigned-off-by: Tomasz Figa \u003ct.figa@samsung.com\u003e\nAcked-by: Kyungmin Park \u003ckyungmin.park@samsung.com\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "21c8ed2dc05bc5477d55000c5e96a4f3e95f408e", "tree": "b593d6c31d3c0ad4679251b0de75f93d6e6f68fa", "parents": [ "310e39c9b3203142a81cdfe7605fc6d2ed6cc25a" ], "author": { "name": "Tomasz Figa", "email": "t.figa@samsung.com", "time": "Thu Dec 12 17:07:14 2013 +0100" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Wed Jan 08 09:46:02 2014 -0800" }, "message": "clk: max77686: Correct callback used for checking clock status\n\nChanging status of clock gates in max77686 requires i2c transfers, which\ncan sleep, so this is done in prepare and unprepare callbacks. Due to\nthis, checking whether whether the clock is ungated must be done\nin is_prepared() callback as well, for consistency.\n\nSigned-off-by: Tomasz Figa \u003ct.figa@samsung.com\u003e\nAcked-by: Kyungmin Park \u003ckyungmin.park@samsung.com\u003e\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "3538a2cf0e04ad69840d74f46f7f8af920d913b5", "tree": "f01c90bdb68d818038b67d06aee0a86e0c4b0247", "parents": [ "c08ceea3a9d3276ec464e8b74573b1c58e93db7f" ], "author": { "name": "Andrew Bresticker", "email": "abrestic@chromium.org", "time": "Wed Sep 25 14:12:51 2013 -0700" }, "committer": { "name": "Tomasz Figa", "email": "t.figa@samsung.com", "time": "Wed Jan 08 18:02:43 2014 +0100" }, "message": "clk: exynos-audss: add support for Exynos 5420\n\nThe AudioSS block on Exynos 5420 has an additional clock gate for the\nADMA bus clock.\n\nSigned-off-by: Andrew Bresticker \u003cabrestic@chromium.org\u003e\nAcked-by: Mike Turquette \u003cmturquette@linaro.org\u003e\nAcked-by: Kukjin Kim \u003ckgene.kim@samsung.com\u003e\nSigned-off-by: Tomasz Figa \u003ct.figa@samsung.com\u003e\n" }, { "commit": "35399dda011b515120e0c39463ac32f0cac75c6a", "tree": "d3117a0bf64baa1b1841570ed61af2cbd25f3cf0", "parents": [ "547f33509ccc6e016df02600d377778b75e26a7b" ], "author": { "name": "Andrew Bresticker", "email": "abrestic@chromium.org", "time": "Wed Sep 25 14:12:49 2013 -0700" }, "committer": { "name": "Tomasz Figa", "email": "t.figa@samsung.com", "time": "Wed Jan 08 18:02:42 2014 +0100" }, "message": "clk: exynos5250: add clock ID for div_pcm0\n\nThere is no gate for the PCM clock input to the AudioSS block, so\nthe parent of sclk_pcm is div_pcm0. Add a clock ID for it so that\nwe can reference it in device trees.\n\nSigned-off-by: Andrew Bresticker \u003cabrestic@chromium.org\u003e\nReviewed-by: Tomasz Figa \u003ct.figa@samsung.com\u003e\nAcked-by: Mike Turquette \u003cmturquette@linaro.org\u003e\nAcked-by: Kukjin Kim \u003ckgene.kim@samsung.com\u003e\nSigned-off-by: Tomasz Figa \u003ct.figa@samsung.com\u003e\n" }, { "commit": "547f33509ccc6e016df02600d377778b75e26a7b", "tree": "2b534dc529d2b747c4fe50e48019aa0a4cd7a0f3", "parents": [ "b37a4224104568198b93fb9831224cfe7d83fff8" ], "author": { "name": "Andrew Bresticker", "email": "abrestic@chromium.org", "time": "Wed Sep 25 14:12:48 2013 -0700" }, "committer": { "name": "Tomasz Figa", "email": "t.figa@samsung.com", "time": "Wed Jan 08 18:02:41 2014 +0100" }, "message": "clk: exynos-audss: allow input clocks to be specified in device tree\n\nThis allows the input clocks to the Exynos AudioSS block to be\nspecified via device-tree bindings. Default names will be used\nwhen an input clock is not given.\n\nSigned-off-by: Andrew Bresticker \u003cabrestic@chromium.org\u003e\nAcked-by: Mike Turquette \u003cmturquette@linaro.org\u003e\nAcked-by: Kukjin Kim \u003ckgene.kim@samsung.com\u003e\nSigned-off-by: Tomasz Figa \u003ct.figa@samsung.com\u003e\n" }, { "commit": "b37a4224104568198b93fb9831224cfe7d83fff8", "tree": "9611f57e12078f03290a45381bc9a1bc4aa5c0d3", "parents": [ "ad3ab455d31da40061c4df32ae5ff11a731f5890" ], "author": { "name": "Andrew Bresticker", "email": "abrestic@chromium.org", "time": "Wed Sep 25 14:12:47 2013 -0700" }, "committer": { "name": "Tomasz Figa", "email": "t.figa@samsung.com", "time": "Wed Jan 08 18:02:41 2014 +0100" }, "message": "clk: exynos-audss: convert to platform device\n\nThe Exynos AudioSS clock controller will later be modified to allow\ninput clocks to be specified via device-tree in order to support\nmultiple Exynos SoCs. This will introduce a dependency on the core\nSoC clock controller being initialized first so that the AudioSS driver\ncan look up its input clocks, but the order in which clock providers\nare probed in of_clk_init() is not guaranteed. Since deferred probing\nis not supported in of_clk_init() and the AudioSS block is not the core\ncontroller, we can initialize it later as a platform device.\n\nSigned-off-by: Andrew Bresticker \u003cabrestic@chromium.org\u003e\nAcked-by: Tomasz Figa \u003ct.figa@samsung.com\u003e\nReviewed-by: Sylwester Nawrocki \u003cs.nawrocki@samsung.com\u003e\nAcked-by: Mike Turquette \u003cmturquette@linaro.org\u003e\nAcked-by: Kukjin Kim \u003ckgene.kim@samsung.com\u003e\nSigned-off-by: Tomasz Figa \u003ct.figa@samsung.com\u003e\n" }, { "commit": "ad3ab455d31da40061c4df32ae5ff11a731f5890", "tree": "6ff1ca87966cd7af5e010e16c3c5b10c270e8240", "parents": [ "7c556885ec95a463ea7670dc36f3efe2faf9d237" ], "author": { "name": "Andrzej Hajda", "email": "a.hajda@samsung.com", "time": "Tue Jan 07 15:47:40 2014 +0100" }, "committer": { "name": "Tomasz Figa", "email": "t.figa@samsung.com", "time": "Wed Jan 08 18:02:40 2014 +0100" }, "message": "clk: exynos5440: replace clock ID private enums with IDs from DT header\n\nThe patch replaces private enum clock IDs in the driver with macros provided\nby the DT header.\n\nSigned-off-by: Andrzej Hajda \u003ca.hajda@samsung.com\u003e\nSigned-off-by: Kyungmin Park \u003ckyungmin.park@samsung.com\u003e\nAcked-by: Mike Turquette \u003cmturquette@linaro.org\u003e\nAcked-by: Kukjin Kim \u003ckgene.kim@samsung.com\u003e\nSigned-off-by: Tomasz Figa \u003ct.figa@samsung.com\u003e\n" }, { "commit": "cba9d2fa8bc38aadaad5b31f84cc500897c70fea", "tree": "07b90e974b38f9aeadcbd3fde6f742c7688db1f3", "parents": [ "8774e124727e01ccf4c4af9accea6faf2d1386a2" ], "author": { "name": "Andrzej Hajda", "email": "a.hajda@samsung.com", "time": "Tue Jan 07 15:47:37 2014 +0100" }, "committer": { "name": "Tomasz Figa", "email": "t.figa@samsung.com", "time": "Wed Jan 08 18:02:39 2014 +0100" }, "message": "clk: exynos5420: replace clock ID private enums with IDs from DT header\n\nThe patch replaces private enum clock IDs in the driver with macros provided\nby the DT header.\n\nSigned-off-by: Andrzej Hajda \u003ca.hajda@samsung.com\u003e\nSigned-off-by: Kyungmin Park \u003ckyungmin.park@samsung.com\u003e\nAcked-by: Mike Turquette \u003cmturquette@linaro.org\u003e\nAcked-by: Kukjin Kim \u003ckgene.kim@samsung.com\u003e\nSigned-off-by: Tomasz Figa \u003ct.figa@samsung.com\u003e\n" }, { "commit": "2fe8f00c497624f8e88dcb212ae227bd06ee6bb7", "tree": "9f5170563933cd0db2b327d310a3328c780ff384", "parents": [ "b568059b16c5f29130443f97cba33b34557ab06f" ], "author": { "name": "Andrzej Hajda", "email": "a.hajda@samsung.com", "time": "Tue Jan 07 15:47:34 2014 +0100" }, "committer": { "name": "Tomasz Figa", "email": "t.figa@samsung.com", "time": "Wed Jan 08 18:02:38 2014 +0100" }, "message": "clk: exynos5250: replace clock ID private enums with IDs from DT header\n\nThe patch replaces private enum clock IDs in the driver with macros provided\nby the DT header.\n\nSigned-off-by: Andrzej Hajda \u003ca.hajda@samsung.com\u003e\nSigned-off-by: Kyungmin Park \u003ckyungmin.park@samsung.com\u003e\nAcked-by: Mike Turquette \u003cmturquette@linaro.org\u003e\nAcked-by: Kukjin Kim \u003ckgene.kim@samsung.com\u003e\nSigned-off-by: Tomasz Figa \u003ct.figa@samsung.com\u003e\n" }, { "commit": "2d73823750542c0dcbc9e7e00cd36d70ade3a65f", "tree": "ca363f43f056cc66b1c4f4f575b878c34cee20ef", "parents": [ "26460bc5588832fd660081cb36103efdaa04291d" ], "author": { "name": "Andrzej Hajda", "email": "a.hajda@samsung.com", "time": "Tue Jan 07 15:47:31 2014 +0100" }, "committer": { "name": "Tomasz Figa", "email": "t.figa@samsung.com", "time": "Wed Jan 08 18:02:38 2014 +0100" }, "message": "clk: exynos4: replace clock ID private enums with IDs from DT header\n\nThe patch replaces private enum clock IDs in the driver with macros provided\nby the DT header.\n\nSigned-off-by: Andrzej Hajda \u003ca.hajda@samsung.com\u003e\nSigned-off-by: Kyungmin Park \u003ckyungmin.park@samsung.com\u003e\nAcked-by: Mike Turquette \u003cmturquette@linaro.org\u003e\nAcked-by: Kukjin Kim \u003ckgene.kim@samsung.com\u003e\nSigned-off-by: Tomasz Figa \u003ct.figa@samsung.com\u003e\n" }, { "commit": "f521ac8b390cd6e1ce3407442d500528becd5874", "tree": "f986ab3e2369bf920fbdf31621ccc8260c50485b", "parents": [ "e86ffc4199c6004274cb4a169c7f84cc489532d4" ], "author": { "name": "Andrew Bresticker", "email": "abrestic@chromium.org", "time": "Fri Nov 08 15:44:08 2013 +0530" }, "committer": { "name": "Tomasz Figa", "email": "t.figa@samsung.com", "time": "Wed Jan 08 18:01:49 2014 +0100" }, "message": "clk: exynos5250: register APLL rate table\n\nRegister the APLL rate table so that we can set the APLL rate from\nthe cpufreq driver.\n\nSigned-off-by: Andrew Bresticker \u003cabrestic@chromium.org\u003e\nSigned-off-by: Sachin Kamat \u003csachin.kamat@linaro.org\u003e\nSigned-off-by: Tomasz Figa \u003ct.figa@samsung.com\u003e\n" }, { "commit": "778037e1ccb75609846deca9e419449c1dc137fa", "tree": "7721a277ab3427f7941915122ed327b006153128", "parents": [ "497d2214e5ba58ef55025b9951e7f9cccab760e4" ], "author": { "name": "James Hogan", "email": "james.hogan@imgtec.com", "time": "Mon Dec 16 10:41:38 2013 +0000" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Wed Jan 08 08:33:12 2014 -0800" }, "message": "clk: clk-divider: fix divisor \u003e 255 bug\n\nCommit 6d9252bd9a4bb (clk: Add support for power of two type dividers)\nmerged in v3.6 added the _get_val function to convert a divisor value to\na register field value depending on the flags. However it used the type\nu8 for the div field, causing divisors larger than 255 to be masked\nand the resultant clock rate to be too high.\n\nE.g. in my case an 11bit divider was supposed to divide 24.576 MHz down\nto 32.768KHz. The divisor was correctly calculated as 750 (0x2ee). This\nwas masked to 238 (0xee) resulting in a frequency of 103.26KHz.\n\nSigned-off-by: James Hogan \u003cjames.hogan@imgtec.com\u003e\nCc: Rajendra Nayak \u003crnayak@ti.com\u003e\nCc: linux-arm-kernel@lists.infradead.org\nCc: stable@vger.kernel.org\nSigned-off-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "497d2214e5ba58ef55025b9951e7f9cccab760e4", "tree": "3988e3c8ff28aadc8d5d118a7d718a0bc10e5fe2", "parents": [ "d6e0a2dd12f4067a5bcefb8bbd8ddbeff800afbc", "3fd68c99f3026f4fe3a1b7b6fb75e5638b2032fd" ], "author": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Sun Jan 05 21:36:43 2014 -0800" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Sun Jan 05 21:36:43 2014 -0800" }, "message": "Merge tag \u0027samsung-clk-fixes\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk into clk-fixes\n\nSamsung Clock fixes for 3.13-rc7\n\n* Several patches fixing up incorrectly defined register addresses and\n bitfield offsets that could lead to undefined operation when accessing\n respective registers or bitfields.\n\n 1) clk: exynos5250: fix sysmmu_mfc{l,r} gate clocks\n\n 2a) clk: samsung: exynos5250: Fix ACP gate register offset\n 2b) clk: samsung: exynos5250: Add MDMA0 clocks\n 2c) ARM: dts: exynos5250: Fix MDMA0 clock number\n\n 3) clk: samsung: exynos4: Correct SRC_MFC register\n\n All three issues have been present since Exynos5250 and Exynos4 clock\n drivers were added by commits 6e3ad26816b72 (\"clk: exynos5250:\n register clocks using common clock framework\") and e062b571777f5\n (\"clk: exynos4: register clocks using common clock framework\")\n respectively.\n\n* Patch to fix automatic disabling of Exynos5250 sysreg clock that could\n cause undefined operation of several peripherals, such as USB, I2C,\n MIPI or display block.\n\n 4) clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg\n clock\n\n Present since Exynos5250 clock drivers was added by commits\n 6e3ad26816b72 (\"clk: exynos5250: register clocks using common clock\n framework\").\n\n* Patch fixing compilation warning in clk-exynos-audss driver when\n CONFIG_PM_SLEEP is disabled.\n\n 5) clk: exynos: File scope reg_save array should depend on PM_SLEEP\n\n Present since the driver was added by commit 1241ef94ccc3 (\"clk:\n samsung: register audio subsystem clocks using common clock\n framework\").\n" }, { "commit": "3d7e0207ced354d1647195f53bcc670f9756c649", "tree": "bedff8fa54a8a086e7426d66a0069323b5864986", "parents": [ "7bfc397fe76de447ca645edd7453d8ef6ab18279", "8e048b9997efbe75fe77b1f14d3af41700cc8724" ], "author": { "name": "Olof Johansson", "email": "olof@lixom.net", "time": "Fri Jan 03 21:55:29 2014 -0800" }, "committer": { "name": "Olof Johansson", "email": "olof@lixom.net", "time": "Fri Jan 03 21:55:29 2014 -0800" }, "message": "Merge tag \u0027integrator-for-v3.14\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into next/drivers\n\nFrom Linus Walleij:\nSome Integrator patches that matured for v3.14:\n\n- Use PATCH_PHYS_TO_VIRT and AUTO_ZRELADDR.\n- Support cascaded interrupts on the SIC.\n- Complete clock implementation for the IM-PD1.\n\n* tag \u0027integrator-for-v3.14\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator:\n clk: versatile: fixup IM-PD1 clock implementation\n clk: versatile: pass a name to ICST clock provider\n ARM: integrator: pass parent IRQ to the SIC\n irqchip: versatile FPGA: support cascaded interrupts from DT\n ARM: integrator: Default enable ARM_PATCH_PHYS_VIRT, AUTO_ZRELADDR\n\nSigned-off-by: Olof Johansson \u003colof@lixom.net\u003e\n" }, { "commit": "11b35a352521b740944455b45dbee190e9c893a4", "tree": "aa5bc9a24cb6290aaed5476990f0e5a05442ff38", "parents": [ "5631e7f4e29b1ebf3d856614c0b5876463857da6", "b652896b02df3dfde3a68957cce01f2aa4585842" ], "author": { "name": "Olof Johansson", "email": "olof@lixom.net", "time": "Fri Jan 03 21:09:51 2014 -0800" }, "committer": { "name": "Olof Johansson", "email": "olof@lixom.net", "time": "Fri Jan 03 21:09:51 2014 -0800" }, "message": "Merge tag \u0027renesas-dt3-for-v3.14\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt\n\nFrom Simon Horman:\nThird Round of Renesas ARM Based SoC DT Updates for v3.14\n\n* r8a7791 (R-Car M2) and r8a7790 (R-Car H2) SoCSs\n - Add SSI, QSPI and MSIOF clocks in device tree\n\nr8a7791 (R-Car M2) based Koelsch and r8a7790 (R-Car H2) based Lager boards\n - Remove reference DTS\n - Specify external clock frequency in DT\n - Sync non-reference DTS with referene DTS\n - Add clocks to DTS\n\n* r8a7740 (R-Mobile A1) based Armadillo board\n - Add gpio-keys device\n - Add PWM backlight enable GPIO\n - Add PWM backlight power supply\n\n* r8a73a0 (SH-Mobile AG5), r8a7740 (R-Mobile A1) and\n r8a73a4 (SH-Mobile APE6) SoCs\n - Specify PFC interrupts in DT\n\n* tag \u0027renesas-dt3-for-v3.14\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (72 commits)\n ARM: shmobile: r8a7791: Add SSI clocks in device tree\n ARM: shmobile: r8a7790: Add SSI clocks in device tree\n ARM: shmobile: r8a7791: Add QSPI module clock in device tree\n ARM: shmobile: r8a7790: Add QSPI module clock in device tree\n ARM: shmobile: r8a7791: Add MSIOF clocks in device tree\n ARM: shmobile: r8a7790: Add MSIOF clocks in device tree\n ARM: shmobile: Remove Koelsch reference DTS\n ARM: shmobile: Remove Lager reference DTS\n ARM: shmobile: koelsch: Specify external clock frequency in DT\n ARM: shmobile: lager: Specify external clock frequency in DT\n ARM: shmobile: Sync Koelsch DTS with Koelsch reference DTS\n ARM: shmobile: Sync Lager DTS with Lager reference DTS\n ARM: shmobile: r8a7791: Add clocks\n ARM: shmobile: r8a7790: Reference clocks\n ARM: shmobile: r8a7790: Add clocks\n ARM: shmobile: armadillo: dts: Add gpio-keys device\n ARM: shmobile: sh73a0: Specify PFC interrupts in DT\n ARM: shmobile: r8a7740: Specify PFC interrupts in DT\n ARM: shmobile: r8a73a4: Specify PFC interrupts in DT\n ARM: shmobile: armadillo: dts: Add PWM backlight enable GPIO\n ...\n\nSigned-off-by: Olof Johansson \u003colof@lixom.net\u003e\n" }, { "commit": "8e048b9997efbe75fe77b1f14d3af41700cc8724", "tree": "bdb60e1592cc4af363774f07c1a2605dafa4bc89", "parents": [ "ae6e694ef566ed69a2537c80771a9031ec627494" ], "author": { "name": "Linus Walleij", "email": "linus.walleij@linaro.org", "time": "Fri Nov 22 16:25:09 2013 +0100" }, "committer": { "name": "Linus Walleij", "email": "linus.walleij@linaro.org", "time": "Fri Jan 03 22:27:54 2014 +0100" }, "message": "clk: versatile: fixup IM-PD1 clock implementation\n\nRegister both VCO clocks, give per-logical module unique names\nto the clocks so we can have several IM-PD1\u0027s connected (in\ntheory). Implement all the fixed-factor clocks as children of\nVCO2.\n\nTested by using the UARTs and the PL181 MMC block on the IM-PD1,\nworks flawlessly.\n\nAcked-by: Mike Turquette \u003cmturquette@linaro.org\u003e\nSigned-off-by: Linus Walleij \u003clinus.walleij@linaro.org\u003e\n" }, { "commit": "ae6e694ef566ed69a2537c80771a9031ec627494", "tree": "86fefdf50b9966e14eec25f6de162935195b0635", "parents": [ "8f6344faafb455e7481d87490d372c8337a0e32b" ], "author": { "name": "Linus Walleij", "email": "linus.walleij@linaro.org", "time": "Fri Nov 22 11:30:05 2013 +0100" }, "committer": { "name": "Linus Walleij", "email": "linus.walleij@linaro.org", "time": "Fri Jan 03 22:27:38 2014 +0100" }, "message": "clk: versatile: pass a name to ICST clock provider\n\nWhen we have more than one of these clocks in a system (such as\non the IM-PD1) we need a mechanism to pass a name for the clock.\nRefactor to add this as an argument.\n\nAcked-by: Mike Turquette \u003cmturquette@linaro.org\u003e\nSigned-off-by: Linus Walleij \u003clinus.walleij@linaro.org\u003e\n" }, { "commit": "2cde51fbd0f310c8a2c5f977e665c0ac3945b46d", "tree": "a2b6d153e535738946c9969a7c9d29392bd6263b", "parents": [ "7471c5c9f58eb7ff322dfcd7a8c6dc801c010b0d", "c097d5fdf3b51cdb2521c3cffab0a8cf03c68cc6", "74c375cb85d7374734e6e53af41c724d9a937f8e", "04c3a852f51ff40f32a29e14078432038b5bcdbc", "5095f55d7cc327026daaa3fa583aa4c1388ca556", "4f534777c130180f9338f0fb96090d43464b7ddf", "2f54d2a1cf7e62f56b1b0bcf44bd704f65359f38", "56d37d85438df38e150282baafe52dcd588854c7", "192043cf608909eb5728a5fd68f5234b90d9415b", "f467a0f513ad81998f0cad1022684a273d5743f7", "bbe580302d33cff282129e26c44f9c3450d6a086", "3990c516de66af940c5c366a81531787aefe81ae", "d754fa9ad18d16209c276fc6241aa2d10f819ede", "516ea4b584332f511d3bf1b98ceabd974b1a2313", "69ae8489076fa0fa98609155434f3c286c7364a0", "25c1a63f43ca40f1581c076b7f7618297ef1cbba", "f52c91921553be26c7a0de13daa0d18ef46655ff", "111bd7b18e13c66552e9a672000eeacacd414a65", "aafa85e71a75fdea9076c5e0f7fe09e12568c9a4", "dd407a3243234c6a17ba624d698e6824067003c9", "71467e46414d3bab220de77d3d085be0c0aa03e1", "0f7f3d1f17c2e4d73e449e6acb2007b13813c58e", "8778ac6be25abf0496fc614a3e77ad2ff8300353", "0406a40a095ca039e5f5ec63783342253c573d06", "308a0f3f24db5e5943ef0aad722e8b3d125dbddb", "2650bc4f6d0c36f1219d2070485cc2980a88fab3", "8cb7a36eb3a80cd58353e351b7b4370d9a9f0c14", "323702b4e06dfd1a4ee6cee5834a889b9663cccf", "ef749400434cefd14fe02fe3de9e9f0125b2256d", "3cec159cfb3fc69190f3ccdc2d1329c66775529f", "72aa62bed3ea30635156fad95f123a0b665072bf", "328089a47112a4fc06071e2003ecd75cc6d31029", "11db0da831b1e6ae3c1f8743599434281db294db", "e1771bcf99b0dc91f4ba645c1740fd5031702f49", "f60e5473e6788f93849a61198bec4e02fea31e51", "a010ff628c0953e6c914ecd09678363848617a88", "5e8154332f48f92f37824577c88e400b5e0cd56d", "58381da687742a3d8bbb98362152de8326a0c077", "626bcacb89f93b2145f3a705a342067a77347a99", "38136bde7691bdafa91c2320e014913aec6dbe6b", "06b2bd23057f9dad149f0dda436c7426c87b986f", "8c5178fca4ce5a57711ea14b807648e19b105d0e", "8e6ad35a31e7ebc59543df875fc970200df2cf68", "008ef947d0c5d14442256a37f6bf6b14015efe26", "f58c4fc4a3bf9eb699a638634d20ef4d16069366", "2309d6757900c4a6909fa673724976935b408a25", "5c1537163ce716e317776565b8210ea06fa2b5de", "b65ab73e5d624eb4a88bc6094a3627007cb92500", "26090a834b49673945458b185be0afa03c2737fe", "9ea6fbc66d15c83089e177b445872a9ba40f125d", "2c4864334c4d9a23fa810638ad27e80ea0ceb9a4", "1769267bb01303ac73b48535454461819ef1dcc2", "f3f9a60f7947b6bd2f970d5680dd3df624405027", "f25cf34969823ab7197ce9ff2521c33f0141075b", "3f3002692ce8fa1e9b257183ea1a36baacfdcfcf", "fbbf7fea8e806ccc3ce0e059ad1d9671d57b4309", "c3e8494c001ce0bec0ebaa49c6f5eeb2aa5ab36a", "e40e0b5da87bb4256a6dc62db7663b8a0c204f1f", "50c9697320434d1489d087cbf38f7907a9894609", "63587116811bd23d22693b50447a2a356602e70b", "0112b62b12e18b883e1027689acab8eaa8830bac", "a0a05916cf67a007f4ee0071fd0fa04e45137a38", "b888edbc68fbace3101cb092c6910476e85ae922", "d44008b358588cf6fcc74716b50584a8e59cbe65", "9a199b8e9933edf83585bac2c9030870e014381b", "784cbf8ab4641c874806a938b9c863c91d70fbe5" ], "author": { "name": "Mark Brown", "email": "broonie@linaro.org", "time": "Thu Jan 02 13:01:55 2014 +0000" }, "committer": { "name": "Mark Brown", "email": "broonie@linaro.org", "time": "Thu Jan 02 13:01:55 2014 +0000" }, "message": "Merge remote-tracking branches \u0027asoc/topic/ad1836\u0027, \u0027asoc/topic/ad193x\u0027, \u0027asoc/topic/adav80x\u0027, \u0027asoc/topic/adsp\u0027, \u0027asoc/topic/ak4641\u0027, \u0027asoc/topic/ak4642\u0027, \u0027asoc/topic/arizona\u0027, \u0027asoc/topic/atmel\u0027, \u0027asoc/topic/au1x\u0027, \u0027asoc/topic/axi\u0027, \u0027asoc/topic/bcm2835\u0027, \u0027asoc/topic/blackfin\u0027, \u0027asoc/topic/cs4271\u0027, \u0027asoc/topic/cs42l52\u0027, \u0027asoc/topic/da7210\u0027, \u0027asoc/topic/davinci\u0027, \u0027asoc/topic/ep93xx\u0027, \u0027asoc/topic/fsl\u0027, \u0027asoc/topic/fsl-mxs\u0027, \u0027asoc/topic/generic\u0027, \u0027asoc/topic/hdmi\u0027, \u0027asoc/topic/jack\u0027, \u0027asoc/topic/jz4740\u0027, \u0027asoc/topic/max98090\u0027, \u0027asoc/topic/mxs\u0027, \u0027asoc/topic/omap\u0027, \u0027asoc/topic/pxa\u0027, \u0027asoc/topic/rcar\u0027, \u0027asoc/topic/s6000\u0027, \u0027asoc/topic/sai\u0027, \u0027asoc/topic/samsung\u0027, \u0027asoc/topic/sgtl5000\u0027, \u0027asoc/topic/spear\u0027, \u0027asoc/topic/ssm2518\u0027, \u0027asoc/topic/ssm2602\u0027, \u0027asoc/topic/tegra\u0027, \u0027asoc/topic/tlv320aic3x\u0027, \u0027asoc/topic/twl6040\u0027, \u0027asoc/topic/txx9\u0027, \u0027asoc/topic/uda1380\u0027, \u0027asoc/topic/width\u0027, \u0027asoc/topic/wm8510\u0027, \u0027asoc/topic/wm8523\u0027, \u0027asoc/topic/wm8580\u0027, \u0027asoc/topic/wm8711\u0027, \u0027asoc/topic/wm8728\u0027, \u0027asoc/topic/wm8731\u0027, \u0027asoc/topic/wm8741\u0027, \u0027asoc/topic/wm8750\u0027, \u0027asoc/topic/wm8753\u0027, \u0027asoc/topic/wm8776\u0027, \u0027asoc/topic/wm8804\u0027, \u0027asoc/topic/wm8900\u0027, \u0027asoc/topic/wm8901\u0027, \u0027asoc/topic/wm8940\u0027, \u0027asoc/topic/wm8962\u0027, \u0027asoc/topic/wm8974\u0027, \u0027asoc/topic/wm8985\u0027, \u0027asoc/topic/wm8988\u0027, \u0027asoc/topic/wm8990\u0027, \u0027asoc/topic/wm8991\u0027, \u0027asoc/topic/wm8994\u0027, \u0027asoc/topic/wm8995\u0027, \u0027asoc/topic/wm9081\u0027 and \u0027asoc/topic/x86\u0027 into asoc-next\n" }, { "commit": "dbdf6ff51e3ce13ade5834b0d7d451522fcdb478", "tree": "b5594d70cf4d484101891adbfc01798c14827fa8", "parents": [ "391e3903e63781debc52a0de73f2e922dcc3f602", "9ffe29d780dd5f9c662f2c32f8dc64435da726bf" ], "author": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Tue Dec 31 11:35:12 2013 -0800" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Tue Dec 31 11:35:12 2013 -0800" }, "message": "Merge branch \u0027clk-next-unregister\u0027 into clk-next\n\nConflicts:\n\tdrivers/clk/clk.c\n" }, { "commit": "391e3903e63781debc52a0de73f2e922dcc3f602", "tree": "0f06e9555dc43090f265cbe726eb6051bf7a0d51", "parents": [ "6b71e0d9d6bfd24d2426a4ea7edf3c01d872903f", "e0c223ec67a98f70770eec85e625015f5af69f10" ], "author": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Mon Dec 30 10:58:22 2013 -0800" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Mon Dec 30 10:58:22 2013 -0800" }, "message": "Merge branch \u0027for_3.14/keystone-clk\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into clk-next-keystone\n" }, { "commit": "e86ffc4199c6004274cb4a169c7f84cc489532d4", "tree": "729e906f3d97496cc95c74c2fd74a09ad343100d", "parents": [ "96987ded8fd6e4b19fdac69950acfaeccd681952" ], "author": { "name": "Sachin Kamat", "email": "sachin.kamat@linaro.org", "time": "Thu Dec 19 14:03:39 2013 +0530" }, "committer": { "name": "Tomasz Figa", "email": "t.figa@samsung.com", "time": "Mon Dec 30 18:43:28 2013 +0100" }, "message": "clk: exynos5250: Add CLK_SET_RATE_PARENT flag to mout_apll\n\nAdd CLK_SET_RATE_PARENT flag to mout_apll clock. This will let us set the\nclock rate in the cpufreq driver.\n\nSigned-off-by: Sachin Kamat \u003csachin.kamat@linaro.org\u003e\nAcked-by: Mike Turquette \u003cmturquette@linaro.org\u003e\nSigned-off-by: Tomasz Figa \u003ct.figa@samsung.com\u003e\n" }, { "commit": "96987ded8fd6e4b19fdac69950acfaeccd681952", "tree": "52f80f05995803e8013d73a0358280f6ad453383", "parents": [ "bfeb9f274b128833eedcdea9779042e49cf4fa85" ], "author": { "name": "Tomasz Figa", "email": "t.figa@samsung.com", "time": "Tue Oct 15 19:41:21 2013 +0200" }, "committer": { "name": "Tomasz Figa", "email": "t.figa@samsung.com", "time": "Mon Dec 30 18:15:49 2013 +0100" }, "message": "clk: samsung: exynos5250: Fix parents of gate clocks from MFC domain\n\nThis patch adds mout_aclk333_sub mux clock and updates gate clocks from\nMFC domain to have it as their parent as specified in SoC documentation.\n\nSigned-off-by: Tomasz Figa \u003ct.figa@samsung.com\u003e\nSigned-off-by: Kyungmin Park \u003ckyungmin.park@samsung.com\u003e\nTested-by: Tomasz Figa \u003ct.figa@samsung.com\u003e\n" }, { "commit": "bfeb9f274b128833eedcdea9779042e49cf4fa85", "tree": "8c7b11899b5c89eb016e813114474d735b42c5ef", "parents": [ "256dd646a30fb7bc6720b636e8b9098cd492e603" ], "author": { "name": "Tomasz Figa", "email": "t.figa@samsung.com", "time": "Tue Oct 15 19:41:20 2013 +0200" }, "committer": { "name": "Tomasz Figa", "email": "t.figa@samsung.com", "time": "Mon Dec 30 18:15:49 2013 +0100" }, "message": "clk: samsung: exynos5250: Correct parent list of audio muxes\n\nAccording to SoC documentation, input 5 of mout_audio muxes is connected\nto xxti (named fin_pll in the driver). This patch corrects defined\nparent arrays to match SoC documentation.\n\nSigned-off-by: Tomasz Figa \u003ct.figa@samsung.com\u003e\nSigned-off-by: Kyungmin Park \u003ckyungmin.park@samsung.com\u003e\nTested-by: Tomasz Figa \u003ct.figa@samsung.com\u003e\n" }, { "commit": "256dd646a30fb7bc6720b636e8b9098cd492e603", "tree": "2d6283636c7c44f25248abb28e127949e4d00901", "parents": [ "3818f11740bbf87ad76f4f502f6739c8d62e5c17" ], "author": { "name": "Tomasz Figa", "email": "t.figa@samsung.com", "time": "Tue Oct 15 19:41:19 2013 +0200" }, "committer": { "name": "Tomasz Figa", "email": "t.figa@samsung.com", "time": "Mon Dec 30 18:15:48 2013 +0100" }, "message": "clk: samsung: exynos5250: Add missing unpopulated mux parents\n\nThis patch updates mux parent arrays with unpopulated mux inputs, as all\ninputs need to be specified in parent arrays passed to\nclk_register_mux(), otherwise clk_set_parent() can generate out of bound\naccesses to the array.\n\nSigned-off-by: Tomasz Figa \u003ct.figa@samsung.com\u003e\nSigned-off-by: Kyungmin Park \u003ckyungmin.park@samsung.com\u003e\nTested-by: Tomasz Figa \u003ct.figa@samsung.com\u003e\n" }, { "commit": "3818f11740bbf87ad76f4f502f6739c8d62e5c17", "tree": "19cc5c3a76f11607db73d0bf500ea4da0f788de9", "parents": [ "796d1f4cd62500ee55a645f2649b546710b11bd1" ], "author": { "name": "Tomasz Figa", "email": "t.figa@samsung.com", "time": "Tue Oct 15 19:41:18 2013 +0200" }, "committer": { "name": "Tomasz Figa", "email": "t.figa@samsung.com", "time": "Mon Dec 30 18:15:48 2013 +0100" }, "message": "clk: samsung: exynos5250: Fix parent of gate clocks from DISP1 domain\n\nThis patch adds mux_aclk_200_disp1_sub mux clock, which according to SoC\ndocumentation is the correct parent of DISP1 gate clocks.\n\nSigned-off-by: Tomasz Figa \u003ct.figa@samsung.com\u003e\nSigned-off-by: Kyungmin Park \u003ckyungmin.park@samsung.com\u003e\nTested-by: Tomasz Figa \u003ct.figa@samsung.com\u003e\n" }, { "commit": "796d1f4cd62500ee55a645f2649b546710b11bd1", "tree": "89defc880d949726f721dac203c9bfcb2b989624", "parents": [ "38ee37540f5a9dd946a9eaca3d48d178c72dbe15" ], "author": { "name": "Tomasz Figa", "email": "t.figa@samsung.com", "time": "Tue Oct 15 19:41:17 2013 +0200" }, "committer": { "name": "Tomasz Figa", "email": "t.figa@samsung.com", "time": "Mon Dec 30 18:15:47 2013 +0100" }, "message": "clk: samsung: exynos5250: Fix parents of gate clocks from GSCL domain\n\nThis patch adds mout_aclk266_gscl_sub mux clock and adjusts definitions\nof GSCL domain gate clocks to use it as their parent, as specified in\nSoC documentation.\n\nSigned-off-by: Tomasz Figa \u003ct.figa@samsung.com\u003e\nSigned-off-by: Kyungmin Park \u003ckyungmin.park@samsung.com\u003e\nTested-by: Tomasz Figa \u003ct.figa@samsung.com\u003e\n" }, { "commit": "38ee37540f5a9dd946a9eaca3d48d178c72dbe15", "tree": "d0f7cf52e8031c66bfa2846e31597c70260cd244", "parents": [ "2786c9622e9031ff03b6d54d8b5d2d28e9fd2579" ], "author": { "name": "Tomasz Figa", "email": "t.figa@samsung.com", "time": "Tue Oct 15 19:41:16 2013 +0200" }, "committer": { "name": "Tomasz Figa", "email": "t.figa@samsung.com", "time": "Mon Dec 30 18:15:47 2013 +0100" }, "message": "clk: samsung: exynos5250: Make names of mux and div clocks consistent\n\nThis patch renames all mux clocks to start with mout_ prefix and all div\nclocks to start with div_ prefix for consistency with other clocks\nalready defined this way.\n\nSigned-off-by: Tomasz Figa \u003ct.figa@samsung.com\u003e\nSigned-off-by: Kyungmin Park \u003ckyungmin.park@samsung.com\u003e\nTested-by: Tomasz Figa \u003ct.figa@samsung.com\u003e\n" }, { "commit": "2786c9622e9031ff03b6d54d8b5d2d28e9fd2579", "tree": "0c14d223a6ffa38705e74d12a73f9bedebcda489", "parents": [ "2bb00c68e094271b79deac993893461cc051b721" ], "author": { "name": "Tomasz Figa", "email": "t.figa@samsung.com", "time": "Tue Oct 15 19:41:15 2013 +0200" }, "committer": { "name": "Tomasz Figa", "email": "t.figa@samsung.com", "time": "Mon Dec 30 18:15:46 2013 +0100" }, "message": "clk: samsung: exynos5250: Sort definitions by registers and bitfield\n\nThis patch reorders clock definitions, so they are sorted by register\naddresses and bitfield shifts. When at it, blank lines are added to\nseparate definitions of clocks from different registers.\n\nOverall this should make the driver more readable and reduce the number\nof potential conflicts when adding new entries.\n\nSigned-off-by: Tomasz Figa \u003ct.figa@samsung.com\u003e\nSigned-off-by: Kyungmin Park \u003ckyungmin.park@samsung.com\u003e\nTested-by: Tomasz Figa \u003ct.figa@samsung.com\u003e\n" }, { "commit": "2bb00c68e094271b79deac993893461cc051b721", "tree": "dbd8676396eac15cc294da946d93fa671aab34bc", "parents": [ "ea72dc2cf9552631e43327ce593bdbb0b9fdf058", "3fd68c99f3026f4fe3a1b7b6fb75e5638b2032fd" ], "author": { "name": "Tomasz Figa", "email": "t.figa@samsung.com", "time": "Mon Dec 30 18:15:23 2013 +0100" }, "committer": { "name": "Tomasz Figa", "email": "t.figa@samsung.com", "time": "Mon Dec 30 18:15:23 2013 +0100" }, "message": "Merge branch \u0027samsung-fixes\u0027 into samsung-next-base\n" }, { "commit": "3fd68c99f3026f4fe3a1b7b6fb75e5638b2032fd", "tree": "397252af843faf5df3d2eb5e84bbbd469d8d5d0b", "parents": [ "2feed5aecf5f367b92bd6b6e92afe9e3de466907" ], "author": { "name": "Krzysztof Kozlowski", "email": "k.kozlowski@samsung.com", "time": "Tue Dec 17 10:56:39 2013 +0100" }, "committer": { "name": "Tomasz Figa", "email": "t.figa@samsung.com", "time": "Mon Dec 30 18:01:09 2013 +0100" }, "message": "clk: exynos: File scope reg_save array should depend on PM_SLEEP\n\nMove reg_save[] into CONFIG_PM_SLEEP dependency block as it is used only\nby suspend and resume functions.\n\nThis fixes the warning on CONFIG_PM_SLEEP\u003dn:\ndrivers/clk/samsung/clk-exynos-audss.c:29:22: warning: ‘reg_save’ defined but not used [-Wunused-variable]\n\nSigned-off-by: Krzysztof Kozlowski \u003ck.kozlowski@samsung.com\u003e\nAcked-by: Mike Turquette \u003cmturquette@linaro.org\u003e\nSigned-off-by: Tomasz Figa \u003ct.figa@samsung.com\u003e\n" }, { "commit": "2feed5aecf5f367b92bd6b6e92afe9e3de466907", "tree": "bc25576a744ec2a5f4e471622a5e8bdaf8e0ecc4", "parents": [ "8777539479abd7b3efeb691685415dc2b057d0e0" ], "author": { "name": "Abhilash Kesavan", "email": "a.kesavan@samsung.com", "time": "Wed Dec 11 17:27:05 2013 +0530" }, "committer": { "name": "Tomasz Figa", "email": "t.figa@samsung.com", "time": "Mon Dec 30 17:59:25 2013 +0100" }, "message": "clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg clock\n\nThe sysreg (system register) generates control signals for various blocks\nlike disp1blk, i2c, mipi, usb etc. However, it gets disabled as an unused\nclock at boot-up. This can lead to failures in operation of above blocks,\nbecause they can not be configured properly if this clock is disabled.\n\nSigned-off-by: Abhilash Kesavan \u003ca.kesavan@samsung.com\u003e\nAcked-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n[t.figa: Updated patch description.]\nSigned-off-by: Tomasz Figa \u003ct.figa@samsung.com\u003e\n" }, { "commit": "8fb9aeb7a71ef4f3e0613d459a2e1366a7a90469", "tree": "720d2c78a046930ebcea5f164654051fd7e4b083", "parents": [ "3bf34666a0cce5234ac677ed2fbe5cea82c71329" ], "author": { "name": "Abhilash Kesavan", "email": "a.kesavan@samsung.com", "time": "Thu Dec 12 08:32:01 2013 +0530" }, "committer": { "name": "Tomasz Figa", "email": "t.figa@samsung.com", "time": "Mon Dec 30 17:55:52 2013 +0100" }, "message": "clk: samsung: exynos5250: Add MDMA0 clocks\n\nAdds gate clock for MDMA0 on Exynos5250 SoC. This is needed to ensure\nthat the clock is enabled when MDMA0 is used on systems on which\nfirmware gates the clockby default.\n\nSigned-off-by: Abhilash Kesavan \u003ca.kesavan@samsung.com\u003e\nAcked-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n[t.figa: Updated patch description.]\nSigned-off-by: Tomasz Figa \u003ct.figa@samsung.com\u003e\n" }, { "commit": "3bf34666a0cce5234ac677ed2fbe5cea82c71329", "tree": "2b3b3bc1bb14008e43bd9d8de92caa8a690d62b5", "parents": [ "97c3557c3e0413efb1f021f582d1459760e22727" ], "author": { "name": "Abhilash Kesavan", "email": "a.kesavan@samsung.com", "time": "Thu Dec 12 08:32:00 2013 +0530" }, "committer": { "name": "Tomasz Figa", "email": "t.figa@samsung.com", "time": "Mon Dec 30 17:53:26 2013 +0100" }, "message": "clk: samsung: exynos5250: Fix ACP gate register offset\n\nThe CLK_GATE_IP_ACP register offset is incorrectly listed making\ndefinition of g2d clock incorrect, which may lead to system failures\nwhen trying to use G2D on systems on which firmware gates this clock\nby default. Fix this and the register ordering as well.\n\nSigned-off-by: Abhilash Kesavan \u003ca.kesavan@samsung.com\u003e\nAcked-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n[t.figa: Updated patch description.]\nSigned-off-by: Tomasz Figa \u003ct.figa@samsung.com\u003e\n" }, { "commit": "97c3557c3e0413efb1f021f582d1459760e22727", "tree": "d5328a3516aaf0f3b55740259011b4c9879adb92", "parents": [ "5fdd1b56be51b1ec4dbde5b213d649ac717442da" ], "author": { "name": "Andrew Bresticker", "email": "abrestic@chromium.org", "time": "Fri Nov 08 15:44:07 2013 +0530" }, "committer": { "name": "Tomasz Figa", "email": "t.figa@samsung.com", "time": "Mon Dec 30 17:53:22 2013 +0100" }, "message": "clk: exynos5250: fix sysmmu_mfc{l,r} gate clocks\n\nThe gate clocks for the MFC sysmmus appear to be flipped, i.e.\nGATE_IP_MFC[2] gates sysmmu_mfcl and GATE_IP_MFC[1] gates sysmmu_mfcr.\nFix this so that the MFC will start up.\n\nSigned-off-by: Andrew Bresticker \u003cabrestic@chromium.org\u003e\nSigned-off-by: Sachin Kamat \u003csachin.kamat@linaro.org\u003e\nAcked-by: Mike Turquette \u003cmturquette@linaro.org\u003e\nSigned-off-by: Tomasz Figa \u003ct.figa@samsung.com\u003e\n" }, { "commit": "5fdd1b56be51b1ec4dbde5b213d649ac717442da", "tree": "14ef5229999dbee0411f5cf3ba47a42713a9c848", "parents": [ "6ce4eac1f600b34f2f7f58f9cd8f0503d79e42ae" ], "author": { "name": "Seung-Woo Kim", "email": "sw0312.kim@samsung.com", "time": "Fri Nov 22 14:21:08 2013 +0900" }, "committer": { "name": "Tomasz Figa", "email": "t.figa@samsung.com", "time": "Mon Dec 30 17:53:18 2013 +0100" }, "message": "clk: samsung: exynos4: Correct SRC_MFC register\n\nThe SRC_MFC register offset was incorrect, which could cause have caused\nwrong calculation of rate of sclk_mfc clock, that could in turn lead to\nincorrect operation of MFC. This patch corrects it.\n\nSigned-off-by: Seung-Woo Kim \u003csw0312.kim@samsung.com\u003e\nAcked-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n[t.figa: Updated patch description]\nSigned-off-by: Tomasz Figa \u003ct.figa@samsung.com\u003e\n" }, { "commit": "6b71e0d9d6bfd24d2426a4ea7edf3c01d872903f", "tree": "e6304ae02ad41ab2620776a7b54cdf61b1e31546", "parents": [ "ea72dc2cf9552631e43327ce593bdbb0b9fdf058", "6f86341726cbec1921e925fd54a10c5b58e6f9f1" ], "author": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Sun Dec 29 13:37:56 2013 -0800" }, "committer": { "name": "Mike Turquette", "email": "mturquette@linaro.org", "time": "Sun Dec 29 13:37:56 2013 -0800" }, "message": "Merge tag \u0027sunxi-clk-3.14-for-mike\u0027 of https://bitbucket.org/emiliolopez/linux into clk-next-sunxi\n\nAllwinner sunXi SoCs clock changes\n\nThis contains the clk driver parts of the \"[PATCH v3 00/13] clk: sunxi:\nadd PLL5 and PLL6 support\" series. It adds support for PLL4/5/6 and\nmod0 clocks on most sunxi platforms. Additionally, it contains \"[PATCH\n1/4] clk: sunxi: Allwinner A20 output clock support\" (v2) from Chen-Yu\nTsai, which adds support for output clocks present on A20.\n" }, { "commit": "6f86341726cbec1921e925fd54a10c5b58e6f9f1", "tree": "ec7de73187cf68dd890e8e62dcab535e4434e052", "parents": [ "76192dc8873f724361c1bf8a90b37abc7dfed7ad" ], "author": { "name": "Chen-Yu Tsai", "email": "wens@csie.org", "time": "Tue Dec 24 21:26:17 2013 +0800" }, "committer": { "name": "Emilio López", "email": "emilio@elopez.com.ar", "time": "Sat Dec 28 17:14:21 2013 -0300" }, "message": "clk: sunxi: Allwinner A20 output clock support\n\nThis patch adds support for the external clock outputs on the\nAllwinner A20 SoC. The clock outputs are similar to \"module 0\"\ntype clocks, with different offsets and widths for clock factors.\n\nSigned-off-by: Chen-Yu Tsai \u003cwens@csie.org\u003e\nAcked-by: Emilio López \u003cemilio@elopez.com.ar\u003e\n" }, { "commit": "76192dc8873f724361c1bf8a90b37abc7dfed7ad", "tree": "9cdae88195f079955485df8fc290a955f5a97bb1", "parents": [ "7551769a225f3e600d6455e63ae00d51df37ff59" ], "author": { "name": "Emilio López", "email": "emilio@elopez.com.ar", "time": "Mon Dec 23 00:32:40 2013 -0300" }, "committer": { "name": "Emilio López", "email": "emilio@elopez.com.ar", "time": "Sat Dec 28 17:08:25 2013 -0300" }, "message": "clk: sunxi: support better factor DT nodes\n\nThe DT nodes should look like\n\n abc_clk: clk@deadbeef {\n ...\n clock-output-names \u003d \"abc\";\n }\n\nBut our old DT nodes look like\n\n abc: abc@deadbeef {\n ...\n }\n\nSo, let\u0027s support both formats, until we can transition everything\nto the new, correct one.\n\nSigned-off-by: Emilio López \u003cemilio@elopez.com.ar\u003e\nAcked-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "7551769a225f3e600d6455e63ae00d51df37ff59", "tree": "e2682fcc3bd43d228022be9be528f5ac58ab5046", "parents": [ "d584c1331d6421e2387eab10b11fa6f08b4a4b5f" ], "author": { "name": "Emilio López", "email": "emilio@elopez.com.ar", "time": "Mon Dec 23 00:32:39 2013 -0300" }, "committer": { "name": "Emilio López", "email": "emilio@elopez.com.ar", "time": "Sat Dec 28 17:08:22 2013 -0300" }, "message": "clk: sunxi: mod0 support\n\nThis commit implements support for the \"module 0\" type of clocks, as\nused by MMC, IR, NAND, SATA and other components.\n\nSigned-off-by: Emilio López \u003cemilio@elopez.com.ar\u003e\nAcked-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "d584c1331d6421e2387eab10b11fa6f08b4a4b5f", "tree": "7c1d6a78ae45ac0aed61a96ae856f9cd295f70a3", "parents": [ "5f4e0be3a72325fbc4d349a847cc9b2edd85b6d2" ], "author": { "name": "Emilio López", "email": "emilio@elopez.com.ar", "time": "Mon Dec 23 00:32:37 2013 -0300" }, "committer": { "name": "Emilio López", "email": "emilio@elopez.com.ar", "time": "Sat Dec 28 17:08:17 2013 -0300" }, "message": "clk: sunxi: add PLL5 and PLL6 support\n\nThis commit implements PLL5 and PLL6 support on the sunxi clock driver.\nThese PLLs use a similar factor clock, but differ on their outputs.\n\nSigned-off-by: Emilio López \u003cemilio@elopez.com.ar\u003e\nAcked-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "5f4e0be3a72325fbc4d349a847cc9b2edd85b6d2", "tree": "9e7527380efe41f1f97ae7ffb65ddc877da40f79", "parents": [ "d838ff33ec3a6262f44476d8edc0303acdc16580" ], "author": { "name": "Emilio López", "email": "emilio@elopez.com.ar", "time": "Mon Dec 23 00:32:36 2013 -0300" }, "committer": { "name": "Emilio López", "email": "emilio@elopez.com.ar", "time": "Sat Dec 28 17:08:14 2013 -0300" }, "message": "clk: sunxi: make factors_clk_setup return the clock it registers\n\nWe will be needing this to register a factor clock as parent with leaf\ndivisors on a single call.\n\nSigned-off-by: Emilio López \u003cemilio@elopez.com.ar\u003e\nAcked-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "d838ff33ec3a6262f44476d8edc0303acdc16580", "tree": "0c700acae95db629e0e085bc4608752e4f77b515", "parents": [ "edaf3fb580df7f6c510699664f51485030a29f17" ], "author": { "name": "Emilio López", "email": "emilio@elopez.com.ar", "time": "Mon Dec 23 00:32:34 2013 -0300" }, "committer": { "name": "Emilio López", "email": "emilio@elopez.com.ar", "time": "Sat Dec 28 17:08:06 2013 -0300" }, "message": "clk: sunxi: add gating support to PLL1\n\nThis commit adds gating support to PLL1 on the clock driver. This makes\nthe PLL1 implementation fully compatible with PLL4 as well.\n\nSigned-off-by: Emilio López \u003cemilio@elopez.com.ar\u003e\nAcked-by: Maxime Ripard \u003cmaxime.ripard@free-electrons.com\u003e\nAcked-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" }, { "commit": "edaf3fb580df7f6c510699664f51485030a29f17", "tree": "9172b45af0755f07555d888ef8a53370ccd92ac3", "parents": [ "40a5dcba4e79023f0b511dc0ca498bdf9eacb5db" ], "author": { "name": "Emilio López", "email": "emilio@elopez.com.ar", "time": "Mon Dec 23 00:32:33 2013 -0300" }, "committer": { "name": "Emilio López", "email": "emilio@elopez.com.ar", "time": "Sat Dec 28 17:08:00 2013 -0300" }, "message": "clk: sunxi: clean the magic number of mux parents\n\nThis was pointed out during the review of the factor patches. Let\u0027s\nindicate what does that magic 5 mean.\n\nSigned-off-by: Emilio López \u003cemilio@elopez.com.ar\u003e\nAcked-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n" } ], "next": "40a5dcba4e79023f0b511dc0ca498bdf9eacb5db" }