)]}' { "log": [ { "commit": "70ef2601feb09d40f4086d055700b7923b3c2d6f", "tree": "b4c86449ec00d280eaf9b0003ac8680e472ee3dc", "parents": [ "d4af0e9d6eef6ce53c1935ca6ee3c01889e3212d" ], "author": { "name": "Jussi Kivilinna", "email": "jussi.kivilinna@mbnet.fi", "time": "Mon Jun 18 14:07:50 2012 +0300" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Wed Jun 27 14:42:03 2012 +0800" }, "message": "crypto: move arch/x86/include/asm/aes.h to arch/x86/include/asm/crypto/\n\nMove AES header to the new asm/crypto directory.\n\nSigned-off-by: Jussi Kivilinna \u003cjussi.kivilinna@mbnet.fi\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "d4af0e9d6eef6ce53c1935ca6ee3c01889e3212d", "tree": "5c9d83cb6b5a28fa11e32092cb4a3ec69da92ca8", "parents": [ "a7378d4e552ac139ae1cbbdfebfeaa9b18c948d0" ], "author": { "name": "Jussi Kivilinna", "email": "jussi.kivilinna@mbnet.fi", "time": "Mon Jun 18 14:07:45 2012 +0300" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Wed Jun 27 14:42:02 2012 +0800" }, "message": "crypto: move arch/x86/include/asm/serpent-{sse2|avx}.h to arch/x86/include/asm/crypto/\n\nMove serpent crypto headers to the new asm/crypto/ directory.\n\nSigned-off-by: Jussi Kivilinna \u003cjussi.kivilinna@mbnet.fi\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "a7378d4e552ac139ae1cbbdfebfeaa9b18c948d0", "tree": "dc8960d5ce50ac27f05e02151c7744bb313286b4", "parents": [ "414cb5e7cc6e258fe36e2c3cc3ef1ff2e246c0e3" ], "author": { "name": "Jussi Kivilinna", "email": "jussi.kivilinna@mbnet.fi", "time": "Mon Jun 18 14:07:39 2012 +0300" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Wed Jun 27 14:42:02 2012 +0800" }, "message": "crypto: twofish-avx - remove duplicated glue code and use shared glue code from glue_helper\n\nNow that shared glue code is available, convert twofish-avx to use it.\n\nCc: Johannes Goetzfried \u003cJohannes.Goetzfried@informatik.stud.uni-erlangen.de\u003e\nSigned-off-by: Jussi Kivilinna \u003cjussi.kivilinna@mbnet.fi\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "414cb5e7cc6e258fe36e2c3cc3ef1ff2e246c0e3", "tree": "bce5793f8d0e9791ea60d09192d74b482b9a6cfd", "parents": [ "964263afdcbf9d1e85c021acfff0cc68dd168475" ], "author": { "name": "Jussi Kivilinna", "email": "jussi.kivilinna@mbnet.fi", "time": "Mon Jun 18 14:07:34 2012 +0300" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Wed Jun 27 14:42:02 2012 +0800" }, "message": "crypto: twofish-x86_64-3way - remove duplicated glue code and use shared glue code from glue_helper\n\nNow that shared glue code is available, convert twofish-x86_64-3way to use it.\n\nSigned-off-by: Jussi Kivilinna \u003cjussi.kivilinna@mbnet.fi\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "964263afdcbf9d1e85c021acfff0cc68dd168475", "tree": "6a9972203d7fa212547aa1bc89098e72fc536c97", "parents": [ "1d0debbd4671a8d302a11837a126d5f87db16bdc" ], "author": { "name": "Jussi Kivilinna", "email": "jussi.kivilinna@mbnet.fi", "time": "Mon Jun 18 14:07:29 2012 +0300" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Wed Jun 27 14:42:02 2012 +0800" }, "message": "crypto: camellia-x86_64 - remove duplicated glue code and use shared glue code from glue_helper\n\nNow that shared glue code is available, convert camellia-x86_64 to use it.\n\nSigned-off-by: Jussi Kivilinna \u003cjussi.kivilinna@mbnet.fi\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "1d0debbd4671a8d302a11837a126d5f87db16bdc", "tree": "8bd1032627c7b2bbec8b4bdf86bd9dc39599130c", "parents": [ "596d875052dac6bf084f0c3a3e946fb4709b727b" ], "author": { "name": "Jussi Kivilinna", "email": "jussi.kivilinna@mbnet.fi", "time": "Mon Jun 18 14:07:24 2012 +0300" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Wed Jun 27 14:42:01 2012 +0800" }, "message": "crypto: serpent-avx: remove duplicated glue code and use shared glue code from glue_helper\n\nNow that shared glue code is available, convert serpent-avx to use it.\n\nCc: Johannes Goetzfried \u003cJohannes.Goetzfried@informatik.stud.uni-erlangen.de\u003e\nSigned-off-by: Jussi Kivilinna \u003cjussi.kivilinna@mbnet.fi\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "596d875052dac6bf084f0c3a3e946fb4709b727b", "tree": "bd5bf090efd70b60d1c26c1ca7b6a559cbcf72b2", "parents": [ "e81792fbc2a6fa4969f724b959829667fb2d4f01" ], "author": { "name": "Jussi Kivilinna", "email": "jussi.kivilinna@mbnet.fi", "time": "Mon Jun 18 14:07:19 2012 +0300" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Wed Jun 27 14:42:01 2012 +0800" }, "message": "crypto: serpent-sse2 - split generic glue code to new helper module\n\nNow that serpent-sse2 glue code has been made generic, it can be split to\nseparate module.\n\nSigned-off-by: Jussi Kivilinna \u003cjussi.kivilinna@mbnet.fi\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "e81792fbc2a6fa4969f724b959829667fb2d4f01", "tree": "20e435e725e8ffca406ffb262c91552efd9dd952", "parents": [ "a9629d7142ea22567eaa999232d8a31a7493665a" ], "author": { "name": "Jussi Kivilinna", "email": "jussi.kivilinna@mbnet.fi", "time": "Mon Jun 18 14:07:14 2012 +0300" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Wed Jun 27 14:42:01 2012 +0800" }, "message": "crypto: serpent-sse2 - prepare serpent-sse2 glue code into generic x86 glue code for 128bit block ciphers\n\nBlock cipher implementations in arch/x86/crypto/ contain common glue code that\nis currently duplicated in each module (camellia-x86_64, twofish-x86_64-3way,\ntwofish-avx, serpent-sse2 and serpent-avx). This patch prepares serpent-sse2\nglue into generic glue code for all 128bit block ciphers to use in\narch/x86/crypto.\n\nSigned-off-by: Jussi Kivilinna \u003cjussi.kivilinna@mbnet.fi\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "a9629d7142ea22567eaa999232d8a31a7493665a", "tree": "6693434c4fa675478f7c3bca469f29b22670f713", "parents": [ "30a04008827b58c4aafbd1d6a27d6b6ed239e993" ], "author": { "name": "Jussi Kivilinna", "email": "jussi.kivilinna@mbnet.fi", "time": "Mon Jun 18 14:07:08 2012 +0300" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Wed Jun 27 14:42:01 2012 +0800" }, "message": "crypto: aes_ni - change to use shared ablk_* functions\n\nRemove duplicate ablk_* functions and make use of ablk_helper module instead.\n\nSigned-off-by: Jussi Kivilinna \u003cjussi.kivilinna@mbnet.fi\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "30a04008827b58c4aafbd1d6a27d6b6ed239e993", "tree": "7c1cb4ead62efb278c0d0154f5fcc08c8ace90bb", "parents": [ "ffaf9156320a077ebf9c5b9a5cf987689dc1a6b3" ], "author": { "name": "Jussi Kivilinna", "email": "jussi.kivilinna@mbnet.fi", "time": "Mon Jun 18 14:07:03 2012 +0300" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Wed Jun 27 14:42:01 2012 +0800" }, "message": "crypto: twofish-avx - change to use shared ablk_* functions\n\nRemove duplicate ablk_* functions and make use of ablk_helper module instead.\n\nSigned-off-by: Jussi Kivilinna \u003cjussi.kivilinna@mbnet.fi\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "ffaf9156320a077ebf9c5b9a5cf987689dc1a6b3", "tree": "22a3602bdedfc8809ff09bc9241b98ae3264ff13", "parents": [ "7c76bdd7c3baf6d2431bb801f5b11d2ac195fdd6" ], "author": { "name": "Jussi Kivilinna", "email": "jussi.kivilinna@mbnet.fi", "time": "Mon Jun 18 14:06:58 2012 +0300" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Wed Jun 27 14:42:00 2012 +0800" }, "message": "crypto: ablk_helper - move ablk_* functions from serpent-sse2/avx glue code to shared module\n\nMove ablk-* functions to separate module to share common code between cipher\nimplementations.\n\nSigned-off-by: Jussi Kivilinna \u003cjussi.kivilinna@mbnet.fi\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "3387e7d69048f5ab02729825f9611754850d9a87", "tree": "d7468f1d4a72dc1282a04c6f5bc5953be2b7bdad", "parents": [ "d366db605c8c4a9878589bc4a87e55f6063184ac" ], "author": { "name": "Jussi Kivilinna", "email": "jussi.kivilinna@mbnet.fi", "time": "Thu Jun 14 10:09:03 2012 +0800" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Thu Jun 14 10:09:03 2012 +0800" }, "message": "crypto: serpent-sse2/avx - allow both to be built into kernel\n\nRename serpent-avx assembler functions so that they do not collide with\nserpent-sse2 assembler functions when linking both versions in to same\nkernel image.\n\nReported-by: Randy Dunlap \u003crdunlap@xenotime.net\u003e\nCc: Johannes Goetzfried \u003cJohannes.Goetzfried@informatik.stud.uni-erlangen.de\u003e\nSigned-off-by: Jussi Kivilinna \u003cjussi.kivilinna@mbnet.fi\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "7efe4076725aeb01722445b56613681aa492c8d6", "tree": "138a24608d523e9794012586a904be0360cfebce", "parents": [ "4da7de4d8be7d18559c56bca446b1161a3b63acc" ], "author": { "name": "Johannes Goetzfried", "email": "Johannes.Goetzfried@informatik.stud.uni-erlangen.de", "time": "Tue Jun 12 16:47:43 2012 +0800" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Tue Jun 12 16:47:43 2012 +0800" }, "message": "crypto: serpent - add x86_64/avx assembler implementation\n\nThis patch adds a x86_64/avx assembler implementation of the Serpent block\ncipher. The implementation is very similar to the sse2 implementation and\nprocesses eight blocks in parallel. Because of the new non-destructive three\noperand syntax all move-instructions can be removed and therefore a little\nperformance increase is provided.\n\nPatch has been tested with tcrypt and automated filesystem tests.\n\nTcrypt benchmark results:\n\nIntel Core i5-2500 CPU (fam:6, model:42, step:7)\n\nserpent-avx-x86_64 vs. serpent-sse2-x86_64\n128bit key: (lrw:256bit) (xts:256bit)\nsize ecb-enc ecb-dec cbc-enc cbc-dec ctr-enc ctr-dec lrw-enc lrw-dec xts-enc xts-dec\n16B 1.03x 1.01x 1.01x 1.01x 1.00x 1.00x 1.00x 1.00x 1.00x 1.01x\n64B 1.00x 1.00x 1.00x 1.00x 1.00x 0.99x 1.00x 1.01x 1.00x 1.00x\n256B 1.05x 1.03x 1.00x 1.02x 1.05x 1.06x 1.05x 1.02x 1.05x 1.02x\n1024B 1.05x 1.02x 1.00x 1.02x 1.05x 1.06x 1.05x 1.03x 1.05x 1.02x\n8192B 1.05x 1.02x 1.00x 1.02x 1.06x 1.06x 1.04x 1.03x 1.04x 1.02x\n\n256bit key: (lrw:384bit) (xts:512bit)\nsize ecb-enc ecb-dec cbc-enc cbc-dec ctr-enc ctr-dec lrw-enc lrw-dec xts-enc xts-dec\n16B 1.01x 1.00x 1.01x 1.01x 1.00x 1.00x 0.99x 1.03x 1.01x 1.01x\n64B 1.00x 1.00x 1.00x 1.00x 1.00x 1.00x 1.00x 1.01x 1.00x 1.02x\n256B 1.05x 1.02x 1.00x 1.02x 1.05x 1.02x 1.04x 1.05x 1.05x 1.02x\n1024B 1.06x 1.02x 1.00x 1.02x 1.07x 1.06x 1.05x 1.04x 1.05x 1.02x\n8192B 1.05x 1.02x 1.00x 1.02x 1.06x 1.06x 1.04x 1.05x 1.05x 1.02x\n\nserpent-avx-x86_64 vs aes-asm (8kB block):\n 128bit 256bit\necb-enc 1.26x 1.73x\necb-dec 1.20x 1.64x\ncbc-enc 0.33x 0.45x\ncbc-dec 1.24x 1.67x\nctr-enc 1.32x 1.76x\nctr-dec 1.32x 1.76x\nlrw-enc 1.20x 1.60x\nlrw-dec 1.15x 1.54x\nxts-enc 1.22x 1.64x\nxts-dec 1.17x 1.57x\n\nSigned-off-by: Johannes Goetzfried \u003cJohannes.Goetzfried@informatik.stud.uni-erlangen.de\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "107778b592576c0c8e8d2ca7a2aa5415a4908223", "tree": "0e07f6abd2acaf69bf25efacf520584d748c860b", "parents": [ "4d03c5047a07a62563e1a8fa798ea258f048bfde" ], "author": { "name": "Johannes Goetzfried", "email": "Johannes.Goetzfried@informatik.stud.uni-erlangen.de", "time": "Mon May 28 15:54:24 2012 +0200" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Tue Jun 12 16:46:07 2012 +0800" }, "message": "crypto: twofish - add x86_64/avx assembler implementation\n\nThis patch adds a x86_64/avx assembler implementation of the Twofish block\ncipher. The implementation processes eight blocks in parallel (two 4 block\nchunk AVX operations). The table-lookups are done in general-purpose registers.\nFor small blocksizes the 3way-parallel functions from the twofish-x86_64-3way\nmodule are called. A good performance increase is provided for blocksizes\ngreater or equal to 128B.\n\nPatch has been tested with tcrypt and automated filesystem tests.\n\nTcrypt benchmark results:\n\nIntel Core i5-2500 CPU (fam:6, model:42, step:7)\n\ntwofish-avx-x86_64 vs. twofish-x86_64-3way\n128bit key: (lrw:256bit) (xts:256bit)\nsize ecb-enc ecb-dec cbc-enc cbc-dec ctr-enc ctr-dec lrw-enc lrw-dec xts-enc xts-dec\n16B 0.96x 0.97x 1.00x 0.95x 0.97x 0.97x 0.96x 0.95x 0.95x 0.98x\n64B 0.99x 0.99x 1.00x 0.99x 0.98x 0.98x 0.99x 0.98x 0.99x 0.98x\n256B 1.20x 1.21x 1.00x 1.19x 1.15x 1.14x 1.19x 1.20x 1.18x 1.19x\n1024B 1.29x 1.30x 1.00x 1.28x 1.23x 1.24x 1.26x 1.28x 1.26x 1.27x\n8192B 1.31x 1.32x 1.00x 1.31x 1.25x 1.25x 1.28x 1.29x 1.28x 1.30x\n\n256bit key: (lrw:384bit) (xts:512bit)\nsize ecb-enc ecb-dec cbc-enc cbc-dec ctr-enc ctr-dec lrw-enc lrw-dec xts-enc xts-dec\n16B 0.96x 0.96x 1.00x 0.96x 0.97x 0.98x 0.95x 0.95x 0.95x 0.96x\n64B 1.00x 0.99x 1.00x 0.98x 0.98x 1.01x 0.98x 0.98x 0.98x 0.98x\n256B 1.20x 1.21x 1.00x 1.21x 1.15x 1.15x 1.19x 1.20x 1.18x 1.19x\n1024B 1.29x 1.30x 1.00x 1.28x 1.23x 1.23x 1.26x 1.27x 1.26x 1.27x\n8192B 1.31x 1.33x 1.00x 1.31x 1.26x 1.26x 1.29x 1.29x 1.28x 1.30x\n\ntwofish-avx-x86_64 vs aes-asm (8kB block):\n 128bit 256bit\necb-enc 1.19x 1.63x\necb-dec 1.18x 1.62x\ncbc-enc 0.75x 1.03x\ncbc-dec 1.23x 1.67x\nctr-enc 1.24x 1.65x\nctr-dec 1.24x 1.65x\nlrw-enc 1.15x 1.53x\nlrw-dec 1.14x 1.52x\nxts-enc 1.16x 1.56x\nxts-dec 1.16x 1.56x\n\nSigned-off-by: Johannes Goetzfried \u003cJohannes.Goetzfried@informatik.stud.uni-erlangen.de\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "65df57743924c3d13e1fa1bcf5bf70fe874fcdfd", "tree": "122291d27b0ea9aeed2e1e454a62f83a8aed3aa5", "parents": [ "4e3c8a1b1c63482403e9d5e3148dee1a711e4b91" ], "author": { "name": "Mathias Krause", "email": "minipli@googlemail.com", "time": "Thu May 24 11:13:42 2012 +0200" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Tue Jun 12 16:37:16 2012 +0800" }, "message": "crypto: sha1 - use Kbuild supplied flags for AVX test\n\nCommit ea4d26ae (\"raid5: add AVX optimized RAID5 checksumming\")\nintroduced x86/ arch wide defines for AFLAGS and CFLAGS indicating AVX\nsupport in binutils based on the same test we have in x86/crypto/ right\nnow. To minimize duplication drop our implementation in favour to the\none in x86/.\n\nSigned-off-by: Mathias Krause \u003cminipli@googlemail.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "7c8d51848a88aafdb68f42b6b650c83485ea2f84", "tree": "7d8ed09c28d44f7b66d8c81695f7af77d43d7794", "parents": [ "121daad8fd1dce63076fa55aaedd5dc3f981b334" ], "author": { "name": "Mathias Krause", "email": "minipli@googlemail.com", "time": "Wed May 30 01:43:08 2012 +0200" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Thu May 31 20:53:22 2012 +1000" }, "message": "crypto: aesni-intel - fix unaligned cbc decrypt for x86-32\n\nThe 32 bit variant of cbc(aes) decrypt is using instructions requiring\n128 bit aligned memory locations but fails to ensure this constraint in\nthe code. Fix this by loading the data into intermediate registers with\nload unaligned instructions.\n\nThis fixes reported general protection faults related to aesni.\n\nReferences: https://bugzilla.kernel.org/show_bug.cgi?id\u003d43223\nReported-by: Daniel \u003cgarkein@mailueberfall.de\u003e\nCc: stable@kernel.org [v2.6.39+]\nSigned-off-by: Mathias Krause \u003cminipli@googlemail.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "ef45b834319f8a18f257a40ba4bce6b829ef1708", "tree": "896c13f5b76fe9d0dd1e7bd8fd1c6b71f4bcca89", "parents": [ "fa46ccb8eb960c62c1e5e3237085d4007788a345" ], "author": { "name": "Jussi Kivilinna", "email": "jussi.kivilinna@mbnet.fi", "time": "Fri May 11 16:00:54 2012 +0300" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Tue May 15 17:25:33 2012 +1000" }, "message": "crypto: aesni-intel - move more common code to ablk_init_common\n\nablk_*_init functions share more common code than what is currently in\nablk_init_common. Move all of the common code to ablk_init_common.\n\nCc: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Jussi Kivilinna \u003cjussi.kivilinna@mbnet.fi\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "fa46ccb8eb960c62c1e5e3237085d4007788a345", "tree": "228c0a3bc949062fd1b0cf659656eeecbb574105", "parents": [ "d1cbb1447bca8eaa28b7a384365932b49c47811f" ], "author": { "name": "Jussi Kivilinna", "email": "jussi.kivilinna@mbnet.fi", "time": "Fri May 11 16:00:48 2012 +0300" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Tue May 15 17:25:33 2012 +1000" }, "message": "crypto: aesni-intel - use crypto_[un]register_algs\n\nCombine all crypto_alg to be registered and use new crypto_[un]register_algs\nfunctions. Simplifies init/exit code and reduce object size.\n\nCc: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Jussi Kivilinna \u003cjussi.kivilinna@mbnet.fi\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "6a76a6992341faab0ef31e7d97000e0cf336d0ba", "tree": "a585bf55b557ad746ff951119feb0a8bd014de08", "parents": [ "d4c6fa73fe984e504d52f3d6bba291fd76fe49f7", "ff0a70fe053614e763eb3ac88bfea9c5615fce3b" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Mar 22 20:19:30 2012 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Mar 22 20:19:30 2012 -0700" }, "message": "Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6\n\nPull crypto fixes from Herbert Xu:\n \"This fixes a build problem where two crypto modules both try to export\n the same symbols (which shouldn\u0027t have been exported in the first\n place).\"\n\n* git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6:\n crypto: twofish-x86_64-3way - module init/exit functions should be static\n crypto: camellia-x86_64 - module init/exit functions should be static\n" }, { "commit": "ff0a70fe053614e763eb3ac88bfea9c5615fce3b", "tree": "1575b70793ba17c26ebbed08c7799dc9b978d62a", "parents": [ "676a38046f4fba4e7418756c6f6fc25cf5976312" ], "author": { "name": "Jussi Kivilinna", "email": "jussi.kivilinna@mbnet.fi", "time": "Thu Mar 15 22:11:57 2012 +0200" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Thu Mar 22 09:17:45 2012 +0800" }, "message": "crypto: twofish-x86_64-3way - module init/exit functions should be static\n\nThis caused conflict with camellia-x86_64 when compiled into kernel, same\nfunction names and not static.\n\nReported-by: Randy Dunlap \u003crdunlap@xenotime.net\u003e\nSigned-off-by: Jussi Kivilinna \u003cjussi.kivilinna@mbnet.fi\u003e\nAcked-by: Randy Dunlap \u003crdunlap@xenotime.net\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "676a38046f4fba4e7418756c6f6fc25cf5976312", "tree": "0775b953b23538b7c989ae1b14e9aced39b1bf41", "parents": [ "2dc9b5dbdef09840de852a4f0cc6a9c9eece7220" ], "author": { "name": "Jussi Kivilinna", "email": "jussi.kivilinna@mbnet.fi", "time": "Thu Mar 15 22:11:51 2012 +0200" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Thu Mar 22 09:17:44 2012 +0800" }, "message": "crypto: camellia-x86_64 - module init/exit functions should be static\n\nThis caused conflict with twofish-x86_64-3way when compiled into kernel,\nsame function names and not static.\n\nReported-by: Randy Dunlap \u003crdunlap@xenotime.net\u003e\nSigned-off-by: Jussi Kivilinna \u003cjussi.kivilinna@mbnet.fi\u003e\nAcked-by: Randy Dunlap \u003crdunlap@xenotime.net\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "b8716614a7cc2fc15ea2a518edd04755fb08d922", "tree": "2a8a5d04066b2bd589ba2ebbeb228e2a6a178ec9", "parents": [ "31f6765266417c0d99f0e922fe82848a7c9c2ae9", "2dc9b5dbdef09840de852a4f0cc6a9c9eece7220" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Mar 21 13:20:43 2012 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Mar 21 13:20:43 2012 -0700" }, "message": "Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6\n\nPull crypto update from Herbert Xu:\n \"* sha512 bug fixes (already in your tree).\n * SHA224/SHA384 AEAD support in caam.\n * X86-64 optimised version of Camellia.\n * Tegra AES support.\n * Bulk algorithm registration interface to make driver registration easier.\n * padata race fixes.\n * Misc fixes.\"\n\n* git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (31 commits)\n padata: Fix race on sequence number wrap\n padata: Fix race in the serialization path\n crypto: camellia - add assembler implementation for x86_64\n crypto: camellia - rename camellia.c to camellia_generic.c\n crypto: camellia - fix checkpatch warnings\n crypto: camellia - rename camellia module to camellia_generic\n crypto: tcrypt - add more camellia tests\n crypto: testmgr - add more camellia test vectors\n crypto: camellia - simplify key setup and CAMELLIA_ROUNDSM macro\n crypto: twofish-x86_64/i586 - set alignmask to zero\n crypto: blowfish-x86_64 - set alignmask to zero\n crypto: serpent-sse2 - combine ablk_*_init functions\n crypto: blowfish-x86_64 - use crypto_[un]register_algs\n crypto: twofish-x86_64-3way - use crypto_[un]register_algs\n crypto: serpent-sse2 - use crypto_[un]register_algs\n crypto: serpent-sse2 - remove dead code from serpent_sse2_glue.c::serpent_sse2_init()\n crypto: twofish-x86 - Remove dead code from twofish_glue_3way.c::init()\n crypto: In crypto_add_alg(), \u0027exact\u0027 wants to be initialized to 0\n crypto: caam - fix gcc 4.6 warning\n crypto: Add bulk algorithm registration interface\n ...\n" }, { "commit": "9f3938346a5c1fa504647670edb5fea5756cfb00", "tree": "7cf6d24d6b076c8db8571494984924cac03703a2", "parents": [ "69a7aebcf019ab3ff5764525ad6858fbe23bb86d", "317b6e128247f75976b0fc2b9fd8d2c20ef13b3a" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Mar 21 09:40:26 2012 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Mar 21 09:40:26 2012 -0700" }, "message": "Merge branch \u0027kmap_atomic\u0027 of git://github.com/congwang/linux\n\nPull kmap_atomic cleanup from Cong Wang.\n\nIt\u0027s been in -next for a long time, and it gets rid of the (no longer\nused) second argument to k[un]map_atomic().\n\nFix up a few trivial conflicts in various drivers, and do an \"evil\nmerge\" to catch some new uses that have come in since Cong\u0027s tree.\n\n* \u0027kmap_atomic\u0027 of git://github.com/congwang/linux: (59 commits)\n feature-removal-schedule.txt: schedule the deprecated form of kmap_atomic() for removal\n highmem: kill all __kmap_atomic() [swarren@nvidia.com: highmem: Fix ARM build break due to __kmap_atomic rename]\n drbd: remove the second argument of k[un]map_atomic()\n zcache: remove the second argument of k[un]map_atomic()\n gma500: remove the second argument of k[un]map_atomic()\n dm: remove the second argument of k[un]map_atomic()\n tomoyo: remove the second argument of k[un]map_atomic()\n sunrpc: remove the second argument of k[un]map_atomic()\n rds: remove the second argument of k[un]map_atomic()\n net: remove the second argument of k[un]map_atomic()\n mm: remove the second argument of k[un]map_atomic()\n lib: remove the second argument of k[un]map_atomic()\n power: remove the second argument of k[un]map_atomic()\n kdb: remove the second argument of k[un]map_atomic()\n udf: remove the second argument of k[un]map_atomic()\n ubifs: remove the second argument of k[un]map_atomic()\n squashfs: remove the second argument of k[un]map_atomic()\n reiserfs: remove the second argument of k[un]map_atomic()\n ocfs2: remove the second argument of k[un]map_atomic()\n ntfs: remove the second argument of k[un]map_atomic()\n ...\n" }, { "commit": "8fd75e1216e0ba601a746177e6c102d5593b572f", "tree": "d9f8e867ccec9ecaa2b77616a01c1c3d0875d76e", "parents": [ "91f2359396d87f24ea43d91ff77dec54847ad69a" ], "author": { "name": "Cong Wang", "email": "amwang@redhat.com", "time": "Fri Nov 25 23:14:17 2011 +0800" }, "committer": { "name": "Cong Wang", "email": "xiyou.wangcong@gmail.com", "time": "Tue Mar 20 21:48:15 2012 +0800" }, "message": "x86: remove the second argument of k[un]map_atomic()\n\nAcked-by: Avi Kivity \u003cavi@redhat.com\u003e\nAcked-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\nSigned-off-by: Cong Wang \u003camwang@redhat.com\u003e\n" }, { "commit": "0b95ec56ae19f61ca664e83766a2180057f0e351", "tree": "dc9b3ee4116b807df10b5832b37d49468d69f3b2", "parents": [ "617ae7c7a1ac04c1d3e4b22add6dfb53b0fd0675" ], "author": { "name": "Jussi Kivilinna", "email": "jussi.kivilinna@mbnet.fi", "time": "Mon Mar 05 20:26:47 2012 +0200" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Wed Mar 14 17:25:56 2012 +0800" }, "message": "crypto: camellia - add assembler implementation for x86_64\n\nPatch adds x86_64 assembler implementation of Camellia block cipher. Two set of\nfunctions are provided. First set is regular \u0027one-block at time\u0027 encrypt/decrypt\nfunctions. Second is \u0027two-block at time\u0027 functions that gain performance increase\non out-of-order CPUs. Performance of 2-way functions should be equal to 1-way\nfunctions with in-order CPUs.\n\nPatch has been tested with tcrypt and automated filesystem tests.\n\nTcrypt benchmark results:\n\nAMD Phenom II 1055T (fam:16, model:10):\n\ncamellia-asm vs camellia_generic:\n128bit key: (lrw:256bit) (xts:256bit)\nsize ecb-enc ecb-dec cbc-enc cbc-dec ctr-enc ctr-dec lrw-enc lrw-dec xts-enc xts-dec\n16B 1.27x 1.22x 1.30x 1.42x 1.30x 1.34x 1.19x 1.05x 1.23x 1.24x\n64B 1.74x 1.79x 1.43x 1.87x 1.81x 1.87x 1.48x 1.38x 1.55x 1.62x\n256B 1.90x 1.87x 1.43x 1.94x 1.94x 1.95x 1.63x 1.62x 1.67x 1.70x\n1024B 1.96x 1.93x 1.43x 1.95x 1.98x 2.01x 1.67x 1.69x 1.74x 1.80x\n8192B 1.96x 1.96x 1.39x 1.93x 2.01x 2.03x 1.72x 1.64x 1.71x 1.76x\n\n256bit key: (lrw:384bit) (xts:512bit)\nsize ecb-enc ecb-dec cbc-enc cbc-dec ctr-enc ctr-dec lrw-enc lrw-dec xts-enc xts-dec\n16B 1.23x 1.23x 1.33x 1.39x 1.34x 1.38x 1.04x 1.18x 1.21x 1.29x\n64B 1.72x 1.69x 1.42x 1.78x 1.81x 1.89x 1.57x 1.52x 1.56x 1.65x\n256B 1.85x 1.88x 1.42x 1.86x 1.93x 1.96x 1.69x 1.65x 1.70x 1.75x\n1024B 1.88x 1.86x 1.45x 1.95x 1.96x 1.95x 1.77x 1.71x 1.77x 1.78x\n8192B 1.91x 1.86x 1.42x 1.91x 2.03x 1.98x 1.73x 1.71x 1.78x 1.76x\n\ncamellia-asm vs aes-asm (8kB block):\n 128bit 256bit\necb-enc 1.15x 1.22x\necb-dec 1.16x 1.16x\ncbc-enc 0.85x 0.90x\ncbc-dec 1.20x 1.23x\nctr-enc 1.28x 1.30x\nctr-dec 1.27x 1.28x\nlrw-enc 1.12x 1.16x\nlrw-dec 1.08x 1.10x\nxts-enc 1.11x 1.15x\nxts-dec 1.14x 1.15x\n\nIntel Core2 T8100 (fam:6, model:23, step:6):\n\ncamellia-asm vs camellia_generic:\n128bit key: (lrw:256bit) (xts:256bit)\nsize ecb-enc ecb-dec cbc-enc cbc-dec ctr-enc ctr-dec lrw-enc lrw-dec xts-enc xts-dec\n16B 1.10x 1.12x 1.14x 1.16x 1.16x 1.15x 1.02x 1.02x 1.08x 1.08x\n64B 1.61x 1.60x 1.17x 1.68x 1.67x 1.66x 1.43x 1.42x 1.44x 1.42x\n256B 1.65x 1.73x 1.17x 1.77x 1.81x 1.80x 1.54x 1.53x 1.58x 1.54x\n1024B 1.76x 1.74x 1.18x 1.80x 1.85x 1.85x 1.60x 1.59x 1.65x 1.60x\n8192B 1.77x 1.75x 1.19x 1.81x 1.85x 1.86x 1.63x 1.61x 1.66x 1.62x\n\n256bit key: (lrw:384bit) (xts:512bit)\nsize ecb-enc ecb-dec cbc-enc cbc-dec ctr-enc ctr-dec lrw-enc lrw-dec xts-enc xts-dec\n16B 1.10x 1.07x 1.13x 1.16x 1.11x 1.16x 1.03x 1.02x 1.08x 1.07x\n64B 1.61x 1.62x 1.15x 1.66x 1.63x 1.68x 1.47x 1.46x 1.47x 1.44x\n256B 1.71x 1.70x 1.16x 1.75x 1.69x 1.79x 1.58x 1.57x 1.59x 1.55x\n1024B 1.78x 1.72x 1.17x 1.75x 1.80x 1.80x 1.63x 1.62x 1.65x 1.62x\n8192B 1.76x 1.73x 1.17x 1.78x 1.80x 1.81x 1.64x 1.62x 1.68x 1.64x\n\ncamellia-asm vs aes-asm (8kB block):\n 128bit 256bit\necb-enc 1.17x 1.21x\necb-dec 1.17x 1.20x\ncbc-enc 0.80x 0.82x\ncbc-dec 1.22x 1.24x\nctr-enc 1.25x 1.26x\nctr-dec 1.25x 1.26x\nlrw-enc 1.14x 1.18x\nlrw-dec 1.13x 1.17x\nxts-enc 1.14x 1.18x\nxts-dec 1.14x 1.17x\n\nSigned-off-by: Jussi Kivilinna \u003cjussi.kivilinna@mbnet.fi\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "894042648902d11d579af2a936a5a9a43cd5f1e4", "tree": "1a2bb99c14f2fb69c4d622fbfdfd528a136f6d9a", "parents": [ "919e2c32496aec4170bd67e64efd526dd0a9bbdc" ], "author": { "name": "Jussi Kivilinna", "email": "jussi.kivilinna@mbnet.fi", "time": "Fri Feb 17 22:49:03 2012 +0200" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Sat Feb 25 17:20:24 2012 +0800" }, "message": "crypto: twofish-x86_64/i586 - set alignmask to zero\n\nx86 has fast unaligned accesses, so twofish-x86_64/i586 does not need to enforce\nalignment.\n\nSigned-off-by: Jussi Kivilinna \u003cjussi.kivilinna@mbnet.fi\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "919e2c32496aec4170bd67e64efd526dd0a9bbdc", "tree": "e72e44b6c826349edcc700751b1f570e2a6ac938", "parents": [ "435d3e51af3de0c1fe9f6ca1a18df3cd4d6b8c17" ], "author": { "name": "Jussi Kivilinna", "email": "jussi.kivilinna@mbnet.fi", "time": "Fri Feb 17 22:48:58 2012 +0200" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Sat Feb 25 17:20:24 2012 +0800" }, "message": "crypto: blowfish-x86_64 - set alignmask to zero\n\nx86 has fast unaligned accesses, so blowfish-x86_64 does not need to enforce\nalignment.\n\nSigned-off-by: Jussi Kivilinna \u003cjussi.kivilinna@mbnet.fi\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "435d3e51af3de0c1fe9f6ca1a18df3cd4d6b8c17", "tree": "088093dac3a047e21efd194e7354df25b58f5f4a", "parents": [ "d433208cfc3db3ae0520da92a15ac1f82d8b61ed" ], "author": { "name": "Jussi Kivilinna", "email": "jussi.kivilinna@mbnet.fi", "time": "Fri Feb 17 22:48:53 2012 +0200" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Sat Feb 25 17:20:23 2012 +0800" }, "message": "crypto: serpent-sse2 - combine ablk_*_init functions\n\nDriver name in ablk_*_init functions can be constructed runtime. Therefore\nuse single function ablk_init to reduce object size.\n\nSigned-off-by: Jussi Kivilinna \u003cjussi.kivilinna@mbnet.fi\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "d433208cfc3db3ae0520da92a15ac1f82d8b61ed", "tree": "141688fc3ae7452daef4e378d5168b595a21666b", "parents": [ "53709ddee36cbd19434aa0f0ac8c1e27b92aca33" ], "author": { "name": "Jussi Kivilinna", "email": "jussi.kivilinna@mbnet.fi", "time": "Fri Feb 17 22:48:48 2012 +0200" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Sat Feb 25 17:20:23 2012 +0800" }, "message": "crypto: blowfish-x86_64 - use crypto_[un]register_algs\n\nCombine all crypto_alg to be registered and use new crypto_[un]register_algs\nfunctions. Simplifies init/exit code and reduce object size.\n\nSigned-off-by: Jussi Kivilinna \u003cjussi.kivilinna@mbnet.fi\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "53709ddee36cbd19434aa0f0ac8c1e27b92aca33", "tree": "59c7543cc150c6849185e74d21976461c530ba28", "parents": [ "35474c3bb712261c285ca20c568e4e508387cad5" ], "author": { "name": "Jussi Kivilinna", "email": "jussi.kivilinna@mbnet.fi", "time": "Fri Feb 17 22:48:43 2012 +0200" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Sat Feb 25 17:20:22 2012 +0800" }, "message": "crypto: twofish-x86_64-3way - use crypto_[un]register_algs\n\nCombine all crypto_alg to be registered and use new crypto_[un]register_algs\nfunctions. Simplifies init/exit code and reduce object size.\n\nSigned-off-by: Jussi Kivilinna \u003cjussi.kivilinna@mbnet.fi\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "35474c3bb712261c285ca20c568e4e508387cad5", "tree": "97cda945581b0b4755838ec8d65d5632f20d0a9b", "parents": [ "d97055e62dd8c6f2150b6062ffbd4a6d836658ff" ], "author": { "name": "Jussi Kivilinna", "email": "jussi.kivilinna@mbnet.fi", "time": "Fri Feb 17 22:48:37 2012 +0200" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Sat Feb 25 17:20:22 2012 +0800" }, "message": "crypto: serpent-sse2 - use crypto_[un]register_algs\n\nCombine all crypto_alg to be registered and use new crypto_[un]register_algs\nfunctions. Simplifies init/exit code and reduce object size.\n\nSigned-off-by: Jussi Kivilinna \u003cjussi.kivilinna@mbnet.fi\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "6e77fe8c1100bfb3c6f5b2558d4556519b837b65", "tree": "d61516dfd38c162d90c2b0b9211a881ee4e80eec", "parents": [ "8d21190e223a785a351a1078ac6e3700809969b6" ], "author": { "name": "Jesper Juhl", "email": "jj@chaosbits.net", "time": "Thu Feb 09 23:16:04 2012 +0100" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Tue Feb 14 16:34:19 2012 +0800" }, "message": "crypto: serpent-sse2 - remove dead code from serpent_sse2_glue.c::serpent_sse2_init()\n\nWe cannot reach the line after \u0027return err\u0027. Remove it.\n\nSigned-off-by: Jesper Juhl \u003cjj@chaosbits.net\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "8d21190e223a785a351a1078ac6e3700809969b6", "tree": "80549a6f6e39247cf383b1e47b0518cf34cc3f85", "parents": [ "0cfdec7a65c98de6637e547a04a33969dc9c61b1" ], "author": { "name": "Jesper Juhl", "email": "jj@chaosbits.net", "time": "Thu Feb 09 23:02:16 2012 +0100" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Tue Feb 14 16:34:18 2012 +0800" }, "message": "crypto: twofish-x86 - Remove dead code from twofish_glue_3way.c::init()\n\nWe can never reach the line just after the \u0027return 0\u0027\nstatement. Remove it.\n\nSigned-off-by: Jesper Juhl \u003cjj@chaosbits.net\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "3bd391f056df61e928de1680ff4a3e7e07e5b399", "tree": "f50b5c80010b901a6542b7f4e4913b76d77f3b72", "parents": [ "644e9cbbe3fc032cc92d0936057e166a994dc246" ], "author": { "name": "Andi Kleen", "email": "ak@linux.intel.com", "time": "Thu Jan 26 00:09:06 2012 +0100" }, "committer": { "name": "Greg Kroah-Hartman", "email": "gregkh@suse.de", "time": "Thu Jan 26 16:48:10 2012 -0800" }, "message": "crypto: Add support for x86 cpuid auto loading for x86 crypto drivers\n\nAdd support for auto-loading of crypto drivers based on cpuid features.\nThis enables auto-loading of the VIA and Intel specific drivers\nfor AES, hashing and CRCs.\n\nRequires the earlier infrastructure patch to add x86 modinfo.\nI kept it all in a single patch for now.\n\nI dropped the printks when the driver cpuid doesn\u0027t match (imho\ndrivers never should print anything in such a case)\n\nOne drawback is that udev doesn\u0027t know if the drivers are used or not,\nso they will be unconditionally loaded at boot up. That\u0027s better\nthan not loading them at all, like it often happens.\n\nCc: Dave Jones \u003cdavej@redhat.com\u003e\nCc: Kay Sievers \u003ckay.sievers@vrfy.org\u003e\nCc: Jen Axboe \u003caxboe@kernel.dk\u003e\nCc: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\nCc: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Andi Kleen \u003cak@linux.intel.com\u003e\nSigned-off-by: Thomas Renninger \u003ctrenn@suse.de\u003e\nAcked-by: H. Peter Anvin \u003chpa@zytor.com\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n" }, { "commit": "847cb7ef565d31484f426677e0bea081bfd2acd9", "tree": "7325f4ce5961e0d51ea4707119aeba80622991c3", "parents": [ "4c58464b8034cef4317593bf4ccbfc19d5bb3a77" ], "author": { "name": "Jussi Kivilinna", "email": "jussi.kivilinna@mbnet.fi", "time": "Tue Dec 20 12:58:06 2011 +0200" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Fri Jan 13 16:38:40 2012 +1100" }, "message": "crypto: serpent-sse2 - change transpose_4x4 to only use integer instructions\n\nMatrix transpose macro in serpent-sse2 uses mix of SSE2 integer and SSE floating\npoint instructions, which might cause performance penality on some CPUs.\n\nThis patch replaces transpose_4x4 macro with version that uses only SSE2\ninteger instructions.\n\nSigned-off-by: Jussi Kivilinna \u003cjussi.kivilinna@mbnet.fi\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "4c58464b8034cef4317593bf4ccbfc19d5bb3a77", "tree": "1c6de45e35919b4260a924f27c508a4372f6e865", "parents": [ "a522ee85ba979e7897a75b1c97db1b0304b68b5c" ], "author": { "name": "Jussi Kivilinna", "email": "jussi.kivilinna@mbnet.fi", "time": "Tue Dec 20 12:20:21 2011 +0200" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Fri Jan 13 16:38:39 2012 +1100" }, "message": "crypto: blowfish-x86_64 - blacklist Pentium 4\n\nImplementation in blowfish-x86_64 uses 64bit rotations which are slow on P4,\nmaking blowfish-x86_64 slower than generic C implementation. Therefore\nblacklist P4.\n\nSigned-off-by: Jussi Kivilinna \u003cjussi.kivilinna@mbnet.fi\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "a522ee85ba979e7897a75b1c97db1b0304b68b5c", "tree": "79e826ab14309f8f291f6eecba929eb4d0e1fba3", "parents": [ "f1df57d02a0f83e764b4dc9187f58665d70f190e" ], "author": { "name": "Jussi Kivilinna", "email": "jussi.kivilinna@mbnet.fi", "time": "Tue Dec 20 12:20:16 2011 +0200" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Fri Jan 13 16:38:39 2012 +1100" }, "message": "crypto: twofish-x86_64-3way - blacklist pentium4 and atom\n\nPerformance of twofish-x86_64-3way on Intel Pentium 4 and Atom is lower than\nof twofish-x86_64 module. So blacklist these CPUs.\n\nSigned-off-by: Jussi Kivilinna \u003cjussi.kivilinna@mbnet.fi\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "7ba8babf84fa4e9b648e247223043785f596dd23", "tree": "d2ed2bccc4de0437a88dd2af7ac3849ac049d004", "parents": [ "feaf0cfc263ec778fa166e96ac6a9ef37854fec9" ], "author": { "name": "Jussi Kivilinna", "email": "jussi.kivilinna@mbnet.fi", "time": "Tue Dec 13 12:53:17 2011 +0200" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Tue Dec 20 15:20:08 2011 +0800" }, "message": "crypto: serpent-sse2 - remove unneeded LRW/XTS #ifdefs\n\nSince LRW \u0026 XTS are selected by serpent-sse2, we don\u0027t need these #ifdefs\nanymore.\n\nSigned-off-by: Jussi Kivilinna \u003cjussi.kivilinna@mbnet.fi\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "88715b9ade718564fd8b1318735826370481366b", "tree": "e6258e4d0834b3e63279e06b82423449b22f53ed", "parents": [ "e7cda5d27ed3febf277fe410687c977ae1a31a25" ], "author": { "name": "Jussi Kivilinna", "email": "jussi.kivilinna@mbnet.fi", "time": "Tue Dec 13 12:53:07 2011 +0200" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Tue Dec 20 15:20:07 2011 +0800" }, "message": "crypto: twofish-x86_64-3way - remove unneeded LRW/XTS #ifdefs\n\nSince LRW \u0026 XTS are selected by twofish-x86_64-3way, we don\u0027t need these\n#ifdefs anymore.\n\nSigned-off-by: Jussi Kivilinna \u003cjussi.kivilinna@mbnet.fi\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "d35643385628d44a5933a0755b01478eb4df5c65", "tree": "ab76260a738e8eec1ff153503bc392c7cca916a6", "parents": [ "5962f8b66dd040ad89d55b58967ea2dec607f4d3" ], "author": { "name": "Jussi Kivilinna", "email": "jussi.kivilinna@mbnet.fi", "time": "Wed Nov 09 19:44:12 2011 +0200" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Mon Nov 21 16:13:25 2011 +0800" }, "message": "crypto: serpent-sse2 - clear CRYPTO_TFM_REQ_MAY_SLEEP in lrw and xts modes\n\nLRW/XTS patches for serpent-sse2 forgot to add this. CRYPTO_TFM_REQ_MAY_SLEEP\nshould be cleared as sleeping between kernel_fpu_begin()/kernel_fpu_end() is\nnot allowed.\n\nSigned-off-by: Jussi Kivilinna \u003cjussi.kivilinna@mbnet.fi\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "5962f8b66dd040ad89d55b58967ea2dec607f4d3", "tree": "cad506028aa0a54facdb68cc500d4ab4eb62305a", "parents": [ "18482053f92b099663bd36a10e8f6bd2c8544669" ], "author": { "name": "Jussi Kivilinna", "email": "jussi.kivilinna@mbnet.fi", "time": "Wed Nov 09 16:26:41 2011 +0200" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Mon Nov 21 16:13:24 2011 +0800" }, "message": "crypto: serpent-sse2 - add xts support\n\nPatch adds XTS support for serpent-sse2 by using xts_crypt(). Patch has been\ntested with tcrypt and automated filesystem tests.\n\nTcrypt benchmarks results (serpent-sse2/serpent_generic speed ratios):\n\nIntel Celeron T1600 (x86_64) (fam:6, model:15, step:13):\nsize xts-enc xts-dec\n16B 0.98x 1.00x\n64B 1.00x 1.01x\n256B 2.78x 2.75x\n1024B 3.30x 3.26x\n8192B 3.39x 3.30x\n\nAMD Phenom II 1055T (x86_64) (fam:16, model:10):\nsize xts-enc xts-dec\n16B 1.05x 1.02x\n64B 1.04x 1.03x\n256B 2.10x 2.05x\n1024B 2.34x 2.35x\n8192B 2.34x 2.40x\n\nIntel Atom N270 (i586):\nsize xts-enc xts-dec\n16B 0.95x 0.96x\n64B 1.53x 1.50x\n256B 1.72x 1.75x\n1024B 1.88x 1.87x\n8192B 1.86x 1.83x\n\nSigned-off-by: Jussi Kivilinna \u003cjussi.kivilinna@mbnet.fi\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "18482053f92b099663bd36a10e8f6bd2c8544669", "tree": "5747eb47b1b0ffa59d4ad5c2402021e3b4544a1f", "parents": [ "251496dbfc1be38bc43b49651f3d33c02faccc47" ], "author": { "name": "Jussi Kivilinna", "email": "jussi.kivilinna@mbnet.fi", "time": "Wed Nov 09 16:26:36 2011 +0200" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Mon Nov 21 16:13:24 2011 +0800" }, "message": "crypto: serpent-sse2 - add lrw support\n\nPatch adds LRW support for serpent-sse2 by using lrw_crypt(). Patch has been\ntested with tcrypt and automated filesystem tests.\n\nTcrypt benchmarks results (serpent-sse2/serpent_generic speed ratios):\n\nBenchmark results with tcrypt:\n\nIntel Celeron T1600 (x86_64) (fam:6, model:15, step:13):\nsize lrw-enc lrw-dec\n16B 1.00x 0.96x\n64B 1.01x 1.01x\n256B 3.01x 2.97x\n1024B 3.39x 3.33x\n8192B 3.35x 3.33x\n\nAMD Phenom II 1055T (x86_64) (fam:16, model:10):\nsize lrw-enc lrw-dec\n16B 0.98x 1.03x\n64B 1.01x 1.04x\n256B 2.10x 2.14x\n1024B 2.28x 2.33x\n8192B 2.30x 2.33x\n\nIntel Atom N270 (i586):\nsize lrw-enc lrw-dec\n16B 0.97x 0.97x\n64B 1.47x 1.50x\n256B 1.72x 1.69x\n1024B 1.88x 1.81x\n8192B 1.84x 1.79x\n\nSigned-off-by: Jussi Kivilinna \u003cjussi.kivilinna@mbnet.fi\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "251496dbfc1be38bc43b49651f3d33c02faccc47", "tree": "e17a6704b90b94d0da126eba603fe20cb7ca822c", "parents": [ "937c30d7f560210b0163035edd42b2aef78fed9e" ], "author": { "name": "Jussi Kivilinna", "email": "jussi.kivilinna@mbnet.fi", "time": "Wed Nov 09 16:26:31 2011 +0200" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Mon Nov 21 16:13:23 2011 +0800" }, "message": "crypto: serpent - add 4-way parallel i586/SSE2 assembler implementation\n\nPatch adds i586/SSE2 assembler implementation of serpent cipher. Assembler\nfunctions crypt data in four block chunks.\n\nPatch has been tested with tcrypt and automated filesystem tests.\n\nTcrypt benchmarks results (serpent-sse2/serpent_generic speed ratios):\n\nIntel Atom N270:\n\nsize ecb-enc ecb-dec cbc-enc cbc-dec ctr-enc ctr-dec\n16 0.95x 1.12x 1.02x 1.07x 0.97x 0.98x\n64 1.73x 1.82x 1.08x 1.82x 1.72x 1.73x\n256 2.08x 2.00x 1.04x 2.07x 1.99x 2.01x\n1024 2.28x 2.18x 1.05x 2.23x 2.17x 2.20x\n8192 2.28x 2.13x 1.05x 2.23x 2.18x 2.20x\n\nFull output:\n http://koti.mbnet.fi/axh/kernel/crypto/atom-n270/serpent-generic.txt\n http://koti.mbnet.fi/axh/kernel/crypto/atom-n270/serpent-sse2.txt\n\nUserspace test results:\n\nEncryption/decryption of sse2-i586 vs generic on Intel Atom N270:\n encrypt: 2.35x\n decrypt: 2.54x\n\nEncryption/decryption of sse2-i586 vs generic on AMD Phenom II:\n encrypt: 1.82x\n decrypt: 2.51x\n\nEncryption/decryption of sse2-i586 vs generic on Intel Xeon E7330:\n encrypt: 2.99x\n decrypt: 3.48x\n\nSigned-off-by: Jussi Kivilinna \u003cjussi.kivilinna@mbnet.fi\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "937c30d7f560210b0163035edd42b2aef78fed9e", "tree": "c47348474ca6cdda0a87c95f3a6831c732f27b4d", "parents": [ "d19978f58745e586d9385d306d557e7c785abe23" ], "author": { "name": "Jussi Kivilinna", "email": "jussi.kivilinna@mbnet.fi", "time": "Wed Nov 09 16:26:25 2011 +0200" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Mon Nov 21 16:13:23 2011 +0800" }, "message": "crypto: serpent - add 8-way parallel x86_64/SSE2 assembler implementation\n\nPatch adds x86_64/SSE2 assembler implementation of serpent cipher. Assembler\nfunctions crypt data in eigth block chunks (two 4 block chunk SSE2 operations\nin parallel to improve performance on out-of-order CPUs). Glue code is based\non one from AES-NI implementation, so requests from irq context are redirected\nto cryptd.\n\nv2:\n - add missing include of linux/module.h\n (appearently crypto.h used to include module.h, which changed for 3.2 by\n commit 7c926402a7e8c9b279968fd94efec8700ba3859e)\n\nPatch has been tested with tcrypt and automated filesystem tests.\n\nTcrypt benchmarks results (serpent-sse2/serpent_generic speed ratios):\n\nAMD Phenom II 1055T (fam:16, model:10):\n\nsize ecb-enc ecb-dec cbc-enc cbc-dec ctr-enc ctr-dec\n16B 1.03x 1.01x 1.03x 1.05x 1.00x 0.99x\n64B 1.00x 1.01x 1.02x 1.04x 1.02x 1.01x\n256B 2.34x 2.41x 0.99x 2.43x 2.39x 2.40x\n1024B 2.51x 2.57x 1.00x 2.59x 2.56x 2.56x\n8192B 2.50x 2.54x 1.00x 2.55x 2.57x 2.57x\n\nIntel Celeron T1600 (fam:6, model:15, step:13):\n\nsize ecb-enc ecb-dec cbc-enc cbc-dec ctr-enc ctr-dec\n16B 0.97x 0.97x 1.01x 1.01x 1.01x 1.02x\n64B 1.00x 1.00x 1.00x 1.02x 1.01x 1.01x\n256B 3.41x 3.35x 1.00x 3.39x 3.42x 3.44x\n1024B 3.75x 3.72x 0.99x 3.74x 3.75x 3.75x\n8192B 3.70x 3.68x 0.99x 3.68x 3.69x 3.69x\n\nFull output:\n http://koti.mbnet.fi/axh/kernel/crypto/phenom-ii-1055t/serpent-generic.txt\n http://koti.mbnet.fi/axh/kernel/crypto/phenom-ii-1055t/serpent-sse2.txt\n http://koti.mbnet.fi/axh/kernel/crypto/celeron-t1600/serpent-generic.txt\n http://koti.mbnet.fi/axh/kernel/crypto/celeron-t1600/serpent-sse2.txt\n\nSigned-off-by: Jussi Kivilinna \u003cjussi.kivilinna@mbnet.fi\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "bae6d3038b7faff187f4207448a40b9912cf787d", "tree": "f61e5e596f57c36d949488cf8ddced982e0f68d4", "parents": [ "131f754161bc01fcf7fbbb08c754ed0e5a62b524" ], "author": { "name": "Jussi Kivilinna", "email": "jussi.kivilinna@mbnet.fi", "time": "Tue Oct 18 13:33:43 2011 +0300" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Wed Nov 09 11:57:57 2011 +0800" }, "message": "crypto: twofish-x86_64-3way - add xts support\n\nPatch adds XTS support for twofish-x86_64-3way by using xts_crypt(). Patch has\nbeen tested with tcrypt and automated filesystem tests.\n\nTcrypt benchmarks results (twofish-3way/twofish-asm speed ratios):\n\nIntel Celeron T1600 (fam:6, model:15, step:13):\n\nsize xts-enc xts-dec\n16B 0.98x 1.00x\n64B 1.14x 1.15x\n256B 1.23x 1.25x\n1024B 1.26x 1.29x\n8192B 1.28x 1.30x\n\nAMD Phenom II 1055T (fam:16, model:10):\n\nsize xts-enc xts-dec\n16B 1.03x 1.03x\n64B 1.13x 1.16x\n256B 1.20x 1.20x\n1024B 1.22x 1.22x\n8192B 1.22x 1.21x\n\nSigned-off-by: Jussi Kivilinna \u003cjussi.kivilinna@mbnet.fi\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "81559f9ad3d88c033e4ec3b6468012dbfda3b31d", "tree": "68eeeb74c13537984c3d0ddb7bbe2f5c9b06fc62", "parents": [ "bee3a90ef5366b58250e4369dac3268ced3351aa" ], "author": { "name": "Jussi Kivilinna", "email": "jussi.kivilinna@mbnet.fi", "time": "Tue Oct 18 13:33:02 2011 +0300" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Wed Nov 09 11:53:32 2011 +0800" }, "message": "crypto: twofish-x86_64-3way - add lrw support\n\nPatch adds LRW support for twofish-x86_64-3way by using lrw_crypt(). Patch has\nbeen tested with tcrypt and automated filesystem tests.\n\nTcrypt benchmarks results (twofish-3way/twofish-asm speed ratios):\n\nIntel Celeron T1600 (fam:6, model:15, step:13):\n\nsize\tlrw-enc\tlrw-dec\n16B\t0.99x\t1.00x\n64B\t1.17x\t1.17x\n256B\t1.26x\t1.27x\n1024B\t1.30x\t1.31x\n8192B\t1.31x\t1.32x\n\nAMD Phenom II 1055T (fam:16, model:10):\n\nsize\tlrw-enc\tlrw-dec\n16B\t1.06x\t1.01x\n64B\t1.08x\t1.14x\n256B\t1.19x\t1.20x\n1024B\t1.21x\t1.22x\n8192B\t1.23x\t1.24x\n\nSigned-off-by: Jussi Kivilinna \u003cjussi.kivilinna@mbnet.fi\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "32aaeffbd4a7457bf2f7448b33b5946ff2a960eb", "tree": "faf7ad871d87176423ff9ed1d1ba4d9c688fc23f", "parents": [ "208bca0860406d16398145ddd950036a737c3c9d", "67b84999b1a8b1af5625b1eabe92146c5eb42932" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sun Nov 06 19:44:47 2011 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sun Nov 06 19:44:47 2011 -0800" }, "message": "Merge branch \u0027modsplit-Oct31_2011\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/paulg/linux\n\n* \u0027modsplit-Oct31_2011\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/paulg/linux: (230 commits)\n Revert \"tracing: Include module.h in define_trace.h\"\n irq: don\u0027t put module.h into irq.h for tracking irqgen modules.\n bluetooth: macroize two small inlines to avoid module.h\n ip_vs.h: fix implicit use of module_get/module_put from module.h\n nf_conntrack.h: fix up fallout from implicit moduleparam.h presence\n include: replace linux/module.h with \"struct module\" wherever possible\n include: convert various register fcns to macros to avoid include chaining\n crypto.h: remove unused crypto_tfm_alg_modname() inline\n uwb.h: fix implicit use of asm/page.h for PAGE_SIZE\n pm_runtime.h: explicitly requires notifier.h\n linux/dmaengine.h: fix implicit use of bitmap.h and asm/page.h\n miscdevice.h: fix up implicit use of lists and types\n stop_machine.h: fix implicit use of smp.h for smp_processor_id\n of: fix implicit use of errno.h in include/linux/of.h\n of_platform.h: delete needless include \u003clinux/module.h\u003e\n acpi: remove module.h include from platform/aclinux.h\n miscdevice.h: delete unnecessary inclusion of module.h\n device_cgroup.h: delete needless include \u003clinux/module.h\u003e\n net: sch_generic remove redundant use of \u003clinux/module.h\u003e\n net: inet_timewait_sock doesnt need \u003clinux/module.h\u003e\n ...\n\nFix up trivial conflicts (other header files, and removal of the ab3550 mfd driver) in\n - drivers/media/dvb/frontends/dibx000_common.c\n - drivers/media/video/{mt9m111.c,ov6650.c}\n - drivers/mfd/ab3550-core.c\n - include/linux/dmaengine.h\n" }, { "commit": "7c52d55170ce84ddf9c0ad4e020ef1d7a97975a7", "tree": "6788d2f806d44a7cd437f38dc44169395112081e", "parents": [ "69c60c88eeb364ebf58432f9bc38033522d58767" ], "author": { "name": "Paul Gortmaker", "email": "paul.gortmaker@windriver.com", "time": "Fri May 27 12:33:10 2011 -0400" }, "committer": { "name": "Paul Gortmaker", "email": "paul.gortmaker@windriver.com", "time": "Mon Oct 31 19:30:36 2011 -0400" }, "message": "x86: fix up files really needing to include module.h\n\nThese files aren\u0027t just exporting symbols -- they are also defining\na MODULE_LICENSE etc. so give them the full module.h file.\n\nSigned-off-by: Paul Gortmaker \u003cpaul.gortmaker@windriver.com\u003e\n" }, { "commit": "906b2c9f2d9f395f5ca01b855b7c74b126517816", "tree": "50df3571adb595a9547cb0f0e4c00e931e8088ba", "parents": [ "a516ebafdf231702b7461cab562c7fe328ef972b" ], "author": { "name": "Jussi Kivilinna", "email": "jussi.kivilinna@mbnet.fi", "time": "Mon Oct 10 12:33:02 2011 +0300" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Fri Oct 21 14:28:57 2011 +0200" }, "message": "crypto: twofish-x86_64-3way - fix ctr blocksize to 1\n\nSigned-off-by: Jussi Kivilinna \u003cjussi.kivilinna@mbnet.fi\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "a516ebafdf231702b7461cab562c7fe328ef972b", "tree": "c45538543f4965d7dd3f4e36c3502dfe376c01c7", "parents": [ "ac4385d250d83fae0148607d9fb694aa6e90ab9c" ], "author": { "name": "Jussi Kivilinna", "email": "jussi.kivilinna@mbnet.fi", "time": "Mon Oct 10 12:32:15 2011 +0300" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Fri Oct 21 14:28:57 2011 +0200" }, "message": "crypto: blowfish-x86_64 - fix ctr blocksize to 1\n\nSigned-off-by: Jussi Kivilinna \u003cjussi.kivilinna@mbnet.fi\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "8280daad436edb7dd9e7e06fc13bcecb6b2a885c", "tree": "0d4cb032c6da8617bd4a2dd84bd8ef1a605fa19d", "parents": [ "91d41f159d75d602f6001218eec64c5e761475a6" ], "author": { "name": "Jussi Kivilinna", "email": "jussi.kivilinna@mbnet.fi", "time": "Mon Sep 26 16:47:25 2011 +0300" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Fri Oct 21 14:23:08 2011 +0200" }, "message": "crypto: twofish - add 3-way parallel x86_64 assembler implemention\n\nPatch adds 3-way parallel x86_64 assembly implementation of twofish as new\nmodule. New assembler functions crypt data in three blocks chunks, improving\ncipher performance on out-of-order CPUs.\n\nPatch has been tested with tcrypt and automated filesystem tests.\n\nSummary of the tcrypt benchmarks:\n\nTwofish 3-way-asm vs twofish asm (128bit 8kb block ECB)\n encrypt: 1.3x speed\n decrypt: 1.3x speed\n\nTwofish 3-way-asm vs twofish asm (128bit 8kb block CBC)\n encrypt: 1.07x speed\n decrypt: 1.4x speed\n\nTwofish 3-way-asm vs twofish asm (128bit 8kb block CTR)\n encrypt: 1.4x speed\n\nTwofish 3-way-asm vs AES asm (128bit 8kb block ECB)\n encrypt: 1.0x speed\n decrypt: 1.0x speed\n\nTwofish 3-way-asm vs AES asm (128bit 8kb block CBC)\n encrypt: 0.84x speed\n decrypt: 1.09x speed\n\nTwofish 3-way-asm vs AES asm (128bit 8kb block CTR)\n encrypt: 1.15x speed\n\nFull output:\n http://koti.mbnet.fi/axh/kernel/crypto/tcrypt-speed-twofish-3way-asm-x86_64.txt\n http://koti.mbnet.fi/axh/kernel/crypto/tcrypt-speed-twofish-asm-x86_64.txt\n http://koti.mbnet.fi/axh/kernel/crypto/tcrypt-speed-aes-asm-x86_64.txt\n\nTests were run on:\n vendor_id : AuthenticAMD\n cpu family : 16\n model : 10\n model name : AMD Phenom(tm) II X6 1055T Processor\n\nAlso userspace test were run on:\n vendor_id : GenuineIntel\n cpu family : 6\n model : 15\n model name : Intel(R) Xeon(R) CPU E7330 @ 2.40GHz\n stepping : 11\n\nUserspace test results:\n\nEncryption/decryption of twofish 3-way vs x86_64-asm on AMD Phenom II:\n encrypt: 1.27x\n decrypt: 1.25x\n\nEncryption/decryption of twofish 3-way vs x86_64-asm on Intel Xeon E7330:\n encrypt: 1.36x\n decrypt: 1.36x\n\nSigned-off-by: Jussi Kivilinna \u003cjussi.kivilinna@mbnet.fi\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "91d41f159d75d602f6001218eec64c5e761475a6", "tree": "1bc2607e291604764348bccdb6cf6f9a0b5e4fbb", "parents": [ "ee5002a5497f3219b4144b5370203ed6e43f7269" ], "author": { "name": "Jussi Kivilinna", "email": "jussi.kivilinna@mbnet.fi", "time": "Mon Sep 26 16:47:20 2011 +0300" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Fri Oct 21 14:23:08 2011 +0200" }, "message": "crypto: twofish-x86-asm - make assembler functions use twofish_ctx instead of crypto_tfm\n\nThis needed by 3-way twofish patch to be able to easily use one block\nassembler functions. As glue code is shared between i586/x86_64 apply\nchange to i586 assembler too. Also export assembler functions for\n3-way parallel twofish module.\n\nCC: Joachim Fritschi \u003cjfritschi@freenet.de\u003e\nSigned-off-by: Jussi Kivilinna \u003cjussi.kivilinna@mbnet.fi\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "a071d06e34ff361c7a8d1ddf3ce8a95d782fa25a", "tree": "b946f33a0fa6aee06cfff108a4992f59057f89f5", "parents": [ "e827bb09c815955d5d5f0ddf98483a7efd04f55b" ], "author": { "name": "Jussi Kivilinna", "email": "jussi.kivilinna@mbnet.fi", "time": "Fri Sep 23 19:51:00 2011 +0300" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Fri Oct 21 14:23:07 2011 +0200" }, "message": "crypto: blowfish-x86_64 - add credits\n\nSigned-off-by: Jussi Kivilinna \u003cjussi.kivilinna@mbnet.fi\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "e827bb09c815955d5d5f0ddf98483a7efd04f55b", "tree": "6a4b262e8b51c5b863855549d5f6280b4f5c0e6c", "parents": [ "fad8fa4782fde8afffc16b2b907b7f5bdbf03133" ], "author": { "name": "Jussi Kivilinna", "email": "jussi.kivilinna@mbnet.fi", "time": "Fri Sep 23 19:50:55 2011 +0300" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Fri Oct 21 14:23:07 2011 +0200" }, "message": "crypto: blowfish-x86_64 - improve x86_64 blowfish 4-way performance\n\nThis patch adds improved F-macro for 4-way parallel functions. With new\nF-macro for 4-way parallel functions, blowfish sees ~15% improvement in\nspeed tests on AMD Phenom II (~5% on Intel Xeon E7330).\n\nHowever when used in 1-way blowfish function new macro would be ~10%\nslower than original, so old F-macro is kept for 1-way functions.\nPatch cleans up old F-macro as it is no longer needed in 4-way part.\n\nPatch also does register macro renaming to reduce stack usage.\n\nSigned-off-by: Jussi Kivilinna \u003cjussi.kivilinna@mbnet.fi\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "4a4cc2b6bf475c183443278808b758c702c01404", "tree": "c2f201b96e3411ee41a0a01c21a4d1fecfe4b497", "parents": [ "64b94ceae8c16cd1b2800cac83112d3815be5250" ], "author": { "name": "H Hartley Sweeten", "email": "hsweeten@visionengravers.com", "time": "Thu Sep 22 21:33:01 2011 +1000" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Thu Sep 22 21:33:01 2011 +1000" }, "message": "crypto: aes-x86 - quiet sparse noise about symbol not declared\n\nInclude \u003casm/aes.h\u003e to pick up the declarations for crypto_aes_encrypt_x86\nand crypto_aes_decrypt_x86 to quiet the sparse noise:\n\nwarning: symbol \u0027crypto_aes_encrypt_x86\u0027 was not declared. Should it be static?\nwarning: symbol \u0027crypto_aes_decrypt_x86\u0027 was not declared. Should it be static?\n\nSigned-off-by: H Hartley Sweeten \u003chsweeten@visionengravers.com\u003e\nAcked-by: Mandeep Singh Baines \u003cmsb@chromium.org\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "64b94ceae8c16cd1b2800cac83112d3815be5250", "tree": "c7e3384659522cac32dc85a34e4ed722346a0f91", "parents": [ "7d47b86cfef808c6580b7603c3f17fcaf27e9d14" ], "author": { "name": "Jussi Kivilinna", "email": "jussi.kivilinna@mbnet.fi", "time": "Fri Sep 02 01:45:22 2011 +0300" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Thu Sep 22 21:25:26 2011 +1000" }, "message": "crypto: blowfish - add x86_64 assembly implementation\n\nPatch adds x86_64 assembly implementation of blowfish. Two set of assembler\nfunctions are provided. First set is regular \u0027one-block at time\u0027\nencrypt/decrypt functions. Second is \u0027four-block at time\u0027 functions that\ngain performance increase on out-of-order CPUs. Performance of 4-way\nfunctions should be equal to 1-way functions with in-order CPUs.\n\nSummary of the tcrypt benchmarks:\n\nBlowfish assembler vs blowfish C (256bit 8kb block ECB)\nencrypt: 2.2x speed\ndecrypt: 2.3x speed\n\nBlowfish assembler vs blowfish C (256bit 8kb block CBC)\nencrypt: 1.12x speed\ndecrypt: 2.5x speed\n\nBlowfish assembler vs blowfish C (256bit 8kb block CTR)\nencrypt: 2.5x speed\n\nFull output:\nhttp://koti.mbnet.fi/axh/kernel/crypto/tcrypt-speed-blowfish-asm-x86_64.txt\nhttp://koti.mbnet.fi/axh/kernel/crypto/tcrypt-speed-blowfish-c-x86_64.txt\n\nTests were run on:\n vendor_id\t: AuthenticAMD\n cpu family\t: 16\n model\t\t: 10\n model name\t: AMD Phenom(tm) II X6 1055T Processor\n stepping\t: 0\n\nSigned-off-by: Jussi Kivilinna \u003cjussi.kivilinna@mbnet.fi\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "66be895158886a6cd816aa1eaa18965a5c522d8f", "tree": "2eee685d2249cd5973e15303b8101df7c956e607", "parents": [ "7c390170b49337477985be7a624015160ffeb056" ], "author": { "name": "Mathias Krause", "email": "minipli@googlemail.com", "time": "Thu Aug 04 20:19:25 2011 +0200" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Wed Aug 10 19:00:29 2011 +0800" }, "message": "crypto: sha1 - SSSE3 based SHA1 implementation for x86-64\n\nThis is an assembler implementation of the SHA1 algorithm using the\nSupplemental SSE3 (SSSE3) instructions or, when available, the\nAdvanced Vector Extensions (AVX).\n\nTesting with the tcrypt module shows the raw hash performance is up to\n2.3 times faster than the C implementation, using 8k data blocks on a\nCore 2 Duo T5500. For the smalest data set (16 byte) it is still 25%\nfaster.\n\nSince this implementation uses SSE/YMM registers it cannot safely be\nused in every situation, e.g. while an IRQ interrupts a kernel thread.\nThe implementation falls back to the generic SHA1 variant, if using\nthe SSE/YMM registers is not possible.\n\nWith this algorithm I was able to increase the throughput of a single\nIPsec link from 344 Mbit/s to 464 Mbit/s on a Core 2 Quad CPU using\nthe SSSE3 variant -- a speedup of +34.8%.\n\nSaving and restoring SSE/YMM state might make the actual throughput\nfluctuate when there are FPU intensive userland applications running.\nFor example, meassuring the performance using iperf2 directly on the\nmachine under test gives wobbling numbers because iperf2 uses the FPU\nfor each packet to check if the reporting interval has expired (in the\nabove test I got min/max/avg: 402/484/464 MBit/s).\n\nUsing this algorithm on a IPsec gateway gives much more reasonable and\nstable numbers, albeit not as high as in the directly connected case.\nHere is the result from an RFC 2544 test run with a EXFO Packet Blazer\nFTB-8510:\n\n frame size sha1-generic sha1-ssse3 delta\n 64 byte 37.5 MBit/s 37.5 MBit/s 0.0%\n 128 byte 56.3 MBit/s 62.5 MBit/s +11.0%\n 256 byte 87.5 MBit/s 100.0 MBit/s +14.3%\n 512 byte 131.3 MBit/s 150.0 MBit/s +14.2%\n 1024 byte 162.5 MBit/s 193.8 MBit/s +19.3%\n 1280 byte 175.0 MBit/s 212.5 MBit/s +21.4%\n 1420 byte 175.0 MBit/s 218.7 MBit/s +25.0%\n 1518 byte 150.0 MBit/s 181.2 MBit/s +20.8%\n\nThe throughput for the largest frame size is lower than for the\nprevious size because the IP packets need to be fragmented in this\ncase to make there way through the IPsec tunnel.\n\nSigned-off-by: Mathias Krause \u003cminipli@googlemail.com\u003e\nCc: Maxim Locktyukhin \u003cmaxim.locktyukhin@intel.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "c3e73e76a90b1e790e0bb7bb36135be9232f58de", "tree": "28516c9807272ee05ae85d2835b2b1923a53d21f", "parents": [ "a18b989a5c12ca82ed37f94279273ddbc073758a" ], "author": { "name": "Gustavo F. Padovan", "email": "padovan@profusion.mobi", "time": "Thu May 26 13:29:33 2011 +1000" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Thu Jun 30 07:43:42 2011 +0800" }, "message": "crypto: ghash-intel - Fix set but not used in ghash_async_setkey()\n\nSigned-off-by: Gustavo F. Padovan \u003cpadovan@profusion.mobi\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "9bed4aca296fdf9c1b85a8f093e92018dc9864f3", "tree": "f01e44f3f827c5805f871a2cc9940390d3159dfc", "parents": [ "b23b64516500df6b70fcafb820970f18538252cf" ], "author": { "name": "Randy Dunlap", "email": "randy.dunlap@oracle.com", "time": "Wed May 18 09:03:34 2011 +1000" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Wed May 18 09:03:34 2011 +1000" }, "message": "crypto: aesni-intel - fix aesni build on i386\n\nFix build error on i386 by moving function prototypes:\n\narch/x86/crypto/aesni-intel_glue.c: In function \u0027aesni_init\u0027:\narch/x86/crypto/aesni-intel_glue.c:1263: error: implicit declaration of function \u0027crypto_fpu_init\u0027\narch/x86/crypto/aesni-intel_glue.c: In function \u0027aesni_exit\u0027:\narch/x86/crypto/aesni-intel_glue.c:1373: error: implicit declaration of function \u0027crypto_fpu_exit\u0027\n\nSigned-off-by: Randy Dunlap \u003crandy.dunlap@oracle.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "b23b64516500df6b70fcafb820970f18538252cf", "tree": "aba2a9ac7384c4d4b64601bd1969dca703b43b52", "parents": [ "6ef84509f3d439ed2d43ea40080643efec37f54f" ], "author": { "name": "Andy Lutomirski", "email": "luto@mit.edu", "time": "Mon May 16 15:12:47 2011 +1000" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Mon May 16 15:12:47 2011 +1000" }, "message": "crypto: aesni-intel - Merge with fpu.ko\n\nLoading fpu without aesni-intel does nothing. Loading aesni-intel\nwithout fpu causes modes like xts to fail. (Unloading\naesni-intel will restore those modes.)\n\nOne solution would be to make aesni-intel depend on fpu, but it\nseems cleaner to just combine the modules.\n\nThis is probably responsible for bugs like:\nhttps://bugzilla.redhat.com/show_bug.cgi?id\u003d589390\n\nSigned-off-by: Andy Lutomirski \u003cluto@mit.edu\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "60af520cf264ea26b2af3a6871bbd71850522aea", "tree": "20137c9607f02c8689c3844a38a9baf0d59225c7", "parents": [ "16c29dafcc86024048f1dbb8349d31cb22c7c55a" ], "author": { "name": "Tadeusz Struk", "email": "tadeusz.struk@intel.com", "time": "Sun Mar 13 16:56:17 2011 +0800" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Sun Mar 27 10:29:39 2011 +0800" }, "message": "crypto: aesni-intel - fixed problem with packets that are not multiple of 64bytes\n\nThis patch fixes problem with packets that are not multiple of 64bytes.\n\nSigned-off-by: Adrian Hoban \u003cadrian.hoban@intel.com\u003e\nSigned-off-by: Aidan O\u0027Mahony \u003caidan.o.mahony@intel.com\u003e\nSigned-off-by: Gabriele Paoloni \u003cgabriele.paoloni@intel.com\u003e\nSigned-off-by: Tadeusz Struk \u003ctadeusz.struk@intel.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "f2e1fbb5f2177227f71c4fc0491e531dd7acd385", "tree": "c45485e3cd8a04f78184ef3bd9ce6972c74ac834", "parents": [ "508996b6a0ef0c7aa7701995d137e71c56180752", "4981d01eada5354d81c8929d5b2836829ba3df7b" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Mar 18 10:45:21 2011 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Mar 18 10:45:21 2011 -0700" }, "message": "Merge branch \u0027x86-fixes-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip\n\n* \u0027x86-fixes-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:\n x86: Flush TLB if PGD entry is changed in i386 PAE mode\n x86, dumpstack: Correct stack dump info when frame pointer is available\n x86: Clean up csum-copy_64.S a bit\n x86: Fix common misspellings\n x86: Fix misspelling and align params\n x86: Use PentiumPro-optimized partial_csum() on VIA C7\n" }, { "commit": "0d2eb44f631d9d0a826efa3156f157477fdaecf4", "tree": "6d0b7b6332ac0bf232b1b1190d8d999ee910eea4", "parents": [ "a6c3270b04340c5e0d47af5bdb10f30d33333739" ], "author": { "name": "Lucas De Marchi", "email": "lucas.de.marchi@gmail.com", "time": "Thu Mar 17 16:24:16 2011 -0300" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Fri Mar 18 10:39:30 2011 +0100" }, "message": "x86: Fix common misspellings\n\nThey were generated by \u0027codespell\u0027 and then manually reviewed.\n\nSigned-off-by: Lucas De Marchi \u003clucas.demarchi@profusion.mobi\u003e\nCc: trivial@kernel.org\nLKML-Reference: \u003c1300389856-1099-3-git-send-email-lucas.demarchi@profusion.mobi\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "fc9044e2db8c13746cd886d6276028b27ed5c78e", "tree": "dd5ef29162ba59ac85e2adf60b1e855123141ecb", "parents": [ "36be070ac600d023ada2ec107ee925f5ac5f902b" ], "author": { "name": "Jesper Juhl", "email": "jj@chaosbits.net", "time": "Wed Feb 16 13:04:09 2011 +1100" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Wed Feb 16 13:04:09 2011 +1100" }, "message": "crypto: aesni-intel - Fix remaining leak in rfc4106_set_hash_key\n\nFix up previous patch that failed to properly fix mem leak in \nrfc4106_set_hash_subkey(). This add-on patch; fixes the leak. moves \nkfree() out of the error path, returns -ENOMEM rather than -EINVAL when \nablkcipher_request_alloc() fails.\n\nSigned-off-by: Jesper Juhl \u003cjj@chaosbits.net\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "7efd95f6270e210be90b94466bd3405b81e8d667", "tree": "6bd08a0e6ba2ce88dbdecdee0f7ea24e3f891587", "parents": [ "1bae4ce27c9c90344f23c65ea6966c50ffeae2f5" ], "author": { "name": "Jesper Juhl", "email": "jj@chaosbits.net", "time": "Sun Jan 23 18:56:36 2011 +1100" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Sun Jan 23 18:59:17 2011 +1100" }, "message": "crypto: aesni-intel - Don\u0027t leak memory in rfc4106_set_hash_subkey\n\nThere\u0027s a small memory leak in \narch/x86/crypto/aesni-intel_glue.c::rfc4106_set_hash_subkey(). If the call \nto kmalloc() fails and returns NULL then the memory allocated previously \nby ablkcipher_request_alloc() is not freed when we leave the function.\n\nI could have just added a call to ablkcipher_request_free() before we \nreturn -ENOMEM, but that started to look too much like the code we \nalready had at the end of the function, so I chose instead to rework the \ncode a bit so that there are now a few labels at the end that we goto when \nvarious allocations fail, so we don\u0027t have to repeat the same blocks of \ncode (this also reduces the object code size slightly).\n\nSigned-off-by: Jesper Juhl \u003cjj@chaosbits.net\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "27d189c02ba25851973c8582e419c0bded9f7e5b", "tree": "be142d664bc4e3cec7ab2878a243343f46e897ee", "parents": [ "a1703154200c390ab03c10224c586e815d3e31e8", "55db8387a5e8d07407f0b7c6b2526417a2bc6243" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Jan 13 10:25:58 2011 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Jan 13 10:25:58 2011 -0800" }, "message": "Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6\n\n* git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (46 commits)\n hwrng: via_rng - Fix memory scribbling on some CPUs\n crypto: padlock - Move padlock.h into include/crypto\n hwrng: via_rng - Fix asm constraints\n crypto: n2 - use __devexit not __exit in n2_unregister_algs\n crypto: mark crypto workqueues CPU_INTENSIVE\n crypto: mv_cesa - dont return PTR_ERR() of wrong pointer\n crypto: ripemd - Set module author and update email address\n crypto: omap-sham - backlog handling fix\n crypto: gf128mul - Remove experimental tag\n crypto: af_alg - fix af_alg memory_allocated data type\n crypto: aesni-intel - Fixed build with binutils 2.16\n crypto: af_alg - Make sure sk_security is initialized on accept()ed sockets\n net: Add missing lockdep class names for af_alg\n include: Install linux/if_alg.h for user-space crypto API\n crypto: omap-aes - checkpatch --file warning fixes\n crypto: omap-aes - initialize aes module once per request\n crypto: omap-aes - unnecessary code removed\n crypto: omap-aes - error handling implementation improved\n crypto: omap-aes - redundant locking is removed\n crypto: omap-aes - DMA initialization fixes for OMAP off mode\n ...\n" }, { "commit": "52f6c5ad430e41736133acac179607b224eaaa11", "tree": "f525c1e28ebff9d96b6cee57729b315b0938a652", "parents": [ "0fcdcfbbc98f70f559e4b36773a69972489a6d8f" ], "author": { "name": "Randy Dunlap", "email": "randy.dunlap@oracle.com", "time": "Wed Dec 15 17:58:57 2010 +0800" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Wed Dec 15 19:44:08 2010 +0800" }, "message": "crypto: ghash-intel - ghash-clmulni-intel_glue needs err.h\n\nAdd missing header file:\n\narch/x86/crypto/ghash-clmulni-intel_glue.c:256: error: implicit declaration of function \u0027IS_ERR\u0027\narch/x86/crypto/ghash-clmulni-intel_glue.c:257: error: implicit declaration of function \u0027PTR_ERR\u0027\n\nSigned-off-by: Randy Dunlap \u003crandy.dunlap@oracle.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "3c097b800816c0e4c2a34c38f8b2409427770f7a", "tree": "c4d5293dae7c0842877221fb12b5f2cf7d4a0a26", "parents": [ "507cad355fc9e426f2846c46a4edca2d22d25f44" ], "author": { "name": "Tadeusz Struk", "email": "tadeusz.struk@intel.com", "time": "Mon Dec 13 19:51:15 2010 +0800" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Mon Dec 13 19:51:15 2010 +0800" }, "message": "crypto: aesni-intel - Fixed build with binutils 2.16\n\nThis patch fixes the problem with 2.16 binutils.\n\nSigned-off-by: Aidan O\u0027Mahony \u003caidan.o.mahony@intel.com\u003e\nSigned-off-by: Adrian Hoban \u003cadrian.hoban@intel.com\u003e\nSigned-off-by: Gabriele Paoloni \u003cgabriele.paoloni@intel.com\u003e\nSigned-off-by: Tadeusz Struk \u003ctadeusz.struk@intel.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "559ad0ff1368baea14dbc3207d55b02bd69bda4b", "tree": "c1f329dd3b3084e0df26cc6436586265f79bf838", "parents": [ "c762be637503b833012457087133c1292fd6056d" ], "author": { "name": "Mathias Krause", "email": "minipli@googlemail.com", "time": "Mon Nov 29 08:35:39 2010 +0800" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Mon Nov 29 08:35:39 2010 +0800" }, "message": "crypto: aesni-intel - Fixed build error on x86-32\n\nExclude AES-GCM code for x86-32 due to heavy usage of 64-bit registers\nnot available on x86-32.\n\nWhile at it, fixed unregister order in aesni_exit().\n\nSigned-off-by: Mathias Krause \u003cminipli@googlemail.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "0d258efb6a58fe047197c3b9cff8746bb176d58a", "tree": "8576f2af5212ec50509de1071cf7afe1ed9531a8", "parents": [ "21ea28abcf825729f9698afd7357dfbf7040d4f8" ], "author": { "name": "Mathias Krause", "email": "minipli@googlemail.com", "time": "Sat Nov 27 16:34:46 2010 +0800" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Sat Nov 27 16:34:46 2010 +0800" }, "message": "crypto: aesni-intel - Ported implementation to x86-32\n\nThe AES-NI instructions are also available in legacy mode so the 32-bit\narchitecture may profit from those, too.\n\nTo illustrate the performance gain here\u0027s a short summary of a dm-crypt\nspeed test on a Core i7 M620 running at 2.67GHz comparing both assembler\nimplementations:\n\nx86: i568 aes-ni delta\nECB, 256 bit: 93.8 MB/s 123.3 MB/s +31.4%\nCBC, 256 bit: 84.8 MB/s 262.3 MB/s +209.3%\nLRW, 256 bit: 108.6 MB/s 222.1 MB/s +104.5%\nXTS, 256 bit: 105.0 MB/s 205.5 MB/s +95.7%\n\nAdditionally, due to some minor optimizations, the 64-bit version also\ngot a minor performance gain as seen below:\n\nx86-64: old impl. new impl. delta\nECB, 256 bit: 121.1 MB/s 123.0 MB/s +1.5%\nCBC, 256 bit: 285.3 MB/s 290.8 MB/s +1.9%\nLRW, 256 bit: 263.7 MB/s 265.3 MB/s +0.6%\nXTS, 256 bit: 251.1 MB/s 255.3 MB/s +1.7%\n\nSigned-off-by: Mathias Krause \u003cminipli@googlemail.com\u003e\nReviewed-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "0bd82f5f6355775fbaf7d3c664432ce1b862be1e", "tree": "5f7f7348c2681d572e8bc11f27a42a6e2b8f4023", "parents": [ "895be15745d59cc7ede0e1c203e3432b0abdb71c" ], "author": { "name": "Tadeusz Struk", "email": "tadeusz.struk@intel.com", "time": "Thu Nov 04 15:00:45 2010 -0400" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Sat Nov 13 21:47:55 2010 +0900" }, "message": "crypto: aesni-intel - RFC4106 AES-GCM Driver Using Intel New Instructions\n\nThis patch adds an optimized RFC4106 AES-GCM implementation for 64-bit\nkernels. It supports 128-bit AES key size. This leverages the crypto\nAEAD interface type to facilitate a combined AES \u0026 GCM operation to\nbe implemented in assembly code. The assembly code leverages Intel(R)\nAES New Instructions and the PCLMULQDQ instruction.\n\nSigned-off-by: Adrian Hoban \u003cadrian.hoban@intel.com\u003e\nSigned-off-by: Tadeusz Struk \u003ctadeusz.struk@intel.com\u003e\nSigned-off-by: Gabriele Paoloni \u003cgabriele.paoloni@intel.com\u003e\nSigned-off-by: Aidan O\u0027Mahony \u003caidan.o.mahony@intel.com\u003e\nSigned-off-by: Erdinc Ozturk \u003cerdinc.ozturk@intel.com\u003e\nSigned-off-by: James Guilford \u003cjames.guilford@intel.com\u003e\nSigned-off-by: Wajdi Feghali \u003cwajdi.k.feghali@intel.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "df2071bd081408318d659cd14a9cf6ff23d874c9", "tree": "b31291b5fd4b9f84c629833afbfaa8d431857475", "parents": [ "97e3d94aac1c3e95bd04d1b186479a4df3663ab8", "be1066bbcd443a65df312fdecea7e4959adedb45" ], "author": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Mon May 03 11:28:58 2010 +0800" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Mon May 03 11:28:58 2010 +0800" }, "message": "Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6\n" }, { "commit": "5a0e3ad6af8660be21ca98a971cd00f331318c05", "tree": "5bfb7be11a03176a87296a43ac6647975c00a1d1", "parents": [ "ed391f4ebf8f701d3566423ce8f17e614cde9806" ], "author": { "name": "Tejun Heo", "email": "tj@kernel.org", "time": "Wed Mar 24 17:04:11 2010 +0900" }, "committer": { "name": "Tejun Heo", "email": "tj@kernel.org", "time": "Tue Mar 30 22:02:32 2010 +0900" }, "message": "include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h\n\npercpu.h is included by sched.h and module.h and thus ends up being\nincluded when building most .c files. percpu.h includes slab.h which\nin turn includes gfp.h making everything defined by the two files\nuniversally available and complicating inclusion dependencies.\n\npercpu.h -\u003e slab.h dependency is about to be removed. Prepare for\nthis change by updating users of gfp and slab facilities include those\nheaders directly instead of assuming availability. As this conversion\nneeds to touch large number of source files, the following script is\nused as the basis of conversion.\n\n http://userweb.kernel.org/~tj/misc/slabh-sweep.py\n\nThe script does the followings.\n\n* Scan files for gfp and slab usages and update includes such that\n only the necessary includes are there. ie. if only gfp is used,\n gfp.h, if slab is used, slab.h.\n\n* When the script inserts a new include, it looks at the include\n blocks and try to put the new include such that its order conforms\n to its surrounding. It\u0027s put in the include block which contains\n core kernel includes, in the same order that the rest are ordered -\n alphabetical, Christmas tree, rev-Xmas-tree or at the end if there\n doesn\u0027t seem to be any matching order.\n\n* If the script can\u0027t find a place to put a new include (mostly\n because the file doesn\u0027t have fitting include block), it prints out\n an error message indicating which .h file needs to be added to the\n file.\n\nThe conversion was done in the following steps.\n\n1. The initial automatic conversion of all .c files updated slightly\n over 4000 files, deleting around 700 includes and adding ~480 gfp.h\n and ~3000 slab.h inclusions. The script emitted errors for ~400\n files.\n\n2. Each error was manually checked. Some didn\u0027t need the inclusion,\n some needed manual addition while adding it to implementation .h or\n embedding .c file was more appropriate for others. This step added\n inclusions to around 150 files.\n\n3. The script was run again and the output was compared to the edits\n from #2 to make sure no file was left behind.\n\n4. Several build tests were done and a couple of problems were fixed.\n e.g. lib/decompress_*.c used malloc/free() wrappers around slab\n APIs requiring slab.h to be added manually.\n\n5. The script was run on all .h files but without automatically\n editing them as sprinkling gfp.h and slab.h inclusions around .h\n files could easily lead to inclusion dependency hell. Most gfp.h\n inclusion directives were ignored as stuff from gfp.h was usually\n wildly available and often used in preprocessor macros. Each\n slab.h inclusion directive was examined and added manually as\n necessary.\n\n6. percpu.h was updated not to include slab.h.\n\n7. Build test were done on the following configurations and failures\n were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my\n distributed build env didn\u0027t work with gcov compiles) and a few\n more options had to be turned off depending on archs to make things\n build (like ipr on powerpc/64 which failed due to missing writeq).\n\n * x86 and x86_64 UP and SMP allmodconfig and a custom test config.\n * powerpc and powerpc64 SMP allmodconfig\n * sparc and sparc64 SMP allmodconfig\n * ia64 SMP allmodconfig\n * s390 SMP allmodconfig\n * alpha SMP allmodconfig\n * um on x86_64 SMP allmodconfig\n\n8. percpu.h modifications were reverted so that it could be applied as\n a separate patch and serve as bisection point.\n\nGiven the fact that I had only a couple of failures from tests on step\n6, I\u0027m fairly confident about the coverage of this conversion patch.\nIf there is a breakage, it\u0027s likely to be something in one of the arch\nheaders which should be easily discoverable easily on most builds of\nthe specific arch.\n\nSigned-off-by: Tejun Heo \u003ctj@kernel.org\u003e\nGuess-its-ok-by: Christoph Lameter \u003ccl@linux-foundation.org\u003e\nCc: Ingo Molnar \u003cmingo@redhat.com\u003e\nCc: Lee Schermerhorn \u003cLee.Schermerhorn@hp.com\u003e\n" }, { "commit": "32cbd7dfce93382a70f155bf539871b4c55bed29", "tree": "30ae215018df38e5f6b29eec73ad9a00d693ccc9", "parents": [ "18bcc9194da3c97e8f458fb1b06ac5b9b35fb23f" ], "author": { "name": "Huang Ying", "email": "ying.huang@intel.com", "time": "Sat Mar 13 16:28:42 2010 +0800" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Sat Mar 13 16:28:42 2010 +0800" }, "message": "crypto: aesni-intel - Fix CTR optimization build failure with gas 2.16.1\n\nAndrew Morton reported that AES-NI CTR optimization failed to compile\nwith gas 2.16.1, the error message is as follow:\n\narch/x86/crypto/aesni-intel_asm.S: Assembler messages:\narch/x86/crypto/aesni-intel_asm.S:752: Error: suffix or operands invalid for `movq\u0027\narch/x86/crypto/aesni-intel_asm.S:753: Error: suffix or operands invalid for `movq\u0027\n\nTo fix this, a gas macro is defined to assemble movq with 64bit\ngeneral purpose registers and XMM registers. The macro will generate\nthe raw .byte sequence for needed instructions.\n\nReported-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "12387a46bb150f5608de4aa9a90dfdddbf991e3f", "tree": "a840b4a5da93cc3658eeb2477e47f402d0c77e28", "parents": [ "269ab459da46ae37979a0d16307d1fcaa05600b2" ], "author": { "name": "Huang Ying", "email": "ying.huang@intel.com", "time": "Wed Mar 10 18:28:55 2010 +0800" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Wed Mar 10 18:28:55 2010 +0800" }, "message": "crypto: aesni-intel - Add AES-NI accelerated CTR mode\n\nTo take advantage of the hardware pipeline implementation of AES-NI\ninstructions. CTR mode cryption is implemented in ASM to schedule\nmultiple AES-NI instructions one after another. This way, some latency\nof AES-NI instruction can be eliminated.\n\nPerformance testing based on dm-crypt should 50% reduction of\necryption/decryption time.\n\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "3ad2f3fbb961429d2aa627465ae4829758bc7e07", "tree": "f365c513e8f5b477a61336a600ff54f32b7ad6e1", "parents": [ "1537a3638cbf741d3826c1002026cce487a6bee0" ], "author": { "name": "Daniel Mack", "email": "daniel@caiaq.de", "time": "Wed Feb 03 08:01:28 2010 +0800" }, "committer": { "name": "Jiri Kosina", "email": "jkosina@suse.cz", "time": "Tue Feb 09 11:13:56 2010 +0100" }, "message": "tree-wide: Assorted spelling fixes\n\nIn particular, several occurances of funny versions of \u0027success\u0027,\n\u0027unknown\u0027, \u0027therefore\u0027, \u0027acknowledge\u0027, \u0027argument\u0027, \u0027achieve\u0027, \u0027address\u0027,\n\u0027beginning\u0027, \u0027desirable\u0027, \u0027separate\u0027 and \u0027necessary\u0027 are fixed.\n\nSigned-off-by: Daniel Mack \u003cdaniel@caiaq.de\u003e\nCc: Joe Perches \u003cjoe@perches.com\u003e\nCc: Junio C Hamano \u003cgitster@pobox.com\u003e\nSigned-off-by: Jiri Kosina \u003cjkosina@suse.cz\u003e\n" }, { "commit": "838632438145ac6863377eb12d8b8eef9c55d288", "tree": "fbb0757df837f3c75a99c518a3596c38daef162d", "parents": [ "9996508b3353063f2d6c48c1a28a84543d72d70b", "29e553631b2a0d4eebd23db630572e1027a9967a" ], "author": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Tue Dec 01 15:16:22 2009 +0800" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Tue Dec 01 15:16:22 2009 +0800" }, "message": "Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6\n" }, { "commit": "68ee87164e73f68cf09070043c97e7f61e6966d4", "tree": "b06f6aac191d35fdb28d464cab686714565bd80e", "parents": [ "564ec0ec05ac6ee409bde81f7ef27a3dadbf3a6a" ], "author": { "name": "Jiri Kosina", "email": "jkosina@suse.cz", "time": "Mon Nov 23 20:19:47 2009 +0800" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Mon Nov 23 20:19:47 2009 +0800" }, "message": "crypto: ghash-clmulni-intel - Put proper .data section in place\n\nLbswap_mask, Lpoly and Ltwo_one should clearly belong to\n.data section, not .text.\n\nSigned-off-by: Jiri Kosina \u003cjkosina@suse.cz\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "564ec0ec05ac6ee409bde81f7ef27a3dadbf3a6a", "tree": "b4bb4e29cdfc2ceb90ac10ed4da139546375faa7", "parents": [ "b369e521237d6ef21c453f3ac4f4b8577ec14f87" ], "author": { "name": "Huang Ying", "email": "ying.huang@intel.com", "time": "Mon Nov 23 19:55:22 2009 +0800" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Mon Nov 23 19:55:22 2009 +0800" }, "message": "crypto: ghash-clmulni-intel - Use gas macro for PCLMULQDQ-NI and PSHUFB\n\nOld binutils do not support PCLMULQDQ-NI and PSHUFB, to make kernel\ncan be compiled by them, .byte code is used instead of assembly\ninstructions. But the readability and flexibility of raw .byte code is\nnot good.\n\nSo corresponding assembly instruction like gas macro is used instead.\n\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "b369e521237d6ef21c453f3ac4f4b8577ec14f87", "tree": "cedf1e4f1287c441d1afc29efd45c0f02f21c761", "parents": [ "fd650a6394b3242edf125ba9c4d500349a6d7178" ], "author": { "name": "Huang Ying", "email": "ying.huang@intel.com", "time": "Mon Nov 23 19:54:06 2009 +0800" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Mon Nov 23 19:54:06 2009 +0800" }, "message": "crypto: aesni-intel - Use gas macro for AES-NI instructions\n\nOld binutils do not support AES-NI instructions, to make kernel can be\ncompiled by them, .byte code is used instead of AES-NI assembly\ninstructions. But the readability and flexibility of raw .byte code is\nnot good.\n\nSo corresponding assembly instruction like gas macro is used instead.\n\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "01dd95827726534230d8f03f7e6faafe24e49260", "tree": "2b198f49ad60e96b8564897f65939c41dd7de2a3", "parents": [ "3b0d65969b549b796abc6f0230f6142fed365d49" ], "author": { "name": "Huang Ying", "email": "ying.huang@intel.com", "time": "Tue Nov 03 10:55:20 2009 -0500" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Tue Nov 03 10:55:20 2009 -0500" }, "message": "crypto: ghash-intel - Fix irq_fpu_usable usage\n\nWhen renaming kernel_fpu_using to irq_fpu_usable, the semantics of the\nfunction is changed too, from mesuring whether kernel is using FPU,\nthat is, the FPU is NOT available, to measuring whether FPU is usable,\nthat is, the FPU is available.\n\nBut the usage of irq_fpu_usable in ghash-clmulni-intel_glue.c is not\nchanged accordingly. This patch fixes this.\n\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "3b0d65969b549b796abc6f0230f6142fed365d49", "tree": "0cce8ac977df20e0902cda3d6092bcb6e90e03c1", "parents": [ "2d06ef7f42ed8c9969c9aa84e95df5d5c6378327" ], "author": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Tue Nov 03 09:11:15 2009 -0500" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Tue Nov 03 09:11:15 2009 -0500" }, "message": "crypto: ghash-intel - Add PSHUFB macros\n\nAdd PSHUFB macros instead of repeating byte sequences, suggested\nby Ingo.\n\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\nAcked-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "2d06ef7f42ed8c9969c9aa84e95df5d5c6378327", "tree": "20ff0f62949a957225cd1a021e20464cf85247a4", "parents": [ "3e02e5cb47e049727a26c9c110867a26972bd0d6" ], "author": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Sun Nov 01 12:49:44 2009 -0500" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Sun Nov 01 12:49:44 2009 -0500" }, "message": "crypto: ghash-intel - Hard-code pshufb\n\nOld gases don\u0027t have a clue what pshufb stands for so we have\nto hard-code it for now.\n\nReported-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "13b79b971564ddd0f14e706592472adc8199e912", "tree": "9e9b680352318aafe356c499dec9319cf25ac3e0", "parents": [ "4c6ab3ee4cdb86cbd4e9400dd22fad7701cbe795" ], "author": { "name": "Huang Ying", "email": "ying.huang@intel.com", "time": "Tue Oct 20 16:20:47 2009 +0900" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Tue Oct 20 16:20:47 2009 +0900" }, "message": "crypto: aesni-intel - Fix irq_fpu_usable usage\n\nWhen renaming kernel_fpu_using to irq_fpu_usable, the semantics of the\nfunction is changed too, from mesuring whether kernel is using FPU,\nthat is, the FPU is NOT available, to measuring whether FPU is usable,\nthat is, the FPU is available.\n\nBut the usage of irq_fpu_usable in aesni-intel_glue.c is not changed\naccordingly. This patch fixes this.\n\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "0e1227d356e9b2fe0500d6cc7084f752040a1e0e", "tree": "6f059b8e3c31539942ad244e7aadabcb54e8d904", "parents": [ "4c6ab3ee4cdb86cbd4e9400dd22fad7701cbe795" ], "author": { "name": "Huang Ying", "email": "ying.huang@intel.com", "time": "Mon Oct 19 11:53:06 2009 +0900" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Mon Oct 19 11:53:06 2009 +0900" }, "message": "crypto: ghash - Add PCLMULQDQ accelerated implementation\n\nPCLMULQDQ is used to accelerate the most time-consuming part of GHASH,\ncarry-less multiplication. More information about PCLMULQDQ can be\nfound at:\n\nhttp://software.intel.com/en-us/articles/carry-less-multiplication-and-its-usage-for-computing-the-gcm-mode/\n\nBecause PCLMULQDQ changes XMM state, its usage must be enclosed with\nkernel_fpu_begin/end, which can be used only in process context, the\nacceleration is implemented as crypto_ahash. That is, request in soft\nIRQ context will be defered to the cryptd kernel thread.\n\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "c7208de304ac335d5d58db346bb773a471fc636b", "tree": "47808484fc3ff8447fe30943a33880bae00d5fee", "parents": [ "15b0404272e1513940223cf9eefadfd22804a060", "5367b6887e7d8c870a5da7d9b8c6e9c207684e43" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Sep 14 07:57:32 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Sep 14 07:57:32 2009 -0700" }, "message": "Merge branch \u0027x86-cpu-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip\n\n* \u0027x86-cpu-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (22 commits)\n x86: Fix code patching for paravirt-alternatives on 486\n x86, msr: change msr-reg.o to obj-y, and export its symbols\n x86: Use hard_smp_processor_id() to get apic id for AMD K8 cpus\n x86, sched: Workaround broken sched domain creation for AMD Magny-Cours\n x86, mcheck: Use correct cpumask for shared bank4\n x86, cacheinfo: Fixup L3 cache information for AMD multi-node processors\n x86: Fix CPU llc_shared_map information for AMD Magny-Cours\n x86, msr: Fix msr-reg.S compilation with gas 2.16.1, on 32-bit too\n x86: Move kernel_fpu_using to irq_fpu_usable in asm/i387.h\n x86, msr: fix msr-reg.S compilation with gas 2.16.1\n x86, msr: Export the register-setting MSR functions via /dev/*/msr\n x86, msr: Create _on_cpu helpers for {rw,wr}msr_safe_regs()\n x86, msr: Have the _safe MSR functions return -EIO, not -EFAULT\n x86, msr: CFI annotations, cleanups for msr-reg.S\n x86, asm: Make _ASM_EXTABLE() usable from assembly code\n x86, asm: Add 32-bit versions of the combined CFI macros\n x86, AMD: Disable wrongly set X86_FEATURE_LAHF_LM CPUID bit\n x86, msr: Rewrite AMD rd/wrmsr variants\n x86, msr: Add rd/wrmsr interfaces with preset registers\n x86: add specific support for Intel Atom architecture\n ...\n" }, { "commit": "ae4b688db2432baad379f73fdcac13ec24f603d5", "tree": "e367ad761a6835fffeb25694f3308e9315d7ef3c", "parents": [ "f6909f394c2d4a0a71320797df72d54c49c5927e" ], "author": { "name": "Huang Ying", "email": "ying.huang@intel.com", "time": "Mon Aug 31 13:11:54 2009 +0800" }, "committer": { "name": "H. Peter Anvin", "email": "hpa@zytor.com", "time": "Tue Sep 01 21:39:15 2009 -0700" }, "message": "x86: Move kernel_fpu_using to irq_fpu_usable in asm/i387.h\n\nThis function measures whether the FPU/SSE state can be touched in\ninterrupt context. If the interrupted code is in user space or has no\nvalid FPU/SSE context (CR0.TS \u003d\u003d 1), FPU/SSE state can be used in IRQ\nor soft_irq context too.\n\nThis is used by AES-NI accelerated AES implementation and PCLMULQDQ\naccelerated GHASH implementation.\n\nv3:\n - Renamed to irq_fpu_usable to reflect the purpose of the function.\n\nv2:\n - Renamed to irq_is_fpu_using to reflect the real situation.\n\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nCC: H. Peter Anvin \u003chpa@zytor.com\u003e\nSigned-off-by: H. Peter Anvin \u003chpa@zytor.com\u003e\n" }, { "commit": "c9944881acf02b6f25fa62a0441a98b7dc0d7ae6", "tree": "264d1e88c293bf8d959d4cbceaa348325618629b", "parents": [ "215ccd6f55a2144bd553e0a3d12e1386f02309fd" ], "author": { "name": "Roland Dreier", "email": "rolandd@cisco.com", "time": "Wed Jun 24 13:42:40 2009 +0800" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Wed Jun 24 13:42:40 2009 +0800" }, "message": "crypto: aes-ni - Don\u0027t print message with KERN_ERR on old system\n\nWhen the aes-intel module is loaded on a system that does not have the\nAES instructions, it prints\n\n Intel AES-NI instructions are not detected.\n\nat level KERN_ERR. Since aes-intel is aliased to \"aes\" it will be tried\nwhenever anything uses AES and spam the console. This doesn\u0027t match\nexisting practice for how to handle \"no hardware\" when initializing a\nmodule, so downgrade the message to KERN_INFO.\n\nSigned-off-by: Roland Dreier \u003crolandd@cisco.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "b6f34d44cb341ad32f08717d1a2c418e6053a031", "tree": "220c1cb09bf5a0610cd285c7f36d3cef2dc8e918", "parents": [ "9251b64fb2d2326d28f0e0646a9e4fb8bbb51d8e" ], "author": { "name": "Huang Ying", "email": "ying.huang@intel.com", "time": "Thu Jun 18 19:44:01 2009 +0800" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Thu Jun 18 19:44:01 2009 +0800" }, "message": "crypto: aes-ni - Remove CRYPTO_TFM_REQ_MAY_SLEEP from fpu template\n\nkernel_fpu_begin/end used preempt_disable/enable, so sleep should be\nprevented between kernel_fpu_begin/end.\n\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "9251b64fb2d2326d28f0e0646a9e4fb8bbb51d8e", "tree": "2ef7e20387ee2646679c587abef236100684a7d6", "parents": [ "e6efaa025384f86a18814a6b9f4e5d54484ab9ff" ], "author": { "name": "Huang Ying", "email": "ying.huang@intel.com", "time": "Thu Jun 18 19:41:27 2009 +0800" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Thu Jun 18 19:41:27 2009 +0800" }, "message": "crypto: aes-ni - Do not sleep when using the FPU\n\nBecause AES-NI instructions will touch XMM state, corresponding code\nmust be enclosed within kernel_fpu_begin/end, which used\npreempt_disable/enable. So sleep should be prevented between\nkernel_fpu_begin/end.\n\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "e6efaa025384f86a18814a6b9f4e5d54484ab9ff", "tree": "e67688f905c8bbea2f35d4e001ef7790676a50e9", "parents": [ "8d8409f773af2cfd52e23e4b138a7d55a31182cd" ], "author": { "name": "Huang Ying", "email": "ying.huang@intel.com", "time": "Thu Jun 18 19:33:57 2009 +0800" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Thu Jun 18 19:33:57 2009 +0800" }, "message": "crypto: aes-ni - Fix cbc mode IV saving\n\nOriginal implementation of aesni_cbc_dec do not save IV if input\nlength % 4 \u003d\u003d 0. This will make decryption of next block failed.\n\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "2cf4ac8beb9dc50a315a6155b7b70e754d511958", "tree": "0c4043a1455ab581b4e505604df290acd59ef79e", "parents": [ "150c7e85526e80474b87004f4b420e8834fdeb43" ], "author": { "name": "Huang Ying", "email": "ying.huang@intel.com", "time": "Sun Mar 29 15:41:20 2009 +0800" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Tue Jun 02 14:04:16 2009 +1000" }, "message": "crypto: aes-ni - Add support for more modes\n\nBecause kernel_fpu_begin() and kernel_fpu_end() operations are too\nslow, the performance gain of general mode implementation + aes-aesni\nis almost all compensated.\n\nThe AES-NI support for more modes are implemented as follow:\n\n- Add a new AES algorithm implementation named __aes-aesni without\n kernel_fpu_begin/end()\n\n- Use fpu(\u003cmode\u003e(AES)) to provide kenrel_fpu_begin/end() invoking\n\n- Add \u003cmode\u003e(AES) ablkcipher, which uses cryptd(fpu(\u003cmode\u003e(AES))) to\n defer cryption to cryptd context in soft_irq context.\n\nNow the ctr, lrw, pcbc and xts support are added.\n\nPerformance testing based on dm-crypt shows that cryption time can be\nreduced to 50% of general mode implementation + aes-aesni implementation.\n\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "150c7e85526e80474b87004f4b420e8834fdeb43", "tree": "66ab693aadaacca850f222ac5fa248fddde3ac32", "parents": [ "505fd21d6138545aa5e96aa738975e6a9deb98a9" ], "author": { "name": "Huang Ying", "email": "ying.huang@intel.com", "time": "Sun Mar 29 15:39:02 2009 +0800" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Tue Jun 02 14:04:15 2009 +1000" }, "message": "crypto: fpu - Add template for blkcipher touching FPU\n\nBlkcipher touching FPU need to be enclosed by kernel_fpu_begin() and\nkernel_fpu_end(). If they are invoked in cipher algorithm\nimplementation, they will be invoked for each block, so that\nperformance will be hurt, because they are \"slow\" operations. This\npatch implements \"fpu\" template, which makes these operations to be\ninvoked for each request.\n\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "54b6a1bd5364aca95cd6ffae00f2b64c6511122c", "tree": "b1e288b009df7fefa92ce001d8709b04dd20663f", "parents": [ "1cac2cbc76b9f3fce0d4ccc374e724e7f2533a47" ], "author": { "name": "Huang Ying", "email": "ying.huang@intel.com", "time": "Sun Jan 18 16:28:34 2009 +1100" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Wed Feb 18 16:48:06 2009 +0800" }, "message": "crypto: aes-ni - Add support to Intel AES-NI instructions for x86_64 platform\n\nIntel AES-NI is a new set of Single Instruction Multiple Data (SIMD)\ninstructions that are going to be introduced in the next generation of\nIntel processor, as of 2009. These instructions enable fast and secure\ndata encryption and decryption, using the Advanced Encryption Standard\n(AES), defined by FIPS Publication number 197. The architecture\nintroduces six instructions that offer full hardware support for\nAES. Four of them support high performance data encryption and\ndecryption, and the other two instructions support the AES key\nexpansion procedure.\n\nThe white paper can be downloaded from:\n\nhttp://softwarecommunity.intel.com/isn/downloads/intelavx/AES-Instructions-Set_WP.pdf\n\nAES may be used in soft_irq context, but MMX/SSE context can not be\ntouched safely in soft_irq context. So in_interrupt() is checked, if\nin IRQ or soft_irq context, the general x86_64 implementation are used\ninstead.\n\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "07bf44f86989f5ed866510374fe761d1903681fb", "tree": "b7a4bbd3a66dd6fec0243a12f8569a4ad0fce9da", "parents": [ "109568e110ed67d4be1b28609b9fa00fca97f8eb" ], "author": { "name": "Huang Ying", "email": "ying.huang@intel.com", "time": "Fri Jan 09 17:25:50 2009 +1100" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Wed Feb 18 16:48:05 2009 +0800" }, "message": "crypto: aes - Export x86 AES encrypt/decrypt functions\n\nIntel AES-NI AES acceleration instructions touch XMM state, to use\nthat in soft_irq context, general x86 AES implementation is used as\nfallback. The first parameter is changed from struct crypto_tfm * to\nstruct crypto_aes_ctx * to make it easier to deal with 16 bytes\nalignment requirement of AES-NI implementation.\n\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "109568e110ed67d4be1b28609b9fa00fca97f8eb", "tree": "f40a1c6a35bb45abf7edcf8ab55ed75af6d405fb", "parents": [ "8eb2dfac41c71701bb741f496f0cb7b7e4a3c3f6" ], "author": { "name": "Huang Ying", "email": "ying.huang@intel.com", "time": "Fri Jan 09 16:49:30 2009 +1100" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Wed Feb 18 16:48:04 2009 +0800" }, "message": "crypto: aes - Move key_length in struct crypto_aes_ctx to be the last field\n\nThe Intel AES-NI AES acceleration instructions need key_enc, key_dec\nin struct crypto_aes_ctx to be 16 byte aligned, it make this easier to\nmove key_length to be the last one.\n\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "b7e8bdadce6317eb13c13b9451d7114614aa1450", "tree": "8a3ed3c64f5a96ce760dba5f79323b3e5b5e9dcc", "parents": [ "faccc4bba160784e834b758f23d598e500ac7108" ], "author": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Thu Nov 06 16:56:41 2008 +0800" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Thu Dec 25 11:01:37 2008 +1100" }, "message": "crypto: crc32c-intel - Switch to shash\n\nThis patch changes crc32c-intel to the new shash interface.\n\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "1c06da81a5d042d5fba67c4c533b16ae62a174ab", "tree": "a0f102a16d5d752a67b0a9119c575e689230bf90", "parents": [ "4b24ea971a93f5d0bec34bf7bfd0939f70cfaae6" ], "author": { "name": "Kent Liu", "email": "kent.liu@intel.com", "time": "Fri Oct 31 16:52:58 2008 +0800" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Thu Dec 25 11:01:18 2008 +1100" }, "message": "crypto: crc32c-intel - Update copyright head\n\nThe original copyright head for crc32c-intel.c is incorrect. Please merge\nthe patch to update it.\n\nSigned-Off-By: Kent Liu \u003ckent.liu@intel.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "8cb51ba8e06570a5fff674b3744d12a1b089f2d0", "tree": "cb46d2598a22aeffb68827b1d09fe4cb1dcd7612", "parents": [ "f139cfa7cdccd0b315fad098889897b5fcd389b0" ], "author": { "name": "Austin Zhang", "email": "austin.zhang@intel.com", "time": "Thu Aug 07 09:57:03 2008 +0800" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Fri Aug 29 15:49:50 2008 +1000" }, "message": "crypto: crc32c - Use Intel CRC32 instruction\n\nFrom NHM processor onward, Intel processors can support hardware accelerated\nCRC32c algorithm with the new CRC32 instruction in SSE 4.2 instruction set.\nThe patch detects the availability of the feature, and chooses the most proper\nway to calculate CRC32c checksum.\nByte code instructions are used for compiler compatibility.\nNo MMX / XMM registers is involved in the implementation.\n\nSigned-off-by: Austin Zhang \u003caustin.zhang@intel.com\u003e\nSigned-off-by: Kent Liu \u003ckent.liu@intel.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "744b5a28109e6a107c24a1426ee22f92b17995e9", "tree": "619ebb94279bd34fb72e10ff77449b11a55511f4", "parents": [ "d5dc392742a9818e2766a63f3533980543e18060" ], "author": { "name": "Sebastian Siewior", "email": "sebastian@breakpoint.cc", "time": "Tue Mar 11 21:29:47 2008 +0800" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Mon Apr 21 10:19:21 2008 +0800" }, "message": "[CRYPTO] aes-x86-32: Remove unused return code\n\nThe return parameter isn\u0027t used remove it.\n\nSigned-off-by: Sebastian Siewior \u003csebastian@breakpoint.cc\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" } ], "next": "15e7b4452b72ae890f2fcb027b4c4fa63a1c9a7a" }