)]}' { "log": [ { "commit": "4fa030a43ddb0d8fe3f2530d6162c11a3b3d31de", "tree": "3eb3dfd8d1fead497fb228ad46e6162908d6b912", "parents": [ "fdf7748b9f8d392a086560616bf112f0ba0c1f71" ], "author": { "name": "Sascha Hauer", "email": "s.hauer@pengutronix.de", "time": "Sun Mar 18 23:48:13 2012 +0100" }, "committer": { "name": "Sascha Hauer", "email": "s.hauer@pengutronix.de", "time": "Wed Apr 25 17:03:43 2012 +0200" }, "message": "dmaengine i.MX ipu: clk_prepare/unprepare clock\n\nSigned-off-by: Sascha Hauer \u003cs.hauer@pengutronix.de\u003e\n" }, { "commit": "185ecb5f4fd43911c35956d4cc7d94a1da30417f", "tree": "ebbdb7f15157d19d8af892cd7948d93947d09ec2", "parents": [ "16052827d98fbc13c31ebad560af4bd53e2b4dd5" ], "author": { "name": "Alexandre Bounine", "email": "alexandre.bounine@idt.com", "time": "Thu Mar 08 15:35:13 2012 -0500" }, "committer": { "name": "Vinod Koul", "email": "vinod.koul@linux.intel.com", "time": "Wed Mar 21 19:20:23 2012 +0530" }, "message": "dmaengine: add context parameter to prep_slave_sg and prep_dma_cyclic\n\nAdd context parameter to device_prep_slave_sg() and device_prep_dma_cyclic()\ninterfaces to allow passing client/target specific information associated\nwith the data transfer.\nModify all affected DMA engine drivers.\n\nSigned-off-by: Alexandre Bounine \u003calexandre.bounine@idt.com\u003e\nAcked-by: Linus Walleij \u003clinus.walleij@linaro.org\u003e\nAcked-by: Felipe Balbi \u003cbalbi@ti.com\u003e\nSigned-off-by: Vinod Koul \u003cvinod.koul@linux.intel.com\u003e\n" }, { "commit": "d3ee98cdcd6198ea1cf75c603178acc8a805b69b", "tree": "721f252d07d5e0596fa9b58a7c876dfd75823d0a", "parents": [ "96a2af41c78b1fbb1f567a3486bdc63f7b31c5fd" ], "author": { "name": "Russell King - ARM Linux", "email": "linux@arm.linux.org.uk", "time": "Tue Mar 06 22:35:47 2012 +0000" }, "committer": { "name": "Vinod Koul", "email": "vinod.koul@linux.intel.com", "time": "Tue Mar 13 11:37:22 2012 +0530" }, "message": "dmaengine: consolidate initialization of cookies\n\nProvide a common function to initialize a channels cookie values.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\nTested-by: Linus Walleij \u003clinus.walleij@linaro.org\u003e\nReviewed-by: Linus Walleij \u003clinus.walleij@linaro.org\u003e\nAcked-by: Jassi Brar \u003cjassisinghbrar@gmail.com\u003e\n[imx-sdma.c \u0026 mxs-dma.c]\nTested-by: Shawn Guo \u003cshawn.guo@linaro.org\u003e\nSigned-off-by: Vinod Koul \u003cvinod.koul@linux.intel.com\u003e\n" }, { "commit": "f7fbce07c6ce26a25b4e0cb5f241c361fde87901", "tree": "66e6321b5ef49e18479ffeb1ed4fd5169e120f97", "parents": [ "884485e1f12dcd39390f042e772cdbefc9ebb750" ], "author": { "name": "Russell King - ARM Linux", "email": "linux@arm.linux.org.uk", "time": "Tue Mar 06 22:35:07 2012 +0000" }, "committer": { "name": "Vinod Koul", "email": "vinod.koul@linux.intel.com", "time": "Tue Mar 13 11:37:01 2012 +0530" }, "message": "dmaengine: provide a common function for completing a dma descriptor\n\nProvide a common function to do the cookie mechanics for completing\na DMA descriptor.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\nTested-by: Linus Walleij \u003clinus.walleij@linaro.org\u003e\nReviewed-by: Linus Walleij \u003clinus.walleij@linaro.org\u003e\nAcked-by: Jassi Brar \u003cjassisinghbrar@gmail.com\u003e\n[imx-sdma.c \u0026 mxs-dma.c]\nTested-by: Shawn Guo \u003cshawn.guo@linaro.org\u003e\nSigned-off-by: Vinod Koul \u003cvinod.koul@linux.intel.com\u003e\n" }, { "commit": "884485e1f12dcd39390f042e772cdbefc9ebb750", "tree": "a35fccb601c48ae1ea839aa6d62e4f102f7b66c3", "parents": [ "d2ebfb335b0426deb1a4fb14e4e926d81ecd8235" ], "author": { "name": "Russell King - ARM Linux", "email": "linux@arm.linux.org.uk", "time": "Tue Mar 06 22:34:46 2012 +0000" }, "committer": { "name": "Vinod Koul", "email": "vinod.koul@linux.intel.com", "time": "Tue Mar 13 11:36:52 2012 +0530" }, "message": "dmaengine: consolidate assignment of DMA cookies\n\nEveryone deals with assigning DMA cookies in the same way (it\u0027s part of\nthe API so they should be), so lets consolidate the common code into a\nhelper function to avoid this duplication.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\nTested-by: Linus Walleij \u003clinus.walleij@linaro.org\u003e\nReviewed-by: Linus Walleij \u003clinus.walleij@linaro.org\u003e\nAcked-by: Jassi Brar \u003cjassisinghbrar@gmail.com\u003e\n[imx-sdma.c \u0026 mxs-dma.c]\nTested-by: Shawn Guo \u003cshawn.guo@linaro.org\u003e\nSigned-off-by: Vinod Koul \u003cvinod.koul@linux.intel.com\u003e\n" }, { "commit": "d2ebfb335b0426deb1a4fb14e4e926d81ecd8235", "tree": "222c90df3fe29a08de668d862ed25d203404c315", "parents": [ "4d4e58de32a192fea65ab84509d17d199bd291c8" ], "author": { "name": "Russell King - ARM Linux", "email": "linux@arm.linux.org.uk", "time": "Tue Mar 06 22:34:26 2012 +0000" }, "committer": { "name": "Vinod Koul", "email": "vinod.koul@linux.intel.com", "time": "Tue Mar 13 11:36:44 2012 +0530" }, "message": "dmaengine: add private header file\n\nAdd a local private header file to contain definitions and declarations\nwhich should only be used by DMA engine drivers.\n\nWe also fix linux/dmaengine.h to use LINUX_DMAENGINE_H to guard against\nmultiple inclusion.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\nTested-by: Linus Walleij \u003clinus.walleij@linaro.org\u003e\nReviewed-by: Linus Walleij \u003clinus.walleij@linaro.org\u003e\nAcked-by: Jassi Brar \u003cjassisinghbrar@gmail.com\u003e\n[imx-sdma.c \u0026 mxs-dma.c]\nTested-by: Shawn Guo \u003cshawn.guo@linaro.org\u003e\nSigned-off-by: Vinod Koul \u003cvinod.koul@linux.intel.com\u003e\n" }, { "commit": "4d4e58de32a192fea65ab84509d17d199bd291c8", "tree": "be35531778c9cc6bee73beb94d07e176a6f3599d", "parents": [ "08714f60b0fc6ea3a060b69b32e77139f14e6045" ], "author": { "name": "Russell King - ARM Linux", "email": "linux@arm.linux.org.uk", "time": "Tue Mar 06 22:34:06 2012 +0000" }, "committer": { "name": "Vinod Koul", "email": "vinod.koul@linux.intel.com", "time": "Tue Mar 13 11:36:06 2012 +0530" }, "message": "dmaengine: move last completed cookie into generic dma_chan structure\n\nEvery DMA engine implementation declares a last completed dma cookie\nin their private dma channel structures. This is pointless, and\nforces driver specific code. Move this out into the common dma_chan\nstructure.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\nTested-by: Linus Walleij \u003clinus.walleij@linaro.org\u003e\nReviewed-by: Linus Walleij \u003clinus.walleij@linaro.org\u003e\nAcked-by: Jassi Brar \u003cjassisinghbrar@gmail.com\u003e\n[imx-sdma.c \u0026 mxs-dma.c]\nTested-by: Shawn Guo \u003cshawn.guo@linaro.org\u003e\nSigned-off-by: Vinod Koul \u003cvinod.koul@linux.intel.com\u003e\n" }, { "commit": "c99e78435342a65a6a0bf9b86f87fd05831858d2", "tree": "b9aa68bc64326a819e0550c85bb4483a90b81b43", "parents": [ "5cd326fd27da347925019fcc041b79bad8dd55ed" ], "author": { "name": "Sascha Hauer", "email": "s.hauer@pengutronix.de", "time": "Thu Dec 01 14:58:51 2011 +0100" }, "committer": { "name": "Vinod Koul", "email": "vinod.koul@linux.intel.com", "time": "Thu Dec 08 12:59:03 2011 +0530" }, "message": "i.MX IPU DMA: Fix wrong burstsize settings\n\nThe burstsize (npb in struct chan_param_mem) is set in\nipu_ch_param_set_size() once. The number of allowed\npixels in a burst depend on the pixel format and the\nrotation mode. For 16bit formats 16 pixels are allowed\nwhereas for 32bit formats only 8 pixels are allowed.\nSet these values correctly in ipu_ch_param_set_size()\nand do not overwrite them afterwards.\nWe do not support rotation right now, so ignore this\ncase.\nThis patch fixes the wrong burstsize setting of 16 pixels\nfor 32bpp.\n\nSigned-off-by: Sascha Hauer \u003cs.hauer@pengutronix.de\u003e\nSigned-off-by: Vinod Koul \u003cvinod.koul@linux.intel.com\u003e\n" }, { "commit": "e0d23ef29ed637dc6bd739f590985746d9ad9caa", "tree": "c5b5856dc88582697997bb10ccacad6fc2535465", "parents": [ "ca7fe2db892dcf91b2c72ee352eda4ff867903a7", "55ba4e5ed4ac57b60fe56acfd324f6a87123cc34" ], "author": { "name": "Vinod Koul", "email": "vinod.koul@linux.intel.com", "time": "Thu Nov 17 14:54:38 2011 +0530" }, "committer": { "name": "Vinod Koul", "email": "vinod.koul@linux.intel.com", "time": "Thu Nov 17 14:54:57 2011 +0530" }, "message": "Merge branch \u0027dma_slave_direction\u0027 into next_test_dirn\n\nresolved conflicts:\n\tdrivers/media/video/mx3_camera.c\n" }, { "commit": "32aaeffbd4a7457bf2f7448b33b5946ff2a960eb", "tree": "faf7ad871d87176423ff9ed1d1ba4d9c688fc23f", "parents": [ "208bca0860406d16398145ddd950036a737c3c9d", "67b84999b1a8b1af5625b1eabe92146c5eb42932" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sun Nov 06 19:44:47 2011 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sun Nov 06 19:44:47 2011 -0800" }, "message": "Merge branch \u0027modsplit-Oct31_2011\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/paulg/linux\n\n* \u0027modsplit-Oct31_2011\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/paulg/linux: (230 commits)\n Revert \"tracing: Include module.h in define_trace.h\"\n irq: don\u0027t put module.h into irq.h for tracking irqgen modules.\n bluetooth: macroize two small inlines to avoid module.h\n ip_vs.h: fix implicit use of module_get/module_put from module.h\n nf_conntrack.h: fix up fallout from implicit moduleparam.h presence\n include: replace linux/module.h with \"struct module\" wherever possible\n include: convert various register fcns to macros to avoid include chaining\n crypto.h: remove unused crypto_tfm_alg_modname() inline\n uwb.h: fix implicit use of asm/page.h for PAGE_SIZE\n pm_runtime.h: explicitly requires notifier.h\n linux/dmaengine.h: fix implicit use of bitmap.h and asm/page.h\n miscdevice.h: fix up implicit use of lists and types\n stop_machine.h: fix implicit use of smp.h for smp_processor_id\n of: fix implicit use of errno.h in include/linux/of.h\n of_platform.h: delete needless include \u003clinux/module.h\u003e\n acpi: remove module.h include from platform/aclinux.h\n miscdevice.h: delete unnecessary inclusion of module.h\n device_cgroup.h: delete needless include \u003clinux/module.h\u003e\n net: sch_generic remove redundant use of \u003clinux/module.h\u003e\n net: inet_timewait_sock doesnt need \u003clinux/module.h\u003e\n ...\n\nFix up trivial conflicts (other header files, and removal of the ab3550 mfd driver) in\n - drivers/media/dvb/frontends/dibx000_common.c\n - drivers/media/video/{mt9m111.c,ov6650.c}\n - drivers/mfd/ab3550-core.c\n - include/linux/dmaengine.h\n" }, { "commit": "1d3564d91f94d0b598304eb6ebe3b83a83176f7a", "tree": "585a122d4ca32f02d65cb24267c5570842567e95", "parents": [ "2d86401c2cbfce9f99b08ba168bdb60b2eb7796e" ], "author": { "name": "Guennadi Liakhovetski", "email": "g.liakhovetski@gmx.de", "time": "Thu Aug 25 13:26:53 2011 -0300" }, "committer": { "name": "Mauro Carvalho Chehab", "email": "mchehab@redhat.com", "time": "Thu Nov 03 18:28:33 2011 -0200" }, "message": "[media] dmaengine: ipu-idmac: add support for the DMA_PAUSE control\n\nTo support multi-size buffers in the mx3_camera V4L2 driver we have to be\nable to stop DMA on a channel without releasing descriptors and completely\nhalting the hardware. Use the DMA_PAUSE control to implement this mode.\n\nSigned-off-by: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nAcked-by: Vinod Koul \u003cvinod.koul@linux.intel.com\u003e\nSigned-off-by: Mauro Carvalho Chehab \u003cmchehab@redhat.com\u003e\n" }, { "commit": "5c45ad77ffd0108596627816a37de71a04d5cb6d", "tree": "c25ddf76be050899e646df8ea99b10482d2e47be", "parents": [ "3382416d867d1c70709dfb03e4a81d5731d96787" ], "author": { "name": "Paul Gortmaker", "email": "paul.gortmaker@windriver.com", "time": "Sun Jul 31 16:14:17 2011 -0400" }, "committer": { "name": "Paul Gortmaker", "email": "paul.gortmaker@windriver.com", "time": "Mon Oct 31 19:31:44 2011 -0400" }, "message": "drivers/dma: Add module.h to files implicitly using it.\n\nFix files that were implicitly using module.h but not\ncalling it out for inclusion directly. We\u0027ll break those\nonce we remove the implicit presence otherwise\n\n[With input from Uwe Kleine-König \u003cu.kleine-koenig@pengutronix.de\u003e]\n\nSigned-off-by: Paul Gortmaker \u003cpaul.gortmaker@windriver.com\u003e\n" }, { "commit": "db8196df4bb6f117caa163aa73b0f16fd62290bd", "tree": "b86531031482037d9b31ad57479f2f7091020957", "parents": [ "49920bc66984a512f4bcc7735a61642cd0e4d6f2" ], "author": { "name": "Vinod Koul", "email": "vinod.koul@linux.intel.com", "time": "Thu Oct 13 22:34:23 2011 +0530" }, "committer": { "name": "Vinod Koul", "email": "vinod.koul@linux.intel.com", "time": "Thu Oct 27 20:53:43 2011 +0530" }, "message": "dmaengine: move drivers to dma_transfer_direction\n\nfixup usage of dma direction by introducing dma_transfer_direction,\nthis patch moves dma/drivers/* to use new enum\n\nCc: Jassi Brar \u003cjaswinder.singh@linaro.org\u003e\nCc: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\nCc: Viresh Kumar \u003cviresh.kumar@st.com\u003e\nCc: Linus Walleij \u003clinus.walleij@linaro.org\u003e\nCc: Nicolas Ferre \u003cnicolas.ferre@atmel.com\u003e\nCc: Mika Westerberg \u003cmika.westerberg@iki.fi\u003e\nCc: H Hartley Sweeten \u003chartleys@visionengravers.com\u003e\nCc: Li Yang \u003cleoli@freescale.com\u003e\nCc: Zhang Wei \u003czw@zh-kernel.org\u003e\nCc: Sascha Hauer \u003cs.hauer@pengutronix.de\u003e\nCc: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nCc: Shawn Guo \u003cshawn.guo@freescale.com\u003e\nCc: Yong Wang \u003cyong.y.wang@intel.com\u003e\nCc: Tomoya MORINAGA \u003ctomoya-linux@dsn.lapis-semi.com\u003e\nCc: Boojin Kim \u003cboojin.kim@samsung.com\u003e\nCc: Barry Song \u003cBaohua.Song@csr.com\u003e\nAcked-by: Mika Westerberg \u003cmika.westerberg@iki.fi\u003e\nAcked-by: Linus Walleij \u003clinus.walleij@linaro.org\u003e\nAcked-by: Viresh Kumar \u003cviresh.kumar@st.com\u003e\nAcked-by: Nicolas Ferre \u003cnicolas.ferre@atmel.com\u003e\nSigned-off-by: Vinod Koul \u003cvinod.koul@linux.intel.com\u003e\n" }, { "commit": "289b4e7a48d91fbef7af819020d826ad9f49f568", "tree": "c3155c141dc976c5c2d404e4cc4c99c278cce58f", "parents": [ "bd31b85960a7fcb2d7ede216460b8da71a88411c" ], "author": { "name": "Uwe Kleine-König", "email": "u.kleine-koenig@pengutronix.de", "time": "Fri Jul 29 16:27:07 2011 +0200" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Tue Sep 13 11:12:15 2011 +0200" }, "message": "locking, dma, ipu: Annotate bank_lock as raw\n\nThe bank_lock can be taken in atomic context (irq handling)\nand therefore cannot be preempted on -rt - annotate it.\n\nIn mainline this change documents the low level nature of\nthe lock - otherwise there\u0027s no functional difference. Lockdep\nand Sparse checking will work as usual.\n\nSigned-off-by: Uwe Kleine-König \u003cu.kleine-koenig@pengutronix.de\u003e\nCc: kernel@pengutronix.de\nCc: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nCc: Dan Williams \u003cdan.j.williams@intel.com\u003e\nLink: http://lkml.kernel.org/r/1311949627-13260-1-git-send-email-u.kleine-koenig@pengutronix.de\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "12ff47e7f5fb64c566f62e6cf6a3b291c51bd337", "tree": "d9fba3780142af380ccfaf90d8b13363e3475bd7", "parents": [ "73bcbac130a59f236ae78ed70ef7a05b45caa19e", "1ae105aa7416087f2920c35c3cd16831d0d09c9c" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Aug 01 13:46:37 2011 -1000" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Aug 01 13:46:37 2011 -1000" }, "message": "Merge branch \u0027for-linus\u0027 of git://git.infradead.org/users/vkoul/slave-dma\n\n* \u0027for-linus\u0027 of git://git.infradead.org/users/vkoul/slave-dma: (37 commits)\n Improve slave/cyclic DMA engine documentation\n dmaengine: pl08x: handle the rest of enums in pl08x_width\n DMA: PL08x: cleanup selection of burst size\n DMA: PL08x: avoid recalculating cctl at each prepare\n DMA: PL08x: cleanup selection of buswidth\n DMA: PL08x: constify plchan-\u003ecd and plat-\u003eslave_channels\n DMA: PL08x: separately store source/destination cctl\n DMA: PL08x: separately store source/destination slave address\n DMA: PL08x: clean up LLI debugging\n DMA: PL08x: select LLI bus only once per LLI setup\n DMA: PL08x: remove unused constants\n ARM: mxs-dma: reset after disable channel\n dma: intel_mid_dma: remove redundant pci_set_drvdata calls\n dma: mxs-dma: fix unterminated platform_device_id table\n dmaengine: pl330: make platform data optional\n dmaengine: imx-sdma: return proper error if kzalloc fails\n pch_dma: Fix CTL register access issue\n dmaengine: mxs-dma: skip request_irq for NO_IRQ\n dmaengine/coh901318: fix slave submission semantics\n dmaengine/ste_dma40: allow memory buswidth/burst to be configured\n ...\n\nFix trivial whitespace conflict in drivers/dma/mv_xor.c\n" }, { "commit": "b7f080cfe223b3b7424872639d153695615a9255", "tree": "605390854789a6ba53e6813ffc69a948a0466530", "parents": [ "4003b65871c101eb5ce8f37a325feac54aa5c681" ], "author": { "name": "Alexey Dobriyan", "email": "adobriyan@gmail.com", "time": "Thu Jun 16 11:01:34 2011 +0000" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Jun 21 19:17:20 2011 -0700" }, "message": "net: remove mm.h inclusion from netdevice.h\n\nRemove linux/mm.h inclusion from netdevice.h -- it\u0027s unused (I\u0027ve checked manually).\n\nTo prevent mm.h inclusion via other channels also extract \"enum dma_data_direction\"\ndefinition into separate header. This tiny piece is what gluing netdevice.h with mm.h\nvia \"netdevice.h \u003d\u003e dmaengine.h \u003d\u003e dma-mapping.h \u003d\u003e scatterlist.h \u003d\u003e mm.h\".\nRemoval of mm.h from scatterlist.h was tried and was found not feasible\non most archs, so the link was cutoff earlier.\n\nHope people are OK with tiny include file.\n\nNote, that mm_types.h is still dragged in, but it is a separate story.\n\nSigned-off-by: Alexey Dobriyan \u003cadobriyan@gmail.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "7dab35c0c01c5d960d7b551a607270adccfadb42", "tree": "c0846a1c89357661ff19cf9610c7b9f88a1a07e3", "parents": [ "d41071575b0b20b780bb0e8e7e70c62c1b07a883" ], "author": { "name": "H Hartley Sweeten", "email": "hartleys@visionengravers.com", "time": "Wed Jun 01 15:10:30 2011 -0700" }, "committer": { "name": "Vinod Koul", "email": "vinod.koul@intel.com", "time": "Mon Jun 06 13:43:59 2011 +0530" }, "message": "dma: ipu_idmac.c: use resource_size in ioremap\n\nSigned-off-by: H Hartley Sweeten \u003chsweeten@visionengravers.com\u003e\nCc: Dan Williams \u003cdan.j.williams@intel.com\u003e\nCc: Vinod Koul \u003cvinod.koul@intel.com\u003e\nCc: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nCc: Anatolij Gustschin \u003cagust@denx.de\u003e\nSigned-off-by: Vinod Koul \u003cvinod.koul@intel.com\u003e\n" }, { "commit": "6a03513825db4db57fa93821a0c04dbbb39a68e6", "tree": "cddcf6a74ee0022d62218bf4a6caf6f4fe952b0c", "parents": [ "ab7798ffcf98b11a9525cf65bacdae3fd58d357f" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Fri Mar 25 12:21:38 2011 +0100" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Fri Mar 25 22:09:00 2011 +0100" }, "message": "dma: Ipu: Convert interupt code\n\nConvert to the new irq chip functions and cleanup the name space.\n\n[ Guennadi reported: irq_data_get_chip_data is undefined. Yes, I screwed up. \n it needs to be irq_data_get_irq_chip_data ]\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nTested-by: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nCc: Dan Williams \u003cdan.j.williams@intel.com\u003e\nLKML-Reference: \u003calpine.LFD.2.00.1103251220000.31464@localhost6.localdomain6\u003e\n" }, { "commit": "a646bd7f0824d3e0f02ff8d7410704f965de01bc", "tree": "8504b83156a36ce508821a334b67d8a55b7dca89", "parents": [ "8179661694595eb3a4f2ff9bb0b73acbb7d2f4a9" ], "author": { "name": "Anatolij Gustschin", "email": "agust@denx.de", "time": "Mon Jan 31 13:22:29 2011 +0100" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Feb 14 02:28:16 2011 -0800" }, "message": "dma: ipu_idmac: do not lose valid received data in the irq handler\n\nCurrently when two or more buffers are queued by the camera driver\nand so the double buffering is enabled in the idmac, we lose one\nframe comming from CSI since the reporting of arrival of the first\nframe is deferred by the DMAIC_7_EOF interrupt handler and reporting\nof the arrival of the last frame is not done at all. So when requesting\nN frames from the image sensor we actually receive N - 1 frames in\nuser space.\n\nThe reason for this behaviour is that the DMAIC_7_EOF interrupt\nhandler misleadingly assumes that the CUR_BUF flag is pointing to the\nbuffer used by the IDMAC. Actually it is not the case since the\nCUR_BUF flag will be flipped by the FSU when the FSU is sending the\n\u003cTASK\u003e_NEW_FRM_RDY signal when new frame data is delivered by the CSI.\nWhen sending this singal, FSU updates the DMA_CUR_BUF and the\nDMA_BUFx_RDY flags: the DMA_CUR_BUF is flipped, the DMA_BUFx_RDY\nis cleared, indicating that the frame data is beeing written by\nthe IDMAC to the pointed buffer. DMA_BUFx_RDY is supposed to be\nset to the ready state again by the MCU, when it has handled the\nreceived data. DMAIC_7_CUR_BUF flag won\u0027t be flipped here by the\nIPU, so waiting for this event in the EOF interrupt handler is wrong.\nActually there is no spurious interrupt as described in the comments,\nthis is the valid DMAIC_7_EOF interrupt indicating reception of the\nframe from CSI.\n\nThe patch removes code that waits for flipping of the DMAIC_7_CUR_BUF\nflag in the DMAIC_7_EOF interrupt handler. As the comment in the\ncurrent code denotes, this waiting doesn\u0027t help anyway. As a result\nof this removal the reporting of the first arrived frame is not\ndeferred to the time of arrival of the next frame and the drivers\nsoftware flag \u0027ichan-\u003eactive_buffer\u0027 is in sync with DMAIC_7_CUR_BUF\nflag, so the reception of all requested frames works.\n\nThis has been verified on the hardware which is triggering the\nimage sensor by the programmable state machine, allowing to\nobtain exact number of frames. On this hardware we do not tolerate\nlosing frames.\n\nThis patch also removes resetting the DMA_BUFx_RDY flags of\nall channels in ipu_disable_channel() since transfers on other\nDMA channels might be triggered by other running tasks and the\nbuffers should always be ready for data sending or reception.\n\nSigned-off-by: Anatolij Gustschin \u003cagust@denx.de\u003e\nReviewed-by: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nTested-by: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "058276303dbc4ed089c1f7dad0871810b1f5ddf1", "tree": "df26ff701721b2a91d61bd29e48bad7cbcedd746", "parents": [ "4aed79b2818e7330b5d00143e4c20bc6555df91f" ], "author": { "name": "Linus Walleij", "email": "linus.walleij@stericsson.com", "time": "Mon May 17 16:30:42 2010 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon May 17 16:30:42 2010 -0700" }, "message": "DMAENGINE: extend the control command to include an arg\n\nThis adds an argument to the DMAengine control function, so that\nwe can later provide control commands that need some external data\npassed in through an argument akin to the ioctl() operation\nprototype.\n\n[dan.j.williams@intel.com: fix up some missed conversions]\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "bca3469205402d9fb14060d255d8786ae2256640", "tree": "3b0c7f246fb9a6eafd3a82dd621dd9753589b3f4", "parents": [ "0793448187643b50af89d36b08470baf45a3cab4" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Fri Mar 26 16:52:10 2010 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Fri Mar 26 16:52:10 2010 -0700" }, "message": "dmaengine: provide helper for setting txstate\n\nSimple conditional struct filler to cut out some duplicated code.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "0793448187643b50af89d36b08470baf45a3cab4", "tree": "b3313ff58d47e26a8cf707d196177effa1aadfbe", "parents": [ "c3635c78e500a52c9fcd55de381a72928d9e054d" ], "author": { "name": "Linus Walleij", "email": "linus.walleij@stericsson.com", "time": "Fri Mar 26 16:50:49 2010 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Fri Mar 26 16:50:49 2010 -0700" }, "message": "DMAENGINE: generic channel status v2\n\nConvert the device_is_tx_complete() operation on the\nDMA engine to a generic device_tx_status()operation which\ncan return three states, DMA_TX_RUNNING, DMA_TX_COMPLETE,\nDMA_TX_PAUSED.\n\n[dan.j.williams@intel.com: update for timberdale]\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nAcked-by: Mark Brown \u003cbroonie@opensource.wolfsonmicro.com\u003e\nCc: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nCc: Nicolas Ferre \u003cnicolas.ferre@atmel.com\u003e\nCc: Pavel Machek \u003cpavel@ucw.cz\u003e\nCc: Li Yang \u003cleoli@freescale.com\u003e\nCc: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nCc: Paul Mundt \u003clethal@linux-sh.org\u003e\nCc: Ralf Baechle \u003cralf@linux-mips.org\u003e\nCc: Haavard Skinnemoen \u003chaavard.skinnemoen@atmel.com\u003e\nCc: Magnus Damm \u003cdamm@opensource.se\u003e\nCc: Liam Girdwood \u003clrg@slimlogic.co.uk\u003e\nCc: Joe Perches \u003cjoe@perches.com\u003e\nCc: Roland Dreier \u003crdreier@cisco.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "c3635c78e500a52c9fcd55de381a72928d9e054d", "tree": "87403f402227cd8b5572550e70facf81c9eaa0d9", "parents": [ "0f65169b1bf44220308e1ce1f6666ad03ddc27af" ], "author": { "name": "Linus Walleij", "email": "linus.walleij@stericsson.com", "time": "Fri Mar 26 16:44:01 2010 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Fri Mar 26 16:44:01 2010 -0700" }, "message": "DMAENGINE: generic slave control v2\n\nConvert the device_terminate_all() operation on the\nDMA engine to a generic device_control() operation\nwhich can now optionally support also pausing and\nresuming DMA on a certain channel. Implemented for the\nCOH 901 318 DMAC as an example.\n\n[dan.j.williams@intel.com: update for timberdale]\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nAcked-by: Mark Brown \u003cbroonie@opensource.wolfsonmicro.com\u003e\nCc: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nCc: Nicolas Ferre \u003cnicolas.ferre@atmel.com\u003e\nCc: Pavel Machek \u003cpavel@ucw.cz\u003e\nCc: Li Yang \u003cleoli@freescale.com\u003e\nCc: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nCc: Paul Mundt \u003clethal@linux-sh.org\u003e\nCc: Ralf Baechle \u003cralf@linux-mips.org\u003e\nCc: Haavard Skinnemoen \u003chaavard.skinnemoen@atmel.com\u003e\nCc: Magnus Damm \u003cdamm@opensource.se\u003e\nCc: Liam Girdwood \u003clrg@slimlogic.co.uk\u003e\nCc: Joe Perches \u003cjoe@perches.com\u003e\nCc: Roland Dreier \u003crdreier@cisco.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "dd58ffcf5a5352fc10820c8ffbcd5fed416a2c3a", "tree": "f36172b40f9f3fc2c646f70da40e01705399b6b8", "parents": [ "aa4d72ae946a4fa40486b871717778734184fa29", "56a5d3cf21c71963c8fc506e9b9d3f71641d9c71" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 03 21:22:21 2010 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 03 21:22:21 2010 -0700" }, "message": "Merge branch \u0027coh\u0027 into dmaengine\n" }, { "commit": "8f98781e0f15207b6ab33bee1fae05428be0475b", "tree": "31830720fd57bd11191e85bbdc98eaefe061f127", "parents": [ "b953df7c70740cd7593072ebec77a8f658505630" ], "author": { "name": "Guennadi Liakhovetski", "email": "g.liakhovetski@gmx.de", "time": "Wed Feb 10 17:32:38 2010 +0100" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Feb 10 12:01:06 2010 -0700" }, "message": "async-tx: fix buffer submission error handling in ipu_idma.c\n\nIf submitting new buffer failed, a wrong descriptor gets completed and it\ndoesn\u0027t check, if a callback is at all defined, which can lead to an Oops. Fix\nthese bugs and make ipu_update_channel_buffer() void, because it never fails.\n\nSigned-off-by: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "9ad7bd2944bd979ef4877cd439719be44c5f3b47", "tree": "cf70d092016d677b68b4178b7f669939c3820b63", "parents": [ "4b1cf1facca31b7db2a61d8aa2ba40d5a93a0957" ], "author": { "name": "Roel Kluin", "email": "roel.kluin@gmail.com", "time": "Wed Jan 20 01:25:56 2010 +0100" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Feb 02 23:42:25 2010 -0700" }, "message": "dma: cases IPU_PIX_FMT_BGRA32, BGR32 and ABGR32 are the same in ipu_ch_param_set_size()\n\nIn these cases the same statements are executed.\n\nSigned-off-by: Roel Kluin \u003croel.kluin@gmail.com\u003e\nAcked-by: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "ad567ffb32f067b30606071eb568cf637fe42185", "tree": "0913e4e6cc06dd59a5a8a2367d30a2e46fad649f", "parents": [ "4f005dbe5584fe54c9f6d6d4f0acd3fb29be84da" ], "author": { "name": "Guennadi Liakhovetski", "email": "g.liakhovetski@gmx.de", "time": "Tue May 12 09:16:29 2009 +0200" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue May 12 14:41:48 2009 -0700" }, "message": "dma: fix ipu_idmac.c to not discard the last queued buffer\n\nThis also fixes the case of a single queued buffer, for example, when taking a\nsingle frame snapshot with the mx3_camera driver.\n\nReported-by: Agustin Ferrin Pozuelo \u003cgatoguan-os@yahoo.com\u003e\nTested-by: Agustin Ferrin Pozuelo \u003cgatoguan-os@yahoo.com\u003e\nSigned-off-by: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "ca50a51e890b0a62b44b5642c1ba5049909e5a8b", "tree": "d5804f7a5ab5760e996093690654df3a59e9adf8", "parents": [ "c56c81abe7e684bc6203632d807303eb765690dc" ], "author": { "name": "Ben Nizette", "email": "bn@niasdigital.com", "time": "Thu Apr 16 05:54:12 2009 +1000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue May 05 12:16:56 2009 -0700" }, "message": "ipu_idmac: Use disable_irq_nosync() from within irq handlers.\n\ndisable_irq() should wait for all running handlers to complete\nbefore returning. As such, if it\u0027s used to disable an interrupt\nfrom that interrupt\u0027s handler it will deadlock. This replaces\nthe dangerous instances with the _nosync() variant which doesn\u0027t\nhave this problem.\n\nNote the 2 handlers in question are only used #ifdef DEBUG so\nI imagine these code paths don\u0027t get hit often.\n\nSigned-off-by: Ben Nizette \u003cbn@niasdigital.com\u003e\nAcked-by: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "133e2a3164771454aa326859c2b293687189b553", "tree": "4e21f63be087738d7ffe7526d41e15140fc63ff0", "parents": [ "20bec8ab1458c24bed0d5492ee15d87807fc415a", "8c6db1bbf80123839ec87bdd6cb364aea384623d" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Apr 03 12:13:45 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Apr 03 12:13:45 2009 -0700" }, "message": "Merge branch \u0027next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx\n\n* \u0027next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx:\n dma: Add SoF and EoF debugging to ipu_idmac.c, minor cleanup\n dw_dmac: add cyclic API to DW DMA driver\n dmaengine: Add privatecnt to revert DMA_PRIVATE property\n dmatest: add dma interrupts and callbacks\n dmatest: add xor test\n dmaengine: allow dma support for async_tx to be toggled\n async_tx: provide __async_inline for HAS_DMA\u003dn archs\n dmaengine: kill some unused headers\n dmaengine: initialize tx_list in dma_async_tx_descriptor_init\n dma: i.MX31 IPU DMA robustness improvements\n dma: improve section assignment in i.MX31 IPU DMA driver\n dma: ipu_idmac driver cosmetic clean-up\n dmaengine: fail device registration if channel registration fails\n" }, { "commit": "8c6db1bbf80123839ec87bdd6cb364aea384623d", "tree": "848b8d42f093c03a046bd9ae204b360b5174ea28", "parents": [ "d9de451989a88a2003ca06e524aca4665c0c7f06" ], "author": { "name": "Guennadi Liakhovetski", "email": "lg@denx.de", "time": "Thu Apr 02 11:36:58 2009 +0200" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Apr 02 16:59:10 2009 -0700" }, "message": "dma: Add SoF and EoF debugging to ipu_idmac.c, minor cleanup\n\nAdd Start-of-Frame and End-of-Frame debugging to ipu_idmac.c, in the\nfuture it might also be needed for the actual video processing in\nmx3-camera, at which point, the ISRs will have to be transferred to\nmx3_camera.c, for which ipu_irq_map() and ipu_irq_unmap() functions will\nhave to be exported.\n\nAlso simplify a couple of pointer-dereferences.\n\nSigned-off-by: Guennadi Liakhovetski \u003clg@denx.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "ccccce229c633a92c42cd1a40c0738d7b0d12644", "tree": "a954537ae73f2e03c4431b244796cdc255af7a10", "parents": [ "8d47bae004f062630f69f7f83d098424252e232d" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 25 09:13:24 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 25 09:13:24 2009 -0700" }, "message": "dmaengine: initialize tx_list in dma_async_tx_descriptor_init\n\nCentralize this common initialization (and one case where ipu_idmac is\nduplicating -\u003echan initialization).\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "8d47bae004f062630f69f7f83d098424252e232d", "tree": "68379790587eef10926d029ffce74b763175b10c", "parents": [ "234f2df56f5b05756c444edc9879145deddf69f4" ], "author": { "name": "Guennadi Liakhovetski", "email": "g.liakhovetski@gmx.de", "time": "Wed Mar 25 09:13:24 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 25 09:13:24 2009 -0700" }, "message": "dma: i.MX31 IPU DMA robustness improvements\n\nAdd DMA error handling to the ISR, move common code fragments to functions, fix\nscatter-gather element queuing in the ISR, survive channel freeing and\nre-allocation in a quick succession.\n\nSigned-off-by: Guennadi Liakhovetski \u003clg@denx.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "234f2df56f5b05756c444edc9879145deddf69f4", "tree": "6946d1561e3243cbb4046652d1d70b647bb7947d", "parents": [ "0149f7d5dc66dcffbb044ba005a5378a5864d2a3" ], "author": { "name": "Guennadi Liakhovetski", "email": "lg@denx.de", "time": "Wed Mar 25 09:13:24 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 25 09:13:24 2009 -0700" }, "message": "dma: improve section assignment in i.MX31 IPU DMA driver\n\nThe i.MX31 IPU DMA driver is a platform driver, but doesn\u0027t need hotplug, so we\ncan use __init and __exit function attributes.\n\nSigned-off-by: Guennadi Liakhovetski \u003clg@denx.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "0149f7d5dc66dcffbb044ba005a5378a5864d2a3", "tree": "9ba399f0c71d62d23563d74308a58cc7eb5baf62", "parents": [ "257b17ca030387cb17314cd1851507bdd1b4ddd5" ], "author": { "name": "Guennadi Liakhovetski", "email": "lg@denx.de", "time": "Wed Mar 25 09:13:23 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 25 09:13:23 2009 -0700" }, "message": "dma: ipu_idmac driver cosmetic clean-up\n\nRemove superfluous semicolons, update comments.\n\nSigned-off-by: Guennadi Liakhovetski \u003clg@denx.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "9eb2eb8c40ffd30da322648c4415bae0288eb167", "tree": "b2402fd33314e4a78d11d8429c86ffe15cac8d4c", "parents": [ "9a51157bab06ab54d6ee442e34fe9574ff14c8c3" ], "author": { "name": "Sascha Hauer", "email": "s.hauer@pengutronix.de", "time": "Wed Feb 18 11:55:33 2009 +0100" }, "committer": { "name": "Sascha Hauer", "email": "s.hauer@pengutronix.de", "time": "Fri Mar 13 10:34:32 2009 +0100" }, "message": "MX31 clkdev support\n\nThis patch adds clkdev support for i.MX31. This is done in a\nsimilar way done previously for i.MX27\n\nSigned-off-by: Sascha Hauer \u003cs.hauer@pengutronix.de\u003e\n" }, { "commit": "c74ef1f867d18171c8617519ee5fe40b02903934", "tree": "35aacfe4325ecf38bea4ec484444fc4b04d66b6d", "parents": [ "a09b09ae51ace43d28cd9bc1c8bb97986f2b55a6" ], "author": { "name": "Luotao Fu", "email": "l.fu@pengutronix.de", "time": "Thu Feb 26 12:29:20 2009 +0100" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 04 16:04:41 2009 -0700" }, "message": "ipu_idmac: fix spinlock type\n\nfix a probably accidently dropped reference operator while calling\nspin_unlock_restore to an ipu lock.\n\nSigned-off-by: Luotao Fu \u003cl.fu@pengutronix.de\u003e\nCc: Guennadi Liakhovetski \u003clg@denx.de\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "5296b56d1b2000b60fb966be161c1f8fb629786b", "tree": "18277748caa9ba43610f76a310d34a3b2155e1a5", "parents": [ "ef560682a97491f62ef538931a4861b57d66c52c" ], "author": { "name": "Guennadi Liakhovetski", "email": "lg@denx.de", "time": "Mon Jan 19 15:36:21 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Jan 19 15:36:21 2009 -0700" }, "message": "i.MX31: Image Processing Unit DMA and IRQ drivers\n\ni.MX3x SoCs contain an Image Processing Unit, consisting of a Control\nModule (CM), Display Interface (DI), Synchronous Display Controller (SDC),\nAsynchronous Display Controller (ADC), Image Converter (IC), Post-Filter\n(PF), Camera Sensor Interface (CSI), and an Image DMA Controller (IDMAC).\nCM contains, among other blocks, an Interrupt Generator (IG) and a Clock\nand Reset Control Unit (CRCU). This driver serves IDMAC and IG. They are\nsupported over dmaengine and irq-chip APIs respectively.\n\nIDMAC is a specialised DMA controller, its DMA channels cannot be used for\ngeneral-purpose operations, even though it might be possible to configure\na memory-to-memory channel for memcpy operation. This driver will not work\nwith generic dmaengine clients, clients, wishing to use it must use\nrespective wrapper structures, they also must specify which channels they\nrequire, as channels are hard-wired to specific IPU functions.\n\nAcked-by: Sascha Hauer \u003cs.hauer@pengutronix.de\u003e\nSigned-off-by: Guennadi Liakhovetski \u003clg@denx.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" } ] }