)]}' { "log": [ { "commit": "7e5b2db77b05746613516599c916a8cc2e321077", "tree": "c3ec333ff7b77bcc8e456a3a3d19bf20f5c651b8", "parents": [ "227d1e4319ffd8729781941d92f4ae4d85beecd9", "c819baf31f5f91fbb06b2c93de2d5b8c8d096f3f" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue May 29 18:27:19 2012 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue May 29 18:27:19 2012 -0700" }, "message": "Merge branch \u0027upstream\u0027 of git://git.linux-mips.org/pub/scm/ralf/upstream-linus\n\nPull MIPS updates from Ralf Baechle:\n \"The whole series has been sitting in -next for quite a while with no\n complaints. The last change to the series was before the weekend the\n removal of an SPI patch which Grant - even though previously acked by\n himself - appeared to raise objections. So I removed it until the\n situation is clarified. Other than that all the patches have the acks\n from their respective maintainers, all MIPS and x86 defconfigs are\n building fine and I\u0027m not aware of any problems introduced by this\n series.\n\n Among the key features for this patch series is a sizable patchset for\n Lantiq which among other things introduces support for Lantiq\u0027s\n flagship product, the FALCON SOC. It also means that the opensource\n developers behind this patchset have overtaken Lantiq\u0027s competing\n inhouse development team that was working behind closed doors.\n\n Less noteworthy the ath79 patchset which adds support for a few more\n chip variants, cleanups and fixes. Finally the usual dose of tweaking\n of generic code.\"\n\nFix up trivial conflicts in arch/mips/lantiq/xway/gpio_{ebu,stp}.c where\nprintk spelling fixes clashed with file move and eventual removal of the\nprintk.\n\n* \u0027upstream\u0027 of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (81 commits)\n MIPS: lantiq: remove orphaned code\n MIPS: Remove all -Wall and almost all -Werror usage from arch/mips.\n MIPS: lantiq: implement support for FALCON soc\n MTD: MIPS: lantiq: verify that the NOR interface is available on falcon soc\n MTD: MIPS: lantiq: implement OF support\n watchdog: MIPS: lantiq: implement OF support and minor fixes\n SERIAL: MIPS: lantiq: implement OF support\n GPIO: MIPS: lantiq: convert gpio-stp-xway to OF\n GPIO: MIPS: lantiq: convert gpio-mm-lantiq to OF and of_mm_gpio\n GPIO: MIPS: lantiq: move gpio-stp and gpio-ebu to the subsystem folder\n MIPS: pci: convert lantiq driver to OF\n MIPS: lantiq: convert dma to platform driver\n MIPS: lantiq: implement support for clkdev api\n MIPS: lantiq: drop ltq_gpio_request() and gpio_to_irq()\n OF: MIPS: lantiq: implement irq_domain support\n OF: MIPS: lantiq: implement OF support\n MIPS: lantiq: drop mips_machine support\n OF: PCI: const usage needed by MIPS\n MIPS: Cavium: Remove smp_reserve_lock.\n MIPS: Move cache setup to setup_arch().\n ...\n" }, { "commit": "3df425f316fb5c5e90236ff22b6e6616b3516af0", "tree": "317262c260132ed136c57a28662f0b8cbd4c4075", "parents": [ "6697c6933048aabe94f0049070f7ec09cd52baa8" ], "author": { "name": "John Crispin", "email": "blogic@openwrt.org", "time": "Thu Apr 12 17:33:07 2012 +0200" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon May 21 14:31:48 2012 +0100" }, "message": "OF: PCI: const usage needed by MIPS\n\nOn MIPS we want to call of_irq_map_pci from inside\n\narch/mips/include/asm/pci.h:extern int pcibios_map_irq(\n\t\t\t\tconst struct pci_dev *dev, u8 slot, u8 pin);\nFor this to work we need to change several functions to const usage.\n\nSigned-off-by: John Crispin \u003cblogic@openwrt.org\u003e\nCc: linux-pci@vger.kernel.org\nCc: devicetree-discuss@lists.ozlabs.org\nCc: linux-mips@linux-mips.org\nAcked-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\nAcked-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\nPatchwork: https://patchwork.linux-mips.org/patch/3710/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "0cbaa57d828aa0a067e06d3c6d795b12ae9fb776", "tree": "871e08f70566b16736ae228eddac018c77ca1144", "parents": [ "99662dd1ce05dbe6394771fcb6ca21bd2aa35987", "284f5f9dbac170b054c1e386ef92cbf654e91bba" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Mon May 07 09:23:27 2012 -0600" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Mon May 07 09:23:27 2012 -0600" }, "message": "Merge branch \u0027topic/stratus\u0027 into next\n" }, { "commit": "977f857ca566a1e68045fcbb7cfc9c4acb077cf0", "tree": "eca7bfd254d2beca6da23cf28e03a50c3d214707", "parents": [ "66f75a5d028beaf67c931435fdc3e7823125730c" ], "author": { "name": "Konrad Rzeszutek Wilk", "email": "konrad.wilk@oracle.com", "time": "Tue Apr 24 13:15:18 2012 -0600" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Mon Apr 30 16:47:26 2012 -0600" }, "message": "PCI: move mutex locking out of pci_dev_reset function\n\nThe intent of git commit 6fbf9e7a90862988c278462d85ce9684605a52b2\n\"PCI: Introduce __pci_reset_function_locked to be used when holding\ndevice_lock.\" was to have a non-locking function that would call\npci_dev_reset function.\n\nBut it fell short of that by just probing and not actually reseting\nthe device. To make that work we need a way to move the lock\naround device_lock to not be in pci_dev_reset (as the caller of\n__pci_reset_function_locked already holds said lock). We do this by\nrenaming pci_dev_reset to __pci_dev_reset and bubbling said mutex out\nof __pci_dev_reset to pci_dev_reset (a wrapper around __pci_dev_reset).\nThe __pci_reset_function_locked can now call __pci_dev_reset without\nhaving to worry about the dead-lock.\n\nSigned-off-by: Konrad Rzeszutek Wilk \u003ckonrad.wilk@oracle.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\n" }, { "commit": "284f5f9dbac170b054c1e386ef92cbf654e91bba", "tree": "74cacc94070d5590378c368fa7378d37319d07be", "parents": [ "66f75a5d028beaf67c931435fdc3e7823125730c" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Mon Apr 30 15:21:02 2012 -0600" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Mon Apr 30 15:21:02 2012 -0600" }, "message": "PCI: work around Stratus ftServer broken PCIe hierarchy\n\nA PCIe downstream port is a P2P bridge. Its secondary interface is\na link that should lead only to device 0 (unless ARI is enabled)[1], so\nwe don\u0027t probe for non-zero device numbers.\n\nSome Stratus ftServer systems have a PCIe downstream port (02:00.0) that\nleads to both an upstream port (03:00.0) and a downstream port (03:01.0),\nand 03:01.0 has important devices below it:\n\n [0000:02]-+-00.0-[03-3c]--+-00.0-[04-09]--...\n \\-01.0-[0a-0d]--+-[USB]\n +-[NIC]\n +-...\n\nPreviously, we didn\u0027t enumerate device 03:01.0, so USB and the network\ndidn\u0027t work. This patch adds a DMI quirk to scan all device numbers,\nnot just 0, below a downstream port.\n\nBased on a patch by Prarit Bhargava.\n\n[1] PCIe spec r3.0, sec 7.3.1\n\nCC: Myron Stowe \u003cmstowe@redhat.com\u003e\nCC: Don Dutile \u003cddutile@redhat.com\u003e\nCC: James Paradis \u003cjames.paradis@stratus.com\u003e\nCC: Matthew Wilcox \u003cmatthew.r.wilcox@intel.com\u003e\nCC: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nCC: Prarit Bhargava \u003cprarit@redhat.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "a6cb9ee7cabe68002c3f2ab07224ea27d2617cf1", "tree": "fb3fc13b4b58e010b1b08c1ae89df810382063dc", "parents": [ "5191d566c023079fa283adc48b71854e9d74ffd5" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Mon Apr 16 23:07:50 2012 +0200" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Apr 16 18:33:35 2012 -0700" }, "message": "PCI: Retry BARs restoration for Type 0 headers only\n\nSome shortcomings introduced into pci_restore_state() by commit\n26f41062f28d (\"PCI: check for pci bar restore completion and retry\")\nhave been fixed by recent commit ebfc5b802fa76 (\"PCI: Fix regression in\npci_restore_state(), v3\"), but that commit treats all PCI devices as\nthose with Type 0 configuration headers.\n\nThat is not entirely correct, because Type 1 and Type 2 headers have\ndifferent layouts. In particular, the area occupied by BARs in Type 0\nconfig headers contains the secondary status register in Type 1 ones and\nit doesn\u0027t make sense to retry the restoration of that register even if\nthe value read back from it after a write is not the same as the written\none (it very well may be different).\n\nFor this reason, make pci_restore_state() only retry the restoration\nof BARs for Type 0 config headers. This effectively makes it behave\nas before commit 26f41062f28d for all header types except for Type 0.\n\nTested-by: Mikko Vinni \u003cmmvinni@yahoo.com\u003e\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "ebfc5b802fa76baeb4371311ff9fc27a2258d90d", "tree": "03da364fee4f182d3e0e2f98e8e20519c0b040b7", "parents": [ "6c23b8e9330c77557fa9658db751029675dd195a" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Sun Apr 15 21:40:40 2012 +0200" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sun Apr 15 13:06:29 2012 -0700" }, "message": "PCI: Fix regression in pci_restore_state(), v3\n\nCommit 26f41062f28d (\"PCI: check for pci bar restore completion and\nretry\") attempted to address problems with PCI BAR restoration on\nsystems where FLR had not been completed before pci_restore_state() was\ncalled, but it did that in an utterly wrong way.\n\nFirst off, instead of retrying the writes for the BAR registers only, it\ndid that for all of the PCI config space of the device, including the\nstatus register (whose value after the write quite obviously need not be\nthe same as the written one). Second, it added arbitrary delay to\npci_restore_state() even for systems where the PCI config space\nrestoration was successful at first attempt. Finally, the mdelay(10) it\nadded to every iteration of the writing loop was way too much of a delay\nfor any reasonable device.\n\nAll of this actually caused resume failures for some devices on Mikko\u0027s\nsystem.\n\nTo fix the regression, make pci_restore_state() only retry the writes\nfor BAR registers and only wait if the first read from the register\ndoesn\u0027t return the written value. Additionaly, make it wait for 1 ms,\ninstead of 10 ms, after every failing attempt to write into config\nspace.\n\nReported-by: Mikko Vinni \u003cmmvinni@yahoo.com\u003e\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "6748dcc269e52925993e0d68447858b41b88b4be", "tree": "51f2e3f04ff1b5bb1dcd96aa82e8ba2ee33b09af", "parents": [ "f6330c3178112a7b7f18e7f51f1cbb89fa1174c7" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Thu Mar 01 00:06:33 2012 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Mar 01 13:36:04 2012 -0800" }, "message": "PCI / PCIe: Introduce command line option to disable ARI\n\nThere are PCIe devices on the market that report ARI support but\nthen fail to initialize correctly when ARI is actually used. This\nleads to situations in which kernels 2.6.34 and newer fail to handle\nsystems where the previous kernels worked without any apparent\nproblems. Unfortunately, it is currently unknown how many such\ndevices are there.\n\nFor this reason, introduce a new kernel command line option,\npci\u003dnoari, allowing users to disable PCIe ARI altogether if they\nsee problems with PCIe device initialization.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "2069ecfbe14ebd71a6f98e8a00724e9adf4fe4ee", "tree": "5a0328d6e545a6488e85face05b0a4d78676bedf", "parents": [ "8474ecd9231434d71a39cd1ba118629e1b036137" ], "author": { "name": "Yinghai Lu", "email": "yinghai@kernel.org", "time": "Wed Feb 15 21:40:31 2012 -0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Feb 24 14:37:26 2012 -0800" }, "message": "PCI: Move \"pci reassigndev resource alignment\" out of quirks.c\n\nThis isn\u0027t really a quirk; calling it directly from pci_add_device makes\nmore sense.\n\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "b55438fdd5173a367659a7e200acea6c9f77b8cb", "tree": "fbcb4ac2e03abcf6933b18fce56361adbcda84af", "parents": [ "0c5be0cb0edfe3b5c4b62eac68aa2aa15ec681af" ], "author": { "name": "Yinghai Lu", "email": "yinghai@kernel.org", "time": "Thu Feb 23 19:23:30 2012 -0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Feb 24 08:47:42 2012 -0800" }, "message": "PCI: prepare pci\u003drealloc for multiple options\n\nLet the user could enable and disable with pci\u003drealloc\u003don or pci\u003drealloc\u003doff\n\nAlso\n1. move variable and functions near the place they are used.\n2. change macro to function\n3. change related functions and variable to static and _init\n4. update parameter description accordingly.\n\nThis will let us add a config option to control default behavior, and\nstill allow the user to turn off automatic reallocation if it fails on\ntheir platform until a permanent solution is found.\n\n-v2: still honor pci\u003drealloc, and treat it as pci\u003drealloc\u003don\n also use enum instead of ...\n-v3: update kernel-paramenters.txt according to Jesse.\n\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "34a4876e3071ddebf3c98c99ba01c14b059a1361", "tree": "e1450472300e41f407c5cfec49b157450d8d85d8", "parents": [ "f796841e49fe086176e27ed0e1f3f7a1123a4a6b" ], "author": { "name": "Yinghai Lu", "email": "yinghai@kernel.org", "time": "Sat Feb 11 00:18:41 2012 -0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Feb 23 12:27:11 2012 -0800" }, "message": "PCI: move pci_find_saved_cap out of linux/pci.h\n\nOnly one user in driver/pci/pci.c, so we don\u0027t need to put it in global\npci.h\n\nReviewed-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "f796841e49fe086176e27ed0e1f3f7a1123a4a6b", "tree": "60d5b1f245ba1a2ca6d81e5e73379cfb26089071", "parents": [ "2dd8ba921d570fcd016f8038c63fa9668892d16b" ], "author": { "name": "Yinghai Lu", "email": "yinghai@kernel.org", "time": "Sat Feb 11 00:18:30 2012 -0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Feb 23 12:08:53 2012 -0800" }, "message": "PCI: fix memleak for pci dev removing during hotplug\n\nunreferenced object 0xffff880276d17700 (size 64):\n comm \"swapper/0\", pid 1, jiffies 4294897182 (age 3976.028s)\n hex dump (first 32 bytes):\n 00 00 00 00 00 00 00 00 18 f9 de 76 02 88 ff ff ...........v....\n 10 00 00 00 0e 00 00 00 0f 28 40 00 00 00 00 00 .........(@.....\n backtrace:\n [\u003cffffffff81c8aede\u003e] kmemleak_alloc+0x26/0x43\n [\u003cffffffff811385f0\u003e] __kmalloc+0x121/0x183\n [\u003cffffffff813cf821\u003e] pci_add_cap_save_buffer+0x35/0x7c\n [\u003cffffffff813d12b7\u003e] pci_allocate_cap_save_buffers+0x1d/0x65\n [\u003cffffffff813cdb52\u003e] pci_device_add+0x92/0xf1\n [\u003cffffffff81c8afe6\u003e] pci_scan_single_device+0x9f/0xa1\n [\u003cffffffff813cdbd2\u003e] pci_scan_slot.part.20+0x21/0x106\n [\u003cffffffff813cdce2\u003e] pci_scan_slot+0x2b/0x35\n [\u003cffffffff81c8dae4\u003e] __pci_scan_child_bus+0x51/0x107\n [\u003cffffffff81c8d75b\u003e] pci_scan_bridge+0x376/0x6ae\n [\u003cffffffff81c8db60\u003e] __pci_scan_child_bus+0xcd/0x107\n [\u003cffffffff81c8dbab\u003e] pci_scan_child_bus+0x11/0x2a\n [\u003cffffffff81cca58c\u003e] pci_acpi_scan_root+0x18b/0x21c\n [\u003cffffffff81c916be\u003e] acpi_pci_root_add+0x1e1/0x42a\n [\u003cffffffff81406210\u003e] acpi_device_probe+0x50/0x190\n [\u003cffffffff814a0227\u003e] really_probe+0x99/0x126\n\nNeed to free saved_buffer for capabilities.\n\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "26f41062f28de65e11d3cf353e52d0be73442be1", "tree": "55ff1002ff04ad6eb8efd8e60f8b60419bc16c64", "parents": [ "2debd9289997fc5d1c0043b41201a8b40d5e11d0" ], "author": { "name": "Kay, Allen M", "email": "allen.m.kay@intel.com", "time": "Thu Jan 26 10:25:53 2012 -0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Feb 14 08:45:02 2012 -0800" }, "message": "PCI: check for pci bar restore completion and retry\n\nOn some OEM systems, pci_restore_state() is called while FLR has not yet\ncompleted. As a result, PCI BAR register restore is not successful. This fix\nreads back the restored value and compares it with saved value and re-tries 10\ntimes before giving up.\n\nSigned-off-by: Jean Guyader \u003cjean.guyader@eu.citrix.com\u003e\nSigned-off-by: Eric Chanudet \u003ceric.chanudet@citrix.com\u003e\nSigned-off-by: Allen Kay \u003callen.m.kay@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "6fbf9e7a90862988c278462d85ce9684605a52b2", "tree": "ccc79061bac41537c37f5edc73bdc5bc59005c8a", "parents": [ "8f0cdddcd3f270901765fc909c3aee37a2091e78" ], "author": { "name": "Konrad Rzeszutek Wilk", "email": "konrad.wilk@oracle.com", "time": "Thu Jan 12 12:06:46 2012 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Feb 14 08:44:48 2012 -0800" }, "message": "PCI: Introduce __pci_reset_function_locked to be used when holding device_lock.\n\nThe use case of this is when a driver wants to call FLR when a device\nis attached to it using the SysFS \"bind\" or \"unbind\" functionality.\n\nThe call chain when a user does \"bind\" looks as so:\n\n echo \"0000:01.07.0\" \u003e /sys/bus/pci/drivers/XXXX/bind\n\nand ends up calling:\n driver_bind:\n device_lock(dev); \u003c\u003d\u003d\u003d TAKES LOCK\n XXXX_probe:\n .. pci_enable_device()\n ...__pci_reset_function(), which calls\n pci_dev_reset(dev, 0):\n if (!0) {\n device_lock(dev) \u003c\u003d\u003d\u003d\u003d DEADLOCK\n\nThe __pci_reset_function_locked function allows the the drivers\n\u0027probe\u0027 function to call the \"pci_reset_function\" while still holding\nthe driver mutex lock.\n\nSigned-off-by: Konrad Rzeszutek Wilk \u003ckonrad.wilk@oracle.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "6e9292c588894bd39eb2d093013f0aee558ddf0e", "tree": "1aaa69c13f260624e84fd7b73a470ddf2201b028", "parents": [ "78d79559f2af1e77034436326aa20f2654074e4c" ], "author": { "name": "Randy Dunlap", "email": "rdunlap@xenotime.net", "time": "Sat Jan 21 11:02:35 2012 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Jan 23 08:44:53 2012 -0800" }, "message": "kernel-doc: fix new warnings in pci\n\nFix new kernel-doc warnings:\n\nWarning(drivers/pci/pci.c:2811): No description found for parameter \u0027dev\u0027\nWarning(drivers/pci/pci.c:2811): Excess function parameter \u0027pdev\u0027 description in \u0027pci_intx_mask_supported\u0027\nWarning(drivers/pci/pci.c:2894): No description found for parameter \u0027dev\u0027\nWarning(drivers/pci/pci.c:2894): Excess function parameter \u0027pdev\u0027 description in \u0027pci_check_and_mask_intx\u0027\nWarning(drivers/pci/pci.c:2908): No description found for parameter \u0027dev\u0027\nWarning(drivers/pci/pci.c:2908): Excess function parameter \u0027pdev\u0027 description in \u0027pci_check_and_unmask_intx\u0027\n\nSigned-off-by: Randy Dunlap \u003crdunlap@xenotime.net\u003e\nCc: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "1900ca132f53c3d51e6e6b94ea8912530223c63a", "tree": "01f7e215f1ba735e54f30c27c3fd91dd747b2c5a", "parents": [ "424eb391596a38ddf422bee1617e4b9dea60126f" ], "author": { "name": "Hao, Xudong", "email": "xudong.hao@intel.com", "time": "Sat Dec 17 21:24:40 2011 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jan 06 12:11:18 2012 -0800" }, "message": "PCI: Enable ATS at the device state restore\n\nDuring S3 or S4 resume or PCI reset, ATS regs aren\u0027t restored correctly.\nThis patch enables ATS at the device state restore if PCI device has ATS\ncapability.\n\nSigned-off-by: Xudong Hao \u003cxudong.hao@intel.com\u003e\nSigned-off-by: Xiantao Zhang \u003cxiantao.zhang@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "85b8582d7ca516030efb84d94fa29a73c1d9a125", "tree": "5a9b8bedd6091a2140026e8edb4eaeb8174597a5", "parents": [ "118faafaf987f521832843d36c6be580983f9a6b" ], "author": { "name": "Vincent Palatin", "email": "vpalatin@chromium.org", "time": "Mon Dec 05 11:51:18 2011 -0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jan 06 12:11:16 2012 -0800" }, "message": "PCI/PM/Runtime: make PCI traces quieter\n\nWhen the runtime PM is activated on PCI, if a device switches state\nfrequently (e.g. an EHCI controller with autosuspending USB devices\nconnected) the PCI configuration traces might be very verbose in the\nkernel log. Let\u0027s guard those traces with DEBUG condition.\n\nAcked-by: \"Rafael J. Wysocki\" \u003crjw@sisk.pl\u003e\nSigned-off-by: Vincent Palatin \u003cvpalatin@chromium.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "f676678f8952d5e2bfc03903dba410c856ae3f3d", "tree": "cdc760f3c0f26635f39b2cb2bc404d375ca1eb05", "parents": [ "b9a276ad262815d88f4dd232d578864949aab3b9" ], "author": { "name": "Myron Stowe", "email": "mstowe@redhat.com", "time": "Fri Oct 28 15:49:20 2011 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jan 06 12:10:47 2012 -0800" }, "message": "PCI: latency timer doesn\u0027t apply to PCIe\n\nThe latency timer is read-only and hardwired to zero for all PCIe\ndevices, both Type 0 and Type 1, so don\u0027t bother trying to update it\nand cluttering the dmesg log with meaningless \"setting latency timer\nto 64\" messages.\n\nSigned-off-by: Myron Stowe \u003cmyron.stowe@redhat.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "96c5590058d7fded14f43af2ab521436cecf3125", "tree": "673577f86b1ee8886c27cc86333fdfdc6cc783ac", "parents": [ "9cdce18d6f0baae53f012fb3f50e66e7ff24c509" ], "author": { "name": "Myron Stowe", "email": "mstowe@redhat.com", "time": "Fri Oct 28 15:48:38 2011 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jan 06 12:10:42 2012 -0800" }, "message": "PCI: Pull PCI \u0027latency timer\u0027 setup up into the core\n\nThe \u0027latency timer\u0027 of PCI devices, both Type 0 and Type 1,\nis setup in architecture-specific code [see: \u0027pcibios_set_master()\u0027].\nThere are two approaches being taken by all the architectures - check\nif the \u0027latency timer\u0027 is currently set between 16 and 255 and if not\nbring it within bounds, or, do nothing (and then there is the\ngratuitously different PA-RISC implementation).\n\nThere is nothing architecture-specific about PCI\u0027s \u0027latency timer\u0027 so\nthis patch pulls its setup functionality up into the PCI core by\ncreating a generic \u0027pcibios_set_master()\u0027 function using the \u0027__weak\u0027\nattribute which can be used by all architectures as a default which,\nif necessary, can then be over-ridden by architecture-specific code.\n\nNo functional change.\n\nSigned-off-by: Myron Stowe \u003cmyron.stowe@redhat.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "a2e27787f893621c5a6b865acf6b7766f8671328", "tree": "b7398b80a56b1e25e4758dfc9ed2af2df27458f3", "parents": [ "fb51ccbf217c1c994607b6519c7d85250928553d" ], "author": { "name": "Jan Kiszka", "email": "jan.kiszka@siemens.com", "time": "Fri Nov 04 09:46:00 2011 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jan 06 12:10:34 2012 -0800" }, "message": "PCI: Introduce INTx check \u0026 mask API\n\nThese new PCI services allow to probe for 2.3-compliant INTx masking\nsupport and then use the feature from PCI interrupt handlers. The\nservices are properly synchronized with concurrent config space access\nvia sysfs or on device reset.\n\nThis enables generic PCI device drivers like uio_pci_generic or KVM\u0027s\ndevice assignment to implement the necessary kernel-side IRQ handling\nwithout any knowledge about device-specific interrupt status and control\nregisters.\n\nAcked-by: Michael S. Tsirkin \u003cmst@redhat.com\u003e\nSigned-off-by: Jan Kiszka \u003cjan.kiszka@siemens.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "fb51ccbf217c1c994607b6519c7d85250928553d", "tree": "d08ba9a0278da0e75b6c6714e9453e46068e27b4", "parents": [ "ae5cd86455381282ece162966183d3f208c6fad7" ], "author": { "name": "Jan Kiszka", "email": "jan.kiszka@siemens.com", "time": "Fri Nov 04 09:45:59 2011 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jan 06 12:10:33 2012 -0800" }, "message": "PCI: Rework config space blocking services\n\npci_block_user_cfg_access was designed for the use case that a single\ncontext, the IPR driver, temporarily delays user space accesses to the\nconfig space via sysfs. This assumption became invalid by the time\npci_dev_reset was added as locking instance. Today, if you run two loops\nin parallel that reset the same device via sysfs, you end up with a\nkernel BUG as pci_block_user_cfg_access detect the broken assumption.\n\nThis reworks the pci_block_user_cfg_access to a sleeping service\npci_cfg_access_lock and an atomic-compatible variant called\npci_cfg_access_trylock. The former not only blocks user space access as\nbefore but also waits if access was already locked. The latter service\njust returns false in this case, allowing the caller to resolve the\nconflict instead of raising a BUG.\n\nAdaptions of the ipr driver were originally written by Brian King.\n\nAcked-by: Brian King \u003cbrking@linux.vnet.ibm.com\u003e\nAcked-by: Michael S. Tsirkin \u003cmst@redhat.com\u003e\nSigned-off-by: Jan Kiszka \u003cjan.kiszka@siemens.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "497f16f21a04060098c0da6ed522fbcafb90c0db", "tree": "8827d2d1d515dc1ea34d63965bf93e9ee21ae9bc", "parents": [ "ab347d94d6515ea9a5be04faccd9b14a319b0a7a" ], "author": { "name": "Yinghai Lu", "email": "yinghai@kernel.org", "time": "Sat Dec 17 18:33:37 2011 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sun Dec 18 14:10:16 2011 -0800" }, "message": "pci: Fix hotplug of Express Module with pci bridges\n\nI noticed that hotplug of one setup does not work with recent change in\npci tree.\n\nAfter checking the bridge conf setup, I noticed that the bridges get\nassigned but do not get enabled.\n\nThe reason is the following commit, while simply ignores bridge\nresources when enabling a pci device:\n\n| commit bbef98ab0f019f1b0c25c1acdf1683c68933d41b\n| Author: Ram Pai \u003clinuxram@us.ibm.com\u003e\n| Date: Sun Nov 6 10:33:10 2011 +0800\n|\n| PCI: defer enablement of SRIOV BARS\n|...\n| NOTE: Note, there is subtle change in the pci_enable_device() API. Any\n| driver that depends on SRIOV BARS to be enabled in pci_enable_device()\n| can fail.\n\nPut back bridge resource and ROM resource checking to fix the problem.\n\nThat should fix regression like BIOS does not assign correct resource to\nbridge.\n\nDiscussion can be found at:\n\thttp://www.spinics.net/lists/linux-pci/msg12874.html\n\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "b51306c63449d7f06ffa689036ba49eb46e898b5", "tree": "6f3ad6817681c1ee2a7d7abc86d85695564924ea", "parents": [ "619a5182d1f38a3d629ee48e04fa182ef9170052" ], "author": { "name": "Ajaykumar Hotchandani", "email": "ajaykumar.hotchandani@oracle.com", "time": "Mon Dec 12 13:57:36 2011 +0530" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Dec 14 08:26:42 2011 -0800" }, "message": "PCI: Set device power state to PCI_D0 for device without native PM support\n\nDuring test of one IB card with guest VM, found that, msi is not\ninitialized properly.\n\nIt turns out __write_msi_msg will do nothing if device current_state is\nnot PCI_D0. And, that pci device does not have pm_cap in guest VM.\n\nThere is an error in setting of power state to PCI_D0 in\npci_enable_device(), but error is not returned for this. Following is\ncode flow:\n\npci_enable_device() --\u003e __pci_enable_device_flags() --\u003e\ndo_pci_enable_device() --\u003e pci_set_power_state() --\u003e\n__pci_start_power_transition()\n\nWe have following condition inside __pci_start_power_transition():\n if (platform_pci_power_manageable(dev)) {\n error \u003d platform_pci_set_power_state(dev, state);\n if (!error)\n pci_update_current_state(dev, state);\n } else {\n error \u003d -ENODEV;\n /* Fall back to PCI_D0 if native PM is not supported */\n if (!dev-\u003epm_cap)\n dev-\u003ecurrent_state \u003d PCI_D0;\n }\n\nHere, from platform_pci_set_power_state(), acpi_pci_set_power_state() is\ngetting called and that is failing with ENODEV because of following\ncondition:\n\n if (!handle || ACPI_SUCCESS(acpi_get_handle(handle, \"_EJ0\",\u0026tmp)))\n return -ENODEV;\n\nBecause of that, pci_update_current_state() is not getting called.\n\nWith this patch, if device power state can not be set via\nplatform_pci_set_power_state and that device does not have native pm\nsupport, then PCI device power state will be set to PCI_D0.\n\n-v2: This also reverts 47e9037ac16637cd7f12b8790ea7ce6680e42168, as it\u0027s\n not needed after this change.\n\nAcked-by: \"Rafael J. Wysocki\" \u003crjw@sisk.pl\u003e\nSigned-off-by: Ajaykumar Hotchandani\u003cajaykumar.hotchandani@oracle.com\u003e\nSigned-off-by: Yinghai Lu\u003cyinghai.lu@oracle.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "bbef98ab0f019f1b0c25c1acdf1683c68933d41b", "tree": "07123873f64c4a61fef7c98a4744d4cad852c345", "parents": [ "8e8da023f5af71662867729db5547dc54786093c" ], "author": { "name": "Ram Pai", "email": "linuxram@us.ibm.com", "time": "Sun Nov 06 10:33:10 2011 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Dec 05 10:30:22 2011 -0800" }, "message": "PCI: defer enablement of SRIOV BARS\n\nAll the PCI BARs of a device are enabled when the device is enabled\nusing pci_enable_device(). This unnecessarily enables SRIOV BARs of the\ndevice.\n\nOn some platforms, which do not support SRIOV as yet, the\npci_enable_device() fails to enable the device if its SRIOV BARs are not\nallocated resources correctly.\n\nThe following patch fixes the above problem. The SRIOV BARs are now\nenabled when IOV capability of the device is enabled in sriov_enable().\n\nNOTE: Note, there is subtle change in the pci_enable_device() API. Any\ndriver that depends on SRIOV BARS to be enabled in pci_enable_device()\ncan fail.\n\nThe patch has been touch tested on power and x86 platform.\n\nTested-by: Michael Wang \u003cwangyun@linux.vnet.ibm.com\u003e\nSigned-off-by: Ram Pai \u003clinuxram@us.ibm.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "a1c473aa11e61bc871be16279c9bf976acf22504", "tree": "13f1c4565817bab8660e2e38f8fedc5344519788", "parents": [ "62f392ea5b5f87b641e16e61a4cedda21ef7341f" ], "author": { "name": "Benjamin Herrenschmidt", "email": "benh@kernel.crashing.org", "time": "Fri Oct 14 14:56:15 2011 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Oct 27 12:45:44 2011 -0700" }, "message": "pci: Clamp pcie_set_readrq() when using \"performance\" settings\n\nWhen configuring the PCIe settings for \"performance\", we allow parents\nto have a larger Max Payload Size than children and rely on children\nMax Read Request Size to not be larger than their own MPS to avoid\nhaving the host bridge generate responses they can\u0027t cope with.\n\nHowever, various drivers in Linux call pci_set_readrq() with arbitrary\nvalues, assuming this to be a simple performance tweak. This breaks\nunder our \"performance\" configuration.\n\nFix that by making sure the value programmed by pcie_set_readrq() is\nnever larger than the configured MPS for that device.\n\nSigned-off-by: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nSigned-off-by: Jon Mason \u003cmason@myri.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "379021d5c0899fcf9410cae4ca7a59a5a94ca769", "tree": "9c91ffb80fcb143b94c20922cb27d60d2c7e6654", "parents": [ "3e309cdf07c930f29a4e0f233e47d399bea34c68" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Mon Oct 03 23:16:33 2011 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Oct 14 09:05:31 2011 -0700" }, "message": "PCI / PM: Extend PME polling to all PCI devices\n\nThe land of PCI power management is a land of sorrow and ugliness,\nespecially in the area of signaling events by devices. There are\ndevices that set their PME Status bits, but don\u0027t really bother\nto send a PME message or assert PME#. There are hardware vendors\nwho don\u0027t connect PME# lines to the system core logic (they know\nwho they are). There are PCI Express Root Ports that don\u0027t bother\nto trigger interrupts when they receive PME messages from the devices\nbelow. There are ACPI BIOSes that forget to provide _PRW methods for\ndevices capable of signaling wakeup. Finally, there are BIOSes that\ndo provide _PRW methods for such devices, but then don\u0027t bother to\ncall Notify() for those devices from the corresponding _Lxx/_Exx\nGPE-handling methods. In all of these cases the kernel doesn\u0027t have\na chance to receive a proper notification that it should wake up a\ndevice, so devices stay in low-power states forever. Worse yet, in\nsome cases they continuously send PME Messages that are silently\nignored, because the kernel simply doesn\u0027t know that it should clear\nthe device\u0027s PME Status bit.\n\nThis problem was first observed for \"parallel\" (non-Express) PCI\ndevices on add-on cards and Matthew Garrett addressed it by adding\ncode that polls PME Status bits of such devices, if they are enabled\nto signal PME, to the kernel. Recently, however, it has turned out\nthat PCI Express devices are also affected by this issue and that it\nis not limited to add-on devices, so it seems necessary to extend\nthe PME polling to all PCI devices, including PCI Express and planar\nones. Still, it would be wasteful to poll the PME Status bits of\ndevices that are known to receive proper PME notifications, so make\nthe kernel (1) poll the PME Status bits of all PCI and PCIe devices\nenabled to signal PME and (2) disable the PME Status polling for\ndevices for which correct PME notifications are received.\n\nTested-by: Sarah Sharp \u003csarah.a.sharp@linux.intel.com\u003e\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "5f39e6705faade2e89d119958a8c51b9b6e2c53c", "tree": "e9d69f2f465daeca7cdc452a3b19d702f15e98b0", "parents": [ "05faadcf59507e8eea57ffbeea9cbb14c9a2ab3d" ], "author": { "name": "Jon Mason", "email": "mason@myri.com", "time": "Mon Oct 03 09:50:20 2011 -0500" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue Oct 04 09:52:28 2011 -0700" }, "message": "PCI: Disable MPS configuration by default\n\nAdd the ability to disable PCI-E MPS turning and using the BIOS\nconfigured MPS defaults. Due to the number of issues recently\ndiscovered on some x86 chipsets, make this the default behavior.\n\nAlso, add the option for peer to peer DMA MPS configuration. Peer to\npeer DMA is outside the scope of this patch, but MPS configuration could\nprevent it from working by having the MPS on one root port different\nthan the MPS on another. To work around this, simply make the system\nwide MPS the smallest possible value (128B).\n\nSigned-off-by: Jon Mason \u003cmason@myri.com\u003e\nAcked-by: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "ed2888e906b56769b4ffabb9c577190438aa68b8", "tree": "81d55511aaa0b2b4074b9432fee3e23beb98b503", "parents": [ "5307f6d5fb12fd01f9f321bc4a8fd77e74858647" ], "author": { "name": "Jon Mason", "email": "mason@myri.com", "time": "Thu Sep 08 16:41:18 2011 -0500" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Sep 09 19:49:58 2011 -0700" }, "message": "PCI: Remove MRRS modification from MPS setting code\n\nModifying the Maximum Read Request Size to 0 (value of 128Bytes) has\nmassive negative ramifications on some devices. Without knowing which\ndevices have this issue, do not modify from the default value when\nwalking the PCI-E bus in pcie_bus_safe mode. Also, make pcie_bus_safe\nthe default procedure.\n\nTested-by: Sven Schnelle \u003csvens@stackframe.org\u003e\nTested-by: Simon Kirby \u003csim@hostway.ca\u003e\nTested-by: Stephen M. Cameron \u003cscameron@beardog.cce.hp.com\u003e\nReported-and-tested-by: Eric Dumazet \u003ceric.dumazet@gmail.com\u003e\nReported-and-tested-by: Niels Ole Salscheider \u003cniels_ole@salscheider-online.de\u003e\nReferences: https://bugzilla.kernel.org/show_bug.cgi?id\u003d42162\nSigned-off-by: Jon Mason \u003cmason@myri.com\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "47c08f3107270e5a439bc0106a308f7c48c9621d", "tree": "d003f7337671bd240da4a463cc6fe1f6fb163e55", "parents": [ "bed8cad9593974a46de5c8aa3d2ee7c49c17182f" ], "author": { "name": "Randy Dunlap", "email": "rdunlap@xenotime.net", "time": "Sat Aug 20 11:49:43 2011 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sat Aug 20 18:02:32 2011 -0700" }, "message": "pci: fix new kernel-doc warning in pci.c\n\nFix new kernel-doc warning in pci.c:\n\n Warning(drivers/pci/pci.c:3259): No description found for parameter \u0027mps\u0027\n Warning(drivers/pci/pci.c:3259): Excess function parameter \u0027rq\u0027 description in \u0027pcie_set_mps\u0027\n\nSigned-off-by: Randy Dunlap \u003crdunlap@xenotime.net\u003e\nCc: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "b03e7495a862b028294f59fc87286d6d78ee7fa1", "tree": "836fbfc2b0e34f034cb273c4d065baba3a65178c", "parents": [ "5f66d2b58ca879e70740c82422354144845d6dd3" ], "author": { "name": "Jon Mason", "email": "mason@myri.com", "time": "Wed Jul 20 15:20:54 2011 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Aug 01 11:49:16 2011 -0700" }, "message": "PCI: Set PCI-E Max Payload Size on fabric\n\nOn a given PCI-E fabric, each device, bridge, and root port can have a\ndifferent PCI-E maximum payload size. There is a sizable performance\nboost for having the largest possible maximum payload size on each PCI-E\ndevice. However, if improperly configured, fatal bus errors can occur.\nThus, it is important to ensure that PCI-E payloads sends by a device\nare never larger than the MPS setting of all devices on the way to the\ndestination.\n\nThis can be achieved two ways:\n\n- A conservative approach is to use the smallest common denominator of\n the entire tree below a root complex for every device on that fabric.\n\nThis means for example that having a 128 bytes MPS USB controller on one\nleg of a switch will dramatically reduce performances of a video card or\n10GE adapter on another leg of that same switch.\n\nIt also means that any hierarchy supporting hotplug slots (including\nexpresscard or thunderbolt I suppose, dbl check that) will have to be\nentirely clamped to 128 bytes since we cannot predict what will be\nplugged into those slots, and we cannot change the MPS on a \"live\"\nsystem.\n\n- A more optimal way is possible, if it falls within a couple of\n constraints:\n* The top-level host bridge will never generate packets larger than the\n smallest TLP (or if it can be controlled independently from its MPS at\n least)\n* The device will never generate packets larger than MPS (which can be\n configured via MRRS)\n* No support of direct PCI-E \u003c-\u003e PCI-E transfers between devices without\n some additional code to specifically deal with that case\n\nThen we can use an approach that basically ignores downstream requests\nand focuses exclusively on upstream requests. In that case, all we need\nto care about is that a device MPS is no larger than its parent MPS,\nwhich allows us to keep all switches/bridges to the max MPS supported by\ntheir parent and eventually the PHB.\n\nIn this case, your USB controller would no longer \"starve\" your 10GE\nEthernet and your hotplug slots won\u0027t affect your global MPS.\nAdditionally, the hotplugged devices themselves can be configured to a\nlarger MPS up to the value configured in the hotplug bridge.\n\nTo choose between the two available options, two PCI kernel boot args\nhave been added to the PCI calls. \"pcie_bus_safe\" will provide the\nformer behavior, while \"pcie_bus_perf\" will perform the latter behavior.\nBy default, the latter behavior is used.\n\nNOTE: due to the location of the enablement, each arch will need to add\ncalls to this function. This patch only enables x86.\n\nThis patch includes a number of changes recommended by Benjamin\nHerrenschmidt.\n\nTested-by: Jordan_Hargrave@dell.com\nSigned-off-by: Jon Mason \u003cmason@myri.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "c9b378c7cbf623649e4ca64f955f2afd12ef01b2", "tree": "2fde509dd86d2548c5bdb8d00413bda8b513897f", "parents": [ "0cab0841dc1400f633a7e1ac1e448518692f927a" ], "author": { "name": "Jon Mason", "email": "jdmason@kudzu.us", "time": "Tue Jun 28 18:26:25 2011 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jul 22 09:06:51 2011 -0700" }, "message": "PCI: correct pcie_set_readrq write size\n\nWhen setting the PCI-E MRRS, pcie_set_readrq queries the current\nsettings via a pci_read_config_word call but writes the modified result\nvia a pci_write_config_dword. This results in writing 16 more bits than\nwere queried.\n\nAlso, the function description comment is slightly incorrect.\n\nSigned-off-by: Jon Mason \u003cjdmason@kudzu.us\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "864d296cf948aef0fa32b81407541572583f7572", "tree": "67d2cee99f6a5f591bcd6a19bb5333f6c4234598", "parents": [ "a8c7ef3187a266d201af887fd48afbef3598825a" ], "author": { "name": "Chris Wright", "email": "chrisw@sous-sol.org", "time": "Wed Jul 13 10:14:33 2011 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jul 22 08:41:51 2011 -0700" }, "message": "PCI: ARI is a PCIe v2 feature\n\nThe function pci_enable_ari() may mistakenly set the downstream port\nof a v1 PCIe switch in ARI Forwarding mode. This is a PCIe v2 feature,\nand with an SR-IOV device on that switch port believing the switch above\nis ARI capable it may attempt to use functions 8-255, translating into\ninvalid (non-zero) device numbers for that bus. This has been seen\nto cause Completion Timeouts and general misbehaviour including hangs\nand panics.\n\nCc: stable@kernel.org\nAcked-by: Don Dutile \u003cddutile@redhat.com\u003e\nTested-by: Don Dutile \u003cddutile@redhat.com\u003e\nSigned-off-by: Chris Wright \u003cchrisw@sous-sol.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "f483d3923dc3a6394c483e28ccb3fe700bdf399e", "tree": "ef487babd0ef104e1fa8323c23050d66096c0f3a", "parents": [ "a2fa83faf47b514ab947cea916d3691b66525073" ], "author": { "name": "Ram Pai", "email": "linuxram@us.ibm.com", "time": "Thu Jul 07 11:19:10 2011 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jul 08 15:49:20 2011 -0700" }, "message": "PCI: conditional resource-reallocation through kernel parameter pci\u003drealloc\n \nMultiple attempts to dynamically reallocate pci resources have\nunfortunately lead to regressions. Though we continue to fix the\nregressions and fine tune the dynamic-reallocation behavior, we have not\nreached a acceptable state yet.\n \nThis patch provides a interim solution. It disables dynamic reallocation\nby default, but adds the ability to enable it through pci\u003drealloc kernel\ncommand line parameter.\n \nTested-by: Oliver Hartkopp \u003csocketcan@hartkopp.net\u003e\nSigned-off-by: Ram Pai \u003clinuxram@us.ibm.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "12f1ba5a7dac4caf8b4e6ccd6453f0a095e74c7c", "tree": "8af7cdfba131994d24ecf0bc7bc701ce11835ba2", "parents": [ "143e859d05d0abf4c3b67c64c93695d59fd41342", "6e33a852a37dee02979ec9d82bea26c07cee5bce" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Jun 24 08:36:16 2011 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Jun 24 08:36:16 2011 -0700" }, "message": "Merge branch \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6\n\n* \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6:\n x86/PCI/ACPI: fix type mismatch\n PCI: fix new kernel-doc warning\n PCI: Fix warning in drivers/pci/probe.c on sparc64\n" }, { "commit": "7ad35cf288fd63a19bf50e490440a992de808b2b", "tree": "a240c3487926ebe62d8c10e0d1ae75db38f025e6", "parents": [ "83533c132a55aac735028f6fb9b956e8c078db1f" ], "author": { "name": "Dave Airlie", "email": "airlied@redhat.com", "time": "Wed May 25 14:00:49 2011 +1000" }, "committer": { "name": "Dave Airlie", "email": "airlied@redhat.com", "time": "Tue Jun 14 09:50:12 2011 +1000" }, "message": "x86/uv/x2apic: update for change in pci bridge handling.\n\nWhen I added 3448a19da479b6bd1e28e2a2be9fa16c6a6feb39\nI forgot about the special uv handling code for this, so this\npatch fixes it up.\n\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nAcked-by: Ingo Molnar\nSigned-off-by: Dave Airlie \u003cairlied@redhat.com\u003e\n" }, { "commit": "3f37d6229ca309f96b163b943ff982f4697630cd", "tree": "4099ff1c8b424c6e5bb51c419b1ea0a6d427b979", "parents": [ "5aceca9d3cbdacbd017712513387d930f9f944d9" ], "author": { "name": "Randy Dunlap", "email": "randy.dunlap@oracle.com", "time": "Wed May 25 19:21:25 2011 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Jun 01 11:43:29 2011 -0700" }, "message": "PCI: fix new kernel-doc warning\n\nFix pci.c kernel-doc warnings:\n\nWarning(drivers/pci/pci.c:3292): No description found for parameter \u0027flags\u0027\nWarning(drivers/pci/pci.c:3292): Excess function parameter \u0027change_bridge_flags\u0027 description in \u0027pci_set_vga_state\u0027\n\nSigned-off-by: Randy Dunlap \u003crandy.dunlap@oracle.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "98b98d316349e9a028e632629fe813d07fa5afdd", "tree": "caaf6a662a86c5e2a418f0929ca05f0748803ac5", "parents": [ "0d66cba1ac3ad38614077443d604d6a09cec99de", "931474c4c30633400ff0dff8fb452ae20e01d067" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue May 24 12:06:40 2011 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue May 24 12:06:40 2011 -0700" }, "message": "Merge branch \u0027drm-core-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6\n\n* \u0027drm-core-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (169 commits)\n drivers/gpu/drm/radeon/atom.c: fix warning\n drm/radeon/kms: bump kms version number\n drm/radeon/kms: properly set num banks for fusion asics\n drm/radeon/kms/atom: move dig phy init out of modesetting\n drm/radeon/kms/cayman: fix typo in register mask\n drm/radeon/kms: fix typo in spread spectrum code\n drm/radeon/kms: fix tile_config value reported to userspace on cayman.\n drm/radeon/kms: fix incorrect comparison in cayman setup code.\n drm/radeon/kms: add wait idle ioctl for eg-\u003ecayman\n drm/radeon/cayman: setup hdp to invalidate and flush when asked\n drm/radeon/evergreen/btc/fusion: setup hdp to invalidate and flush when asked\n agp/uninorth: Fix lockups with radeon KMS and \u003e1x.\n drm/radeon/kms: the SS_Id field in the LCD table if for LVDS only\n drm/radeon/kms: properly set the CLK_REF bit for DCE3 devices\n drm/radeon/kms: fixup eDP connector handling\n drm/radeon/kms: bail early for eDP in hotplug callback\n drm/radeon/kms: simplify hotplug handler logic\n drm/radeon/kms: rewrite DP handling\n drm/radeon/kms/atom: add support for setting DP panel mode\n drm/radeon/kms: atombios.h updates for DP panel mode\n ...\n" }, { "commit": "ffbdd3f7931fb7cb7e36d00d16303ec433be5145", "tree": "503e1ad819bb3f1d682de24de5271935849ba5ff", "parents": [ "24a4742f0be6226eb0106fbb17caf4d711d1ad43" ], "author": { "name": "Alex Williamson", "email": "alex.williamson@redhat.com", "time": "Tue May 10 10:02:27 2011 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Sat May 21 12:17:09 2011 -0700" }, "message": "PCI: Add interfaces to store and load the device saved state\n\nFor KVM device assignment, we\u0027d like to save off the state of a device\nprior to passing it to the guest and restore it later. We also want\nto allow pci_reset_funciton() to be called while the device is owned\nby the guest. This however overwrites and invalidates the struct pci_dev\nbuffers, so we can\u0027t just manually call save and restore. Add generic\ninterfaces for the saved state to be stored and reloaded back into\nstruct pci_dev at a later time.\n\nSigned-off-by: Alex Williamson \u003calex.williamson@redhat.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "24a4742f0be6226eb0106fbb17caf4d711d1ad43", "tree": "43c61634fec10605571321daa38b81de4006eab6", "parents": [ "9f728f53dd70396f3183d2f0861022259471824b" ], "author": { "name": "Alex Williamson", "email": "alex.williamson@redhat.com", "time": "Tue May 10 10:02:11 2011 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Sat May 21 12:17:08 2011 -0700" }, "message": "PCI: Track the size of each saved capability data area\n\nThis will allow us to store and load it later.\n\nSigned-off-by: Alex Williamson \u003calex.williamson@redhat.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "51c2e0a7e5bc7ed1384cc68cfb95e702571500c9", "tree": "839dc5d6eb233b009c8802cb8cafde68f5a2ce6e", "parents": [ "48a92a8179b3e677fac07db7bd109e68f020468c" ], "author": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jan 14 08:53:04 2011 -0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed May 11 15:18:53 2011 -0700" }, "message": "PCI: add latency tolerance reporting enable/disable support\n\nLatency tolerance reporting allows devices to send messages to the root\ncomplex indicating their latency tolerance for snooped \u0026 unsnooped\nmemory transactions. Add support for enabling \u0026 disabling this\nfeature, along with a routine to set the max latencies a device should\nsend upstream.\n\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "48a92a8179b3e677fac07db7bd109e68f020468c", "tree": "a0d43c7fc33fd5c899ce81103097117c27dd3e60", "parents": [ "b48d4425b602f5f4978299474743dbea130d940d" ], "author": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Jan 10 12:46:36 2011 -0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed May 11 15:18:48 2011 -0700" }, "message": "PCI: add OBFF enable/disable support\n\nOBFF (optimized buffer flush/fill), where supported, can help improve\nenergy efficiency by giving devices information about when interrupts\nand other activity will have a reduced power impact. It requires\nsupport from both the device and system (i.e. not only does the device\nneed to respond to OBFF messages, but the platform must be capable of\ngenerating and routing them to the end point).\n\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "b48d4425b602f5f4978299474743dbea130d940d", "tree": "7da23c264cab62bce753e60c4e8d5fbbb0aab0e7", "parents": [ "69643e4829c5cd13bafe44a6b9f3eb2086e0f618" ], "author": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Oct 19 13:07:57 2010 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed May 11 15:18:40 2011 -0700" }, "message": "PCI: add ID-based ordering enable/disable support\n\nAdd support to allow drivers to enable/disable ID-based ordering. Where\nsupported, ID-based ordering can significantly improve the latency of\nindividual requests by preventing them from queueing up behind unrelated\ntraffic.\n\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "83d74e036b94ffbf871667eede5ef02993709452", "tree": "69ef4a3bc6ed289389ab6221df46459e088e4d11", "parents": [ "3504e47ffca5ed3f9e2cc7d37b428fbf1e00ad1b" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Sat Mar 05 21:48:44 2011 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue May 10 15:43:29 2011 -0700" }, "message": "PCI/PM: Add kerneldoc description of pci_pm_reset()\n\nThe pci_pm_reset() function is not a very nice interface due to its\nlimitations and conditional behavior (e.g. it doesn\u0027t affect devices\nin low-power states), but it cannot be simply dropped, because\nexisting device drivers may depend on it. However, its behavior and\nlimitations should be well documented, so add an appropriate\nkerneldoc comment to it.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "3448a19da479b6bd1e28e2a2be9fa16c6a6feb39", "tree": "b69bfa9e71e46c8c7470cbdf49de8530227d6687", "parents": [ "8116188fdef5946bcbb2d73e41d7412a57ffb034" ], "author": { "name": "Dave Airlie", "email": "airlied@redhat.com", "time": "Tue Jun 01 15:32:24 2010 +1000" }, "committer": { "name": "Dave Airlie", "email": "airlied@redhat.com", "time": "Wed May 04 13:38:46 2011 +1000" }, "message": "vgaarb: use bridges to control VGA routing where possible.\n\nSo in a lot of modern systems, a GPU will always be below a parent bridge that won\u0027t share with any other GPUs. This means VGA arbitration on those GPUs can be controlled by using the bridge routing instead of io/mem decodes.\n\nThe problem is locating which GPUs share which upstream bridges. This patch attempts to identify all the GPUs which can be controlled via bridges, and ones that can\u0027t. This patch endeavours to work out the bridge sharing semantics.\n\nWhen disabling GPUs via a bridge, it doesn\u0027t do irq callbacks or touch the io/mem decodes for the gpu.\n\nSigned-off-by: Dave Airlie \u003cairlied@redhat.com\u003e\n" }, { "commit": "1a680b7c325882188865f05b9a88d32f75f26495", "tree": "eb3844655f9ff01630157e4b2c039759970b1a94", "parents": [ "8b8bae901ce23addbdcdb54fa1696fb2d049feb5" ], "author": { "name": "Naga Chumbalkar", "email": "nagananda.chumbalkar@hp.com", "time": "Mon Mar 21 03:29:08 2011 +0000" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Mar 21 09:40:43 2011 -0700" }, "message": "PCI: PCIe links may not get configured for ASPM under POWERSAVE mode\n\nv3 -\u003e v2: Moved ASPM enabling logic to pci_set_power_state()\nv2 -\u003e v1: Preserved the logic in pci_raw_set_power_state()\n\t: Added ASPM enabling logic after scanning Root Bridge\n\t: http://marc.info/?l\u003dlinux-pci\u0026m\u003d130046996216391\u0026w\u003d2\nv1\t: http://marc.info/?l\u003dlinux-pci\u0026m\u003d130013164703283\u0026w\u003d2\n\nThe assumption made in commit 41cd766b065970ff6f6c89dd1cf55fa706c84a3d\n(PCI: Don\u0027t enable aspm before drivers have had a chance to veto it) that\npci_enable_device() will result in re-configuring ASPM when aspm_policy is\nPOWERSAVE is no longer valid. This is due to commit\n97c145f7c87453cec90e91238fba5fe2c1561b32 (PCI: read current power state\nat enable time) which resets dev-\u003ecurrent_state to D0. Due to this the\ncall to pcie_aspm_pm_state_change() is never made. Note the equality check\n(below) that returns early:\n./drivers/pci/pci.c: pci_raw_set_pci_power_state()\n546 /* Check if we\u0027re already there */\n547 if (dev-\u003ecurrent_state \u003d\u003d state)\n548 return 0;\n\nTherefore OSPM never configures the PCIe links for ASPM to turn them \"on\".\n\nFix it by configuring ASPM from the pci_enable_device() code path. This\nalso allows a driver such as the e1000e networking driver a chance to\ndisable ASPM (L0s, L1), if need be, prior to enabling the device. A\ndriver may perform this action if the device is known to mis-behave\nwrt ASPM.\n\nSigned-off-by: Naga Chumbalkar \u003cnagananda.chumbalkar@hp.com\u003e\nAcked-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nCc: Matthew Garrett \u003cmjg59@srcf.ucam.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "0f953bf6b4efa0daddb7c418130a9bd3ee97f7ed", "tree": "4a24901b0ff701e80787e39d87603bdd4b762876", "parents": [ "b6e335aeeb114dccb07eaa09e8b62ff9510cf745" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Wed Dec 29 13:22:08 2010 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jan 14 08:55:43 2011 -0800" }, "message": "PCI/PM: Report wakeup events before resuming devices\n\nMake wakeup events be reported by the PCI subsystem before attempting to\nresume devices or queuing up runtime resume requests for them, because\nwakeup events should be reported as soon as they have been detected.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "b6e335aeeb114dccb07eaa09e8b62ff9510cf745", "tree": "f4292a579e594b6c0312e9c34467649cb978aea5", "parents": [ "ff29530e651a3449aea6b0ef4c7048db9e22ef27" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Wed Dec 29 13:21:23 2010 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jan 14 08:55:43 2011 -0800" }, "message": "PCI/PM: Use pm_wakeup_event() directly for reporting wakeup events\n\nAfter recent changes related to wakeup events pm_wakeup_event()\nautomatically checks if the given device is configured to signal wakeup,\nso pci_wakeup_event() may be a static inline function calling\npm_wakeup_event() directly.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "1d3c16a818e992c199844954d95c17fd7ce6cbba", "tree": "6f54b4153b8f7e54bdb5a8abc3ceffa7b4eec0e2", "parents": [ "2f671e2dbff6eb5ef4e2600adbec550c13b8fe72" ], "author": { "name": "Jon Mason", "email": "jon.mason@exar.com", "time": "Tue Nov 30 17:43:26 2010 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Dec 23 12:53:09 2010 -0800" }, "message": "PCI: make pci_restore_state return void\n\npci_restore_state only ever returns 0, thus there is no benefit in\nhaving it return any value. Also, a large majority of the callers do\nnot check the return code of pci_restore_state. Make the\npci_restore_state a void return and avoid the overhead.\n\nAcked-by: Mauro Carvalho Chehab \u003cmchehab@redhat.com\u003e\nSigned-off-by: Jon Mason \u003cjon.mason@exar.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "97c145f7c87453cec90e91238fba5fe2c1561b32", "tree": "e69b486547e713b6a9358ad780dcdf7b697a7912", "parents": [ "3b519e4ea618b6943a82931630872907f9ac2c2b" ], "author": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Nov 05 15:16:36 2010 -0400" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Nov 11 09:38:14 2010 -0800" }, "message": "PCI: read current power state at enable time\n\nWhen we enable a PCI device, we avoid doing a lot of the initial setup\nwork if the device\u0027s enable count is non-zero. If we don\u0027t fetch the\npower state though, we may later fail to set up MSI due to the unknown\nstatus. So pick it up before we short circuit the rest due to a\npre-existing enable or mismatched enable/disable pair (as happens with\nVGA devices, which are special in a special way).\n\nTested-by: Jesse Brandeburg \u003cjesse.brandeburg@gmail.com\u003e\nReported-by: Dave Airlie \u003cairlied@linux.ie\u003e\nTested-by: Dave Airlie \u003cairlied@linux.ie\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "df17e62e5bff60aeefd0e81165c62f9e46f33217", "tree": "12f612592ae274330455c2206ce2d17c10082ab2", "parents": [ "bf4d29086972ceaeaf72544d8f64933c2cfdc992" ], "author": { "name": "Matthew Garrett", "email": "mjg@redhat.com", "time": "Mon Oct 04 14:22:29 2010 -0400" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Sun Oct 17 20:03:06 2010 -0700" }, "message": "PCI: Add support for polling PME state on suspended legacy PCI devices\n\nNot all hardware vendors hook up the PME line for legacy PCI devices,\nmeaning that wakeup events get lost. The only way around this is to poll\nthe devices to see if their state has changed, so add support for doing\nthat on legacy PCI devices that aren\u0027t part of the core chipset.\n\nAcked-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Matthew Garrett \u003cmjg@redhat.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "93e75faba3982767d425323aec5726282d3ad7a2", "tree": "afe0d48677a09c71357293f612fb495983193c37", "parents": [ "8fd01d6cfbf75465d84a4e533ed70c5f57b3ff51" ], "author": { "name": "Julia Lawall", "email": "julia@diku.dk", "time": "Thu Aug 05 22:23:16 2010 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Oct 15 13:09:46 2010 -0700" }, "message": "PCI: Adjust confusing if indentation in pcie_get_readrq\n\nIndent the branch of an if.\n\nThe semantic match that finds this problem is as follows:\n(http://coccinelle.lip6.fr/)\n\n// \u003csmpl\u003e\n@r disable braces4@\nposition p1,p2;\nstatement S1,S2;\n@@\n\n(\nif (...) { ... }\n|\nif (...) S1@p1 S2@p2\n)\n\n@script:python@\np1 \u003c\u003c r.p1;\np2 \u003c\u003c r.p2;\n@@\n\nif (p1[0].column \u003d\u003d p2[0].column):\n cocci.print_main(\"branch\",p1)\n cocci.print_secs(\"after\",p2)\n// \u003c/smpl\u003e\n\nSigned-off-by: Julia Lawall \u003cjulia@diku.dk\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "1cfd2bda8c486ae0e7a8005354758ebb68172bca", "tree": "76ce15f377d8d6eb3ae4aa8b8b0b415457e38d36", "parents": [ "b57bdda58cda0aaf6def042d101dd85977a286ed", "763e9db9994e27a7d2cb3701c8a097a867d0e0b4" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Aug 06 11:44:36 2010 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Aug 06 11:44:36 2010 -0700" }, "message": "Merge branch \u0027linux-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6\n\n* \u0027linux-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6: (30 commits)\n PCI: update for owner removal from struct device_attribute\n PCI: Fix warnings when CONFIG_DMI unset\n PCI: Do not run NVidia quirks related to MSI with MSI disabled\n x86/PCI: use for_each_pci_dev()\n PCI: use for_each_pci_dev()\n PCI: MSI: Restore read_msi_msg_desc(); add get_cached_msi_msg_desc()\n PCI: export SMBIOS provided firmware instance and label to sysfs\n PCI: Allow read/write access to sysfs I/O port resources\n x86/PCI: use host bridge _CRS info on ASRock ALiveSATA2-GLAN\n PCI: remove unused HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_{SIZE|BOUNDARY}\n PCI: disable mmio during bar sizing\n PCI: MSI: Remove unsafe and unnecessary hardware access\n PCI: Default PCIe ASPM control to on and require !EMBEDDED to disable\n PCI: kernel oops on access to pci proc file while hot-removal\n PCI: pci-sysfs: remove casts from void*\n ACPI: Disable ASPM if the platform won\u0027t provide _OSC control for PCIe\n PCI hotplug: make sure child bridges are enabled at hotplug time\n PCI hotplug: shpchp: Removed check for hotplug of display devices\n PCI hotplug: pciehp: Fixed return value sign for pciehp_unconfigure_device\n PCI: Don\u0027t enable aspm before drivers have had a chance to veto it\n ...\n" }, { "commit": "bfb51cd01661136bae1dd00c32d504cff6a9f924", "tree": "0fa29f7e27f6bac5741b6dad123759481ced5847", "parents": [ "253d2e549818f5a4a52e2db0aba3dacee21e5b38" ], "author": { "name": "FUJITA Tomonori", "email": "fujita.tomonori@lab.ntt.co.jp", "time": "Mon Jul 12 15:59:11 2010 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jul 30 09:29:36 2010 -0700" }, "message": "PCI: remove unused HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_{SIZE|BOUNDARY}\n\nIn 2.6.34, we transformed the PCI DMA API into the generic device\nmode. The PCI DMA API is just the wrapper of the DMA API.\n\nSo we don\u0027t need HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE or\nHAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY (which enable architectures to\nhave the own implementations). Both haven\u0027t been used anyway.\n\nSigned-off-by: FUJITA Tomonori \u003cfujita.tomonori@lab.ntt.co.jp\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "c125e96f044427f38d106fab7bc5e4a5e6a18262", "tree": "d9bbd40cc933fe522dbdf8ca2f7edf7b6f2f7ca4", "parents": [ "b14e033e17d0ea0ba12668d0d2f371cd31586994" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Mon Jul 05 22:43:53 2010 +0200" }, "committer": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Mon Jul 19 01:58:48 2010 +0200" }, "message": "PM: Make it possible to avoid races between wakeup and system sleep\n\nOne of the arguments during the suspend blockers discussion was that\nthe mainline kernel didn\u0027t contain any mechanisms making it possible\nto avoid races between wakeup and system suspend.\n\nGenerally, there are two problems in that area. First, if a wakeup\nevent occurs exactly when /sys/power/state is being written to, it\nmay be delivered to user space right before the freezer kicks in, so\nthe user space consumer of the event may not be able to process it\nbefore the system is suspended. Second, if a wakeup event occurs\nafter user space has been frozen, it is not generally guaranteed that\nthe ongoing transition of the system into a sleep state will be\naborted.\n\nTo address these issues introduce a new global sysfs attribute,\n/sys/power/wakeup_count, associated with a running counter of wakeup\nevents and three helper functions, pm_stay_awake(), pm_relax(), and\npm_wakeup_event(), that may be used by kernel subsystems to control\nthe behavior of this attribute and to request the PM core to abort\nsystem transitions into a sleep state already in progress.\n\nThe /sys/power/wakeup_count file may be read from or written to by\nuser space. Reads will always succeed (unless interrupted by a\nsignal) and return the current value of the wakeup events counter.\nWrites, however, will only succeed if the written number is equal to\nthe current value of the wakeup events counter. If a write is\nsuccessful, it will cause the kernel to save the current value of the\nwakeup events counter and to abort the subsequent system transition\ninto a sleep state if any wakeup events are reported after the write\nhas returned.\n\n[The assumption is that before writing to /sys/power/state user space\nwill first read from /sys/power/wakeup_count. Next, user space\nconsumers of wakeup events will have a chance to acknowledge or\nveto the upcoming system transition to a sleep state. Finally, if\nthe transition is allowed to proceed, /sys/power/wakeup_count will\nbe written to and if that succeeds, /sys/power/state will be written\nto as well. Still, if any wakeup events are reported to the PM core\nby kernel subsystems after that point, the transition will be\naborted.]\n\nAdditionally, put a wakeup events counter into struct dev_pm_info and\nmake these per-device wakeup event counters available via sysfs,\nso that it\u0027s possible to check the activity of various wakeup event\nsources within the kernel.\n\nTo illustrate how subsystems can use pm_wakeup_event(), make the\nlow-level PCI runtime PM wakeup-handling code use it.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nAcked-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\nAcked-by: markgross \u003cmarkgross@thegnar.org\u003e\nReviewed-by: Alan Stern \u003cstern@rowland.harvard.edu\u003e\n" }, { "commit": "b03214d559471359e2a85ae256686381d0672f29", "tree": "b2c5d617304bffc8dd4917ecef251ec109eb3b8b", "parents": [ "686d363786a53ed28ee875b84ef24e6d5126ef6f" ], "author": { "name": "Michael S. Tsirkin", "email": "mst@redhat.com", "time": "Wed Jun 23 22:49:06 2010 -0600" }, "committer": { "name": "Rusty Russell", "email": "rusty@rustcorp.com.au", "time": "Wed Jun 23 22:49:07 2010 +0930" }, "message": "virtio-pci: disable msi at startup\n\nvirtio-pci resets the device at startup by writing to the status\nregister, but this does not clear the pci config space,\nspecifically msi enable status which affects register\nlayout.\n\nThis breaks things like kdump when they try to use e.g. virtio-blk.\n\nFix by forcing msi off at startup. Since pci.c already has\na routine to do this, we export and use it instead of duplicating code.\n\nSigned-off-by: Michael S. Tsirkin \u003cmst@redhat.com\u003e\nTested-by: Vivek Goyal \u003cvgoyal@redhat.com\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nCc: linux-pci@vger.kernel.org\nSigned-off-by: Rusty Russell \u003crusty@rustcorp.com.au\u003e\nCc: stable@kernel.org\n" }, { "commit": "6109e2ce2600e2db26cd0424bb9c6ed019723288", "tree": "54b5d347bf12e0a987edfb52f287399f748a9a38", "parents": [ "0961d6581c870850342ad6ea25263763433d666f", "ac81860ea073daed50246af54db706c6e491f240" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri May 21 18:58:52 2010 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri May 21 18:58:52 2010 -0700" }, "message": "Merge branch \u0027linux-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6\n\n* \u0027linux-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6: (36 commits)\n PCI: hotplug: pciehp: Removed check for hotplug of display devices\n PCI: read memory ranges out of Broadcom CNB20LE host bridge\n PCI: Allow manual resource allocation for PCI hotplug bridges\n x86/PCI: make ACPI MCFG reserved error messages ACPI specific\n PCI hotplug: Use kmemdup\n PM/PCI: Update PCI power management documentation\n PCI: output FW warning in pci_read/write_vpd\n PCI: fix typos pci_device_dis/enable to pci_dis/enable_device in comments\n PCI quirks: disable msi on AMD rs4xx internal gfx bridges\n PCI: Disable MSI for MCP55 on P5N32-E SLI\n x86/PCI: irq and pci_ids patch for additional Intel Cougar Point DeviceIDs\n PCI: aerdrv: trivial cleanup for aerdrv_core.c\n PCI: aerdrv: trivial cleanup for aerdrv.c\n PCI: aerdrv: introduce default_downstream_reset_link\n PCI: aerdrv: rework find_aer_service\n PCI: aerdrv: remove is_downstream\n PCI: aerdrv: remove magical ROOT_ERR_STATUS_MASKS\n PCI: aerdrv: redefine PCI_ERR_ROOT_*_SRC\n PCI: aerdrv: rework do_recovery\n PCI: aerdrv: rework get_e_source()\n ...\n" }, { "commit": "f39d01be4c59a61a08d0cb53f615e7016b85d339", "tree": "6777590e3ff2ddf4df1d38444ba7d692cd463b7b", "parents": [ "54291263519ac2c9bdda68b23b02fef3808deed4", "7db82437cfcac4bdfe79a6323eb554fdfa271623" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu May 20 09:20:59 2010 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu May 20 09:20:59 2010 -0700" }, "message": "Merge branch \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial\n\n* \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial: (44 commits)\n vlynq: make whole Kconfig-menu dependant on architecture\n add descriptive comment for TIF_MEMDIE task flag declaration.\n EEPROM: max6875: Header file cleanup\n EEPROM: 93cx6: Header file cleanup\n EEPROM: Header file cleanup\n agp: use NULL instead of 0 when pointer is needed\n rtc-v3020: make bitfield unsigned\n PCI: make bitfield unsigned\n jbd2: use NULL instead of 0 when pointer is needed\n cciss: fix shadows sparse warning\n doc: inode uses a mutex instead of a semaphore.\n uml: i386: Avoid redefinition of NR_syscalls\n fix \"seperate\" typos in comments\n cocbalt_lcdfb: correct sections\n doc: Change urls for sparse\n Powerpc: wii: Fix typo in comment\n i2o: cleanup some exit paths\n Documentation/: it\u0027s -\u003e its where appropriate\n UML: Fix compiler warning due to missing task_struct declaration\n UML: add kernel.h include to signal.c\n ...\n" }, { "commit": "ee6583f6e8f8dad4a53985dbabcd7c242d66a6b6", "tree": "e9ed3553db8af0134275fe5d35d26992a0d73040", "parents": [ "9313ff450400e6a2ab10fe6b9bdb12a828329410" ], "author": { "name": "Roman Fietze", "email": "roman.fietze@telemotive.de", "time": "Tue May 18 14:45:47 2010 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue May 18 14:59:08 2010 -0700" }, "message": "PCI: fix typos pci_device_dis/enable to pci_dis/enable_device in comments\n\nThis fixes all occurrences of pci_enable_device and pci_disable_device\nin all comments. There are no code changes involved.\n\nSigned-off-by: Roman Fietze \u003croman.fietze@telemotive.de\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "52b265a12768b9a72679bec825eb82c784116464", "tree": "59affe31ac556631a9012e13f93ea54e43109f2f", "parents": [ "75568f8094eb0333e9c2109b23cbc8b82d318a3c" ], "author": { "name": "Alan Stern", "email": "stern@rowland.harvard.edu", "time": "Mon Mar 08 16:48:49 2010 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue May 11 12:01:08 2010 -0700" }, "message": "PCI: clearing wakeup flags not needed\n\nThis patch (as1353) removes a couple of unnecessary assignments from\nthe PCI core. The should_wakeup flag is naturally initialized to 0;\nthere\u0027s no need to clear it.\n\nAcked-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Alan Stern \u003cstern@rowland.harvard.edu\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "6c9468e9eb1252eaefd94ce7f06e1be9b0b641b1", "tree": "797676a336b050bfa1ef879377c07e541b9075d6", "parents": [ "4cb3ca7cd7e2cae8d1daf5345ec99a1e8502cf3f", "c81eddb0e3728661d1585fbc564449c94165cc36" ], "author": { "name": "Jiri Kosina", "email": "jkosina@suse.cz", "time": "Fri Apr 23 02:08:44 2010 +0200" }, "committer": { "name": "Jiri Kosina", "email": "jkosina@suse.cz", "time": "Fri Apr 23 02:08:44 2010 +0200" }, "message": "Merge branch \u0027master\u0027 into for-next\n" }, { "commit": "cc2893b6af5265baa1d68b17b136cffca9e40cfa", "tree": "4de82276df0cbcf13b4fe50c267b91c2381723c2", "parents": [ "66528fdd45b082bf7c74687d72ae08afa4a446f8" ], "author": { "name": "Matthew Garrett", "email": "mjg@redhat.com", "time": "Thu Apr 22 09:30:51 2010 -0400" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Apr 22 16:13:47 2010 -0700" }, "message": "PCI: Ensure we re-enable devices on resume\n\nIf the firmware puts a device back into D0 state at resume time, we\u0027ll\nupdate its state in resume_noirq and thus skip the platform resume code.\nCalling that code twice should be safe and we ought to avoid getting to\nthat point anyway, so remove the check and also allow the platform pci\ncode to be called for D0.\n\nFixes USB not being powered after resume on recent Lenovo machines.\n\nAcked-by: Alex Chiang \u003cachiang@canonical.com\u003e\nAcked-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Matthew Garrett \u003cmjg@redhat.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "5a0e3ad6af8660be21ca98a971cd00f331318c05", "tree": "5bfb7be11a03176a87296a43ac6647975c00a1d1", "parents": [ "ed391f4ebf8f701d3566423ce8f17e614cde9806" ], "author": { "name": "Tejun Heo", "email": "tj@kernel.org", "time": "Wed Mar 24 17:04:11 2010 +0900" }, "committer": { "name": "Tejun Heo", "email": "tj@kernel.org", "time": "Tue Mar 30 22:02:32 2010 +0900" }, "message": "include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h\n\npercpu.h is included by sched.h and module.h and thus ends up being\nincluded when building most .c files. percpu.h includes slab.h which\nin turn includes gfp.h making everything defined by the two files\nuniversally available and complicating inclusion dependencies.\n\npercpu.h -\u003e slab.h dependency is about to be removed. Prepare for\nthis change by updating users of gfp and slab facilities include those\nheaders directly instead of assuming availability. As this conversion\nneeds to touch large number of source files, the following script is\nused as the basis of conversion.\n\n http://userweb.kernel.org/~tj/misc/slabh-sweep.py\n\nThe script does the followings.\n\n* Scan files for gfp and slab usages and update includes such that\n only the necessary includes are there. ie. if only gfp is used,\n gfp.h, if slab is used, slab.h.\n\n* When the script inserts a new include, it looks at the include\n blocks and try to put the new include such that its order conforms\n to its surrounding. It\u0027s put in the include block which contains\n core kernel includes, in the same order that the rest are ordered -\n alphabetical, Christmas tree, rev-Xmas-tree or at the end if there\n doesn\u0027t seem to be any matching order.\n\n* If the script can\u0027t find a place to put a new include (mostly\n because the file doesn\u0027t have fitting include block), it prints out\n an error message indicating which .h file needs to be added to the\n file.\n\nThe conversion was done in the following steps.\n\n1. The initial automatic conversion of all .c files updated slightly\n over 4000 files, deleting around 700 includes and adding ~480 gfp.h\n and ~3000 slab.h inclusions. The script emitted errors for ~400\n files.\n\n2. Each error was manually checked. Some didn\u0027t need the inclusion,\n some needed manual addition while adding it to implementation .h or\n embedding .c file was more appropriate for others. This step added\n inclusions to around 150 files.\n\n3. The script was run again and the output was compared to the edits\n from #2 to make sure no file was left behind.\n\n4. Several build tests were done and a couple of problems were fixed.\n e.g. lib/decompress_*.c used malloc/free() wrappers around slab\n APIs requiring slab.h to be added manually.\n\n5. The script was run on all .h files but without automatically\n editing them as sprinkling gfp.h and slab.h inclusions around .h\n files could easily lead to inclusion dependency hell. Most gfp.h\n inclusion directives were ignored as stuff from gfp.h was usually\n wildly available and often used in preprocessor macros. Each\n slab.h inclusion directive was examined and added manually as\n necessary.\n\n6. percpu.h was updated not to include slab.h.\n\n7. Build test were done on the following configurations and failures\n were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my\n distributed build env didn\u0027t work with gcov compiles) and a few\n more options had to be turned off depending on archs to make things\n build (like ipr on powerpc/64 which failed due to missing writeq).\n\n * x86 and x86_64 UP and SMP allmodconfig and a custom test config.\n * powerpc and powerpc64 SMP allmodconfig\n * sparc and sparc64 SMP allmodconfig\n * ia64 SMP allmodconfig\n * s390 SMP allmodconfig\n * alpha SMP allmodconfig\n * um on x86_64 SMP allmodconfig\n\n8. percpu.h modifications were reverted so that it could be applied as\n a separate patch and serve as bisection point.\n\nGiven the fact that I had only a couple of failures from tests on step\n6, I\u0027m fairly confident about the coverage of this conversion patch.\nIf there is a breakage, it\u0027s likely to be something in one of the arch\nheaders which should be easily discoverable easily on most builds of\nthe specific arch.\n\nSigned-off-by: Tejun Heo \u003ctj@kernel.org\u003e\nGuess-its-ok-by: Christoph Lameter \u003ccl@linux-foundation.org\u003e\nCc: Ingo Molnar \u003cmingo@redhat.com\u003e\nCc: Lee Schermerhorn \u003cLee.Schermerhorn@hp.com\u003e\n" }, { "commit": "7c9e2b1c4784c6e574f69dbd904b2822f2e04d6e", "tree": "4f11b13961671d83128866aa456688c7e437f243", "parents": [ "bdc2bda7c4dd253026cc1fce45fc939304749029" ], "author": { "name": "Dean Nelson", "email": "dnelson@redhat.com", "time": "Tue Mar 09 22:26:55 2010 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Mar 19 12:41:48 2010 -0700" }, "message": "PCI: cleanup error return for pcix get and set mmrbc functions\n\npcix_get_mmrbc() returns the maximum memory read byte count (mmrbc), if\nsuccessful, or an appropriate error value, if not.\n\nDistinguishing errors from correct values and understanding the meaning of an\nerror can be somewhat confusing in that:\n\n\tcorrect values: 512, 1024, 2048, 4096\n\terrors: -EINVAL \t\t\t-22\n \t\tPCIBIOS_FUNC_NOT_SUPPORTED\t0x81\n\t\tPCIBIOS_BAD_VENDOR_ID\t\t0x83\n\t\tPCIBIOS_DEVICE_NOT_FOUND\t0x86\n\t\tPCIBIOS_BAD_REGISTER_NUMBER\t0x87\n\t\tPCIBIOS_SET_FAILED\t\t0x88\n\t\tPCIBIOS_BUFFER_TOO_SMALL\t0x89\n\nThe PCIBIOS_ errors are returned from the PCI functions generated by the\nPCI_OP_READ() and PCI_OP_WRITE() macros.\n\nIn a similar manner, pcix_set_mmrbc() also returns the PCIBIOS_ error values\nreturned from pci_read_config_[word|dword]() and pci_write_config_word().\n\nFollowing pcix_get_max_mmrbc()\u0027s example, the following patch simply returns\n-EINVAL for all PCIBIOS_ errors encountered by pcix_get_mmrbc(), and -EINVAL\nor -EIO for those encountered by pcix_set_mmrbc().\n\nThis simplification was chosen in light of the fact that none of the current\ncallers of these functions are interested in the specific type of error\nencountered. In the future, should this change, one could simply create a\nfunction that maps each PCIBIOS_ error to a corresponding unique errno value,\nwhich could be called by pcix_get_max_mmrbc(), pcix_get_mmrbc(), and\npcix_set_mmrbc().\n\nAdditionally, this patch eliminates some unnecessary variables.\n\nCc: stable@kernel.org\nSigned-off-by: Dean Nelson \u003cdnelson@redhat.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "bdc2bda7c4dd253026cc1fce45fc939304749029", "tree": "2d77daf16bd33f570ffa83853aec64f2253d564b", "parents": [ "ded1d8f29b4d315a2093cafc3ee17ac870a87972" ], "author": { "name": "Dean Nelson", "email": "dnelson@redhat.com", "time": "Tue Mar 09 22:26:48 2010 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Mar 19 12:40:22 2010 -0700" }, "message": "PCI: fix access of PCI_X_CMD by pcix get and set mmrbc functions\n\nAn e1000 driver on a system with a PCI-X bus was always being returned\na value of 135 from both pcix_get_mmrbc() and pcix_set_mmrbc(). This\nvalue reflects an error return of PCIBIOS_BAD_REGISTER_NUMBER from\npci_bus_read_config_dword(,, cap + PCI_X_CMD,).\n\nThis is because for a dword, the following portion of the PCI_OP_READ()\nmacro:\n\n\tif (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER;\n\nexpands to:\n\n\tif (pos \u0026 3) return PCIBIOS_BAD_REGISTER_NUMBER;\n\nAnd is always true for \u0027cap + PCI_X_CMD\u0027, which is 0xe4 + 2 \u003d 0xe6. (\u0027cap\u0027 is\nthe result of calling pci_find_capability(, PCI_CAP_ID_PCIX).)\n\nThe same problem exists for pci_bus_write_config_dword(,, cap + PCI_X_CMD,).\nIn both cases, instead of calling _dword(), _word() should be called.\n\nCc: stable@kernel.org\nSigned-off-by: Dean Nelson \u003cdnelson@redhat.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "ded1d8f29b4d315a2093cafc3ee17ac870a87972", "tree": "fce932138ca3ca4b576271b7748ce33234d2fc8d", "parents": [ "25daeb550b69e89aff59bc6a84218a12b5203531" ], "author": { "name": "Paul Mundt", "email": "lethal@linux-sh.org", "time": "Thu Mar 11 14:08:33 2010 -0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Mar 19 12:38:18 2010 -0700" }, "message": "PCI: kill off pci_register_set_vga_state() symbol export.\n\nWhen pci_register_set_vga_state() was made __init, the EXPORT_SYMBOL() was\nretained, which now leaves us with a section mismatch.\n\nSigned-off-by: Paul Mundt \u003clethal@linux-sh.org\u003e\nCc: Mike Travis \u003ctravis@sgi.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "25daeb550b69e89aff59bc6a84218a12b5203531", "tree": "6e3f7191269e7199482f492bc6a43676742f3a94", "parents": [ "fc7f99cf36ebae853639dabb43bc2f0098c59aef" ], "author": { "name": "Dean Nelson", "email": "dnelson@redhat.com", "time": "Tue Mar 09 22:26:40 2010 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Mar 19 12:36:51 2010 -0700" }, "message": "PCI: fix return value from pcix_get_max_mmrbc()\n\nFor the PCI_X_STATUS register, pcix_get_max_mmrbc() is returning an incorrect\nvalue, which is based on:\n\n\t(stat \u0026 PCI_X_STATUS_MAX_READ) \u003e\u003e 12\n\nValid return values are 512, 1024, 2048, 4096, which correspond to a \u0027stat\u0027\n(masked and right shifted by 21) of 0, 1, 2, 3, respectively.\n\nA right shift by 11 would generate the correct return value when \u0027stat\u0027 (masked\nand right shifted by 21) has a value of 1 or 2. But for a value of 0 or 3 it\u0027s\nnot possible to generate the correct return value by only right shifting.\n\nFix is based on pcix_get_mmrbc()\u0027s similar dealings with the PCI_X_CMD register.\n\nCc: stable@kernel.org\nSigned-off-by: Dean Nelson \u003cdnelson@redhat.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "88393161210493e317ae391696ee8ef463cb3c23", "tree": "6ec81a50d0e8174b415d83948b48cbabd7e54ddb", "parents": [ "932fb06b0898f5883200f1da2e00075f0d70ba9c" ], "author": { "name": "Thomas Weber", "email": "swirl@gmx.li", "time": "Tue Mar 16 11:47:56 2010 +0100" }, "committer": { "name": "Jiri Kosina", "email": "jkosina@suse.cz", "time": "Tue Mar 16 11:47:56 2010 +0100" }, "message": "Fix typos in comments\n\n[Ss]ytem \u003d\u003e [Ss]ystem\nudpate \u003d\u003e update\nparamters \u003d\u003e parameters\norginal \u003d\u003e original\n\nSigned-off-by: Thomas Weber \u003cswirl@gmx.li\u003e\nAcked-by: Randy Dunlap \u003crdunlap@xenotime.net\u003e\nSigned-off-by: Jiri Kosina \u003cjkosina@suse.cz\u003e\n" }, { "commit": "5f3cd1e0bb452c31a306a3e764514ea2eaf7d2e0", "tree": "2fe245e004491e195127fe2327d48775b45ed4e1", "parents": [ "6fee48cd330c68332f9712bc968d934a1a84a32a" ], "author": { "name": "FUJITA Tomonori", "email": "fujita.tomonori@lab.ntt.co.jp", "time": "Wed Mar 10 15:23:41 2010 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Mar 12 15:52:42 2010 -0800" }, "message": "dma-mapping: pci: move pci_set_dma_mask and pci_set_consistent_dma_mask to pci-dma-compat.h\n\nWe can use pci-dma-compat.h to implement pci_set_dma_mask and\npci_set_consistent_dma_mask as we do with the other PCI DMA API.\n\nWe can remove HAVE_ARCH_PCI_SET_DMA_MASK too.\n\nSigned-off-by: FUJITA Tomonori \u003cfujita.tomonori@lab.ntt.co.jp\u003e\nCc: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nCc: Greg KH \u003cgreg@kroah.com\u003e\nCc: Kay Sievers \u003ckay.sievers@vrfy.org\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "6a1961f49ee8d7339ea2454443dfc0460e0b2748", "tree": "057b03936a7dac1fd88d94c963bc52c3619c0022", "parents": [ "e3c4bccabaf3e5c13f4b307c7737cbe8d0cecd02" ], "author": { "name": "FUJITA Tomonori", "email": "fujita.tomonori@lab.ntt.co.jp", "time": "Wed Mar 10 15:23:39 2010 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Mar 12 15:52:42 2010 -0800" }, "message": "dma-mapping: dma-mapping.h: add dma_set_coherent_mask\n\ndma_set_coherent_mask corresponds to pci_set_consistent_dma_mask. This is\nnecessary to move to the generic device model DMA API from the PCI bus\nspecific API in the long term.\n\ndma_set_coherent_mask works in the exact same way that\npci_set_consistent_dma_mask does. So this patch also changes\npci_set_consistent_dma_mask to call dma_set_coherent_mask.\n\nSigned-off-by: FUJITA Tomonori \u003cfujita.tomonori@lab.ntt.co.jp\u003e\nCc: James Bottomley \u003cJames.Bottomley@suse.de\u003e\nCc: David S. Miller \u003cdavem@davemloft.net\u003e\nCc: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nCc: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nCc: Russell King \u003clinux@arm.linux.org.uk\u003e\nCc: Greg KH \u003cgreg@kroah.com\u003e\nCc: Kay Sievers \u003ckay.sievers@vrfy.org\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "e3c4bccabaf3e5c13f4b307c7737cbe8d0cecd02", "tree": "e486608f8a24af1a7839ea28915a3b36dc568305", "parents": [ "c186caca3dbe7f44da624cb4f9d78e1b1dfb13b8" ], "author": { "name": "FUJITA Tomonori", "email": "fujita.tomonori@lab.ntt.co.jp", "time": "Wed Mar 10 15:23:38 2010 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Mar 12 15:52:42 2010 -0800" }, "message": "dma-mapping: pci: convert pci_set_dma_mask to call dma_set_mask\n\nThis changes pci_set_dma_mask to call the generic DMA API, dma_set_mask.\n\npci_set_dma_mask (in drivers/pci/pci.c) does the same things that\ndma_set_mask does on all the architectures that use pci_set_dma_mask;\ncalls dma_supprted and sets dev-\u003edma_mask. So we safely change\npci_set_dma_mask to simply call dma_set_mask.\n\nSigned-off-by: FUJITA Tomonori \u003cfujita.tomonori@lab.ntt.co.jp\u003e\nCc: James Bottomley \u003cJames.Bottomley@suse.de\u003e\nCc: David S. Miller \u003cdavem@davemloft.net\u003e\nCc: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nAcked-by: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nCc: Russell King \u003clinux@arm.linux.org.uk\u003e\nCc: Greg KH \u003cgreg@kroah.com\u003e\nCc: Kay Sievers \u003ckay.sievers@vrfy.org\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "522dba7134d6b2e5821d3457f7941ec34f668e6d", "tree": "e2ad937216c513a545abbe4ccff0c57519b9c080", "parents": [ "51d0f6d1f50349579f007adf5c0b51aaedd93b94", "bb910a7040e90a0ca3d3e8245d6d5c128a5d1287" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Mar 08 16:10:29 2010 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Mar 08 16:10:29 2010 -0800" }, "message": "Merge branch \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6\n\n* \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6:\n PCI/PM Runtime: Make runtime PM of PCI devices inactive by default\n" }, { "commit": "8e9394ce2412254ec69fd2a4f3e44a66eade2297", "tree": "355f25148b4ce3f5cfebeaf0939d71cb6beaf88b", "parents": [ "62e877b893e6350c900d381f353aa62ed48dcc97" ], "author": { "name": "Greg Kroah-Hartman", "email": "gregkh@suse.de", "time": "Wed Feb 17 10:57:05 2010 -0800" }, "committer": { "name": "Greg Kroah-Hartman", "email": "gregkh@suse.de", "time": "Sun Mar 07 17:04:52 2010 -0800" }, "message": "Driver core: create lock/unlock functions for struct device\n\nIn the future, we are going to be changing the lock type for struct\ndevice (once we get the lockdep infrastructure properly worked out) To\nmake that changeover easier, and to possibly burry the lock in a\ndifferent part of struct device, let\u0027s create some functions to lock and\nunlock a device so that no out-of-core code needs to be changed in the\nfuture.\n\nThis patch creates the device_lock/unlock/trylock() functions, and\nconverts all in-tree users to them.\n\nCc: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nCc: Jean Delvare \u003ckhali@linux-fr.org\u003e\nCc: Dave Young \u003chidave.darkstar@gmail.com\u003e\nCc: Ming Lei \u003ctom.leiming@gmail.com\u003e\nCc: Jiri Kosina \u003cjkosina@suse.cz\u003e\nCc: Phil Carmody \u003cext-phil.2.carmody@nokia.com\u003e\nCc: Arjan van de Ven \u003carjan@linux.intel.com\u003e\nCc: Cornelia Huck \u003ccornelia.huck@de.ibm.com\u003e\nCc: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nCc: Pavel Machek \u003cpavel@ucw.cz\u003e\nCc: Len Brown \u003clen.brown@intel.com\u003e\nCc: Magnus Damm \u003cdamm@igel.co.jp\u003e\nCc: Alan Stern \u003cstern@rowland.harvard.edu\u003e\nCc: Randy Dunlap \u003crandy.dunlap@oracle.com\u003e\nCc: Stefan Richter \u003cstefanr@s5r6.in-berlin.de\u003e\nCc: David Brownell \u003cdbrownell@users.sourceforge.net\u003e\nCc: Vegard Nossum \u003cvegard.nossum@gmail.com\u003e\nCc: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nCc: Alex Chiang \u003cachiang@hp.com\u003e\nCc: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nCc: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nCc: Andrew Patterson \u003candrew.patterson@hp.com\u003e\nCc: Yu Zhao \u003cyu.zhao@intel.com\u003e\nCc: Dominik Brodowski \u003clinux@dominikbrodowski.net\u003e\nCc: Samuel Ortiz \u003csameo@linux.intel.com\u003e\nCc: Wolfram Sang \u003cw.sang@pengutronix.de\u003e\nCc: CHENG Renquan \u003crqcheng@smu.edu.sg\u003e\nCc: Oliver Neukum \u003coliver@neukum.org\u003e\nCc: Frans Pop \u003celendil@planet.nl\u003e\nCc: David Vrabel \u003cdavid.vrabel@csr.com\u003e\nCc: Kay Sievers \u003ckay.sievers@vrfy.org\u003e\nCc: Sarah Sharp \u003csarah.a.sharp@linux.intel.com\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n\n\n" }, { "commit": "322aafa6645a48c3b7837ca7385f126ab78127fd", "tree": "50f6665aedcf051cecd571183df81ba7f248014b", "parents": [ "dd04265b028c00c365a78f9ff78a05e217f98656", "c7bbf52aa4fa332b84c4f2bb33e69561ee6870b4" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sun Mar 07 15:59:39 2010 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sun Mar 07 15:59:39 2010 -0800" }, "message": "Merge branch \u0027x86-mrst-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip\n\n* \u0027x86-mrst-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (30 commits)\n x86, mrst: Fix whitespace breakage in apb_timer.c\n x86, mrst: Fix APB timer per cpu clockevent\n x86, mrst: Remove X86_MRST dependency on PCI_IOAPIC\n x86, olpc: Use pci subarch init for OLPC\n x86, pci: Add arch_init to x86_init abstraction\n x86, mrst: Add Kconfig dependencies for Moorestown\n x86, pci: Exclude Moorestown PCI code if CONFIG_X86_MRST\u003dn\n x86, numaq: Make CONFIG_X86_NUMAQ depend on CONFIG_PCI\n x86, pci: Add sanity check for PCI fixed bar probing\n x86, legacy_irq: Remove duplicate vector assigment\n x86, legacy_irq: Remove left over nr_legacy_irqs\n x86, mrst: Platform clock setup code\n x86, apbt: Moorestown APB system timer driver\n x86, mrst: Add vrtc platform data setup code\n x86, mrst: Add platform timer info parsing code\n x86, mrst: Fill in PCI functions in x86_init layer\n x86, mrst: Add dummy legacy pic to platform setup\n x86/PCI: Moorestown PCI support\n x86, ioapic: Add dummy ioapic functions\n x86, ioapic: Early enable ioapic for timer irq\n ...\n\nFixed up semantic conflict of new clocksources due to commit\n17622339af25 (\"clocksource: add argument to resume callback\").\n" }, { "commit": "bb910a7040e90a0ca3d3e8245d6d5c128a5d1287", "tree": "1ee24e8ff4d4d1410db3af01a11193ce7595a980", "parents": [ "64096c17417380d8a472d096645f4cbc9406c987" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Sat Feb 27 21:37:37 2010 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Mar 05 15:09:39 2010 -0800" }, "message": "PCI/PM Runtime: Make runtime PM of PCI devices inactive by default\n\nMake the run-time power management of PCI devices be inactive by\ndefault by calling pm_runtime_forbid() for each PCI device during its\ninitialization. This setting may be overriden by the user space with\nthe help of the /sys/devices/.../power/control interface.\n\nThat\u0027s necessary to avoid breakage on systems where ACPI-based\nwake-up is known to fail for some devices.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "c7e15899d07c9813c1aa96b21699d2d9c8314c4b", "tree": "16e9b4dceddf1b4d1dad05588d700c70cf8fcb88", "parents": [ "f6a0b5cd34d6e922cc7258c5429fb0f17508ceb6", "78c06176466cbd1b3f0f67709d3023c40dbebcbd" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sun Feb 28 10:59:18 2010 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sun Feb 28 10:59:18 2010 -0800" }, "message": "Merge branch \u0027x86-pci-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip\n\n* \u0027x86-pci-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:\n x86: Enable NMI on all cpus on UV\n vgaarb: Add user selectability of the number of GPUS in a system\n vgaarb: Fix VGA arbiter to accept PCI domains other than 0\n x86, uv: Update UV arch to target Legacy VGA I/O correctly.\n pci: Update pci_set_vga_state() to call arch functions\n" }, { "commit": "a1e4d72cd3024999bfb6703092ea271438805c89", "tree": "853a289d73ad9ffb04038fc493d209e980a3ef9b", "parents": [ "09c09bc618a4ceec387c57542031b4fc35826e16" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Mon Feb 08 19:16:33 2010 +0100" }, "committer": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Fri Feb 26 20:39:12 2010 +0100" }, "message": "PM: Allow PCI devices to suspend/resume asynchronously\n\nSet power.async_suspend for all PCI devices and PCIe port services,\nso that they can be suspended and resumed in parallel with other\ndevices they don\u0027t depend on in a known way (i.e. devices which are\nnot their parents or children).\n\nThis only affects the \"regular\" suspend and resume stages, which\nmeans in particular that the restoration of the PCI devices\u0027 standard\nconfiguration registers during resume will still be carried out\nsynchronously (at the \"early\" resume stage).\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\n" }, { "commit": "89a74ecccd1f78e51faf6287e5c0e93a92ac096e", "tree": "6d167d73fb2cf5bb457b0b19145fcbf81cf441ef", "parents": [ "2adf75160b10bf3f09ed7d3d04e937f923fc557e" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Tue Feb 23 10:24:31 2010 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Feb 23 09:43:31 2010 -0800" }, "message": "PCI: add pci_bus_for_each_resource(), remove direct bus-\u003eresource[] refs\n\nNo functional change; this converts loops that iterate from 0 to\nPCI_BUS_NUM_RESOURCES through pci_bus resource[] table to use the\npci_bus_for_each_resource() iterator instead.\n\nThis doesn\u0027t change the way resources are stored; it merely removes\ndependencies on the fact that they\u0027re in a table.\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "6cbf82148ff286ec22a55be6836c3a5bffc489c1", "tree": "77b1b0097f9c2389d56734ec4c022611aa1bd9db", "parents": [ "552be54cc4232dc5acc49ccb372129d6f1b6923f" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Wed Feb 17 23:44:58 2010 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:21:19 2010 -0800" }, "message": "PCI PM: Run-time callbacks for PCI bus type\n\nIntroduce run-time PM callbacks for the PCI bus type. Make the new\ncallbacks work in analogy with the existing system sleep PM\ncallbacks, so that the drivers already converted to struct dev_pm_ops\ncan use their suspend and resume routines for run-time PM without\nmodifications.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "b67ea76172d4b1922c4b3c46c8ea8e9fec1ff38c", "tree": "c2f51811376060b3b59ac43243a182b94a48be9b", "parents": [ "3f0be67188c60ebf1b5d00354b44b4b24f5af313" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Wed Feb 17 23:44:09 2010 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:21:02 2010 -0800" }, "message": "PCI / ACPI / PM: Platform support for PCI PME wake-up\n\nAlthough the majority of PCI devices can generate PMEs that in\nprinciple may be used to wake up devices suspended at run time,\nplatform support is generally necessary to convert PMEs into wake-up\nevents that can be delivered to the kernel. If ACPI is used for this\npurpose, PME signals generated by a PCI device will trigger the ACPI\nGPE associated with the device to generate an ACPI wake-up event that\nwe can set up a handler for, provided that everything is configured\ncorrectly.\n\nUnfortunately, the subset of PCI devices that have GPEs associated\nwith them is quite limited. The devices without dedicated GPEs have\nto rely on the GPEs associated with other devices (in the majority of\ncases their upstream bridges and, possibly, the root bridge) to\ngenerate ACPI wake-up events in response to PME signals from them.\n\nAdd ACPI platform support for PCI PME wake-up:\no Add a framework making is possible to use ACPI system notify\n handlers for run-time PM.\no Add new PCI platform callback -\u003erun_wake() to struct\n pci_platform_pm_ops allowing us to enable/disable the platform to\n generate wake-up events for given device. Implemet this callback\n for the ACPI platform.\no Define ACPI wake-up handlers for PCI devices and PCI root buses and\n make the PCI-ACPI binding code register wake-up notifiers for all\n PCI devices present in the ACPI tables.\no Add function pci_dev_run_wake() which can be used by PCI drivers to\n check if given device is capable of generating wake-up events at\n run time.\n\nDeveloped in cooperation with Matthew Garrett \u003cmjg@redhat.com\u003e.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "58ff463396ad00828e922d50998787e97fd32512", "tree": "4964b07518a02736a23839d89bb7ac4a065dede8", "parents": [ "6d3be84aab461815978d970aa45f5bc9e52dd772" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Wed Feb 17 23:36:58 2010 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:20:24 2010 -0800" }, "message": "PCI PM: Add function for checking PME status of devices\n\nAdd function pci_check_pme_status() that will check the PME status\nbit of given device and clear it along with the PME enable bit. It\nwill be necessary for PCI run-time power management.\n\nBased on a patch from Shaohua Li \u003cshaohua.li@intel.com\u003e\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "93177a748ba0d4f3d3e51c8e6c785773bf6a70df", "tree": "1207e03e87d1b68a54ff159c9a8a2f279ea0b6a1", "parents": [ "3804259475314a50e4d7a8a974a22fddb6ac7dd7" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Sat Jan 02 22:57:24 2010 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:15:21 2010 -0800" }, "message": "PCI: Clean up build for CONFIG_PCI_QUIRKS unset\n\nCurrently, drivers/pci/quirks.c is built unconditionally, but if\nCONFIG_PCI_QUIRKS is unset, the only things actually built in this\nfile are definitions of global variables and empty functions (due to\nthe #ifdef CONFIG_PCI_QUIRKS embracing all of the code inside the\nfile). This is not particularly nice and if someone overlooks\nthe #ifdef CONFIG_PCI_QUIRKS, build errors are introduced.\n\nTo clean that up, move the definitions of the global variables in\nquirks.c that are always built to pci.c, move the definitions of\nthe empty functions (compiled when CONFIG_PCI_QUIRKS is unset) to\nheaders (additionally make these functions static inline) and modify\ndrivers/pci/Makefile so that quirks.c is only built if\nCONFIG_PCI_QUIRKS is set.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "cf4c43dd439b90a1a876b3f836ebe745abb9a269", "tree": "59d7a278d9d5cb6c9927819fa75231e284b29556", "parents": [ "724e6d3fe8003c3f60bf404bf22e4e331327c596" ], "author": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Jul 15 13:13:00 2009 -0700" }, "committer": { "name": "H. Peter Anvin", "email": "hpa@zytor.com", "time": "Fri Feb 19 16:12:26 2010 -0800" }, "message": "PCI: Add pci_bus_find_ext_capability\n\nFor use by code that needs to walk extended capability lists before\npci_dev structures are set up.\n\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nLKML-Reference: \u003c43F901BD926A4E43B106BF17856F07559FB80CFD@orsmsx508.amr.corp.intel.com\u003e\nSigned-off-by: Jacob Pan \u003cjacob.jun.pan@intel.com\u003e\nSigned-off-by: H. Peter Anvin \u003chpa@zytor.com\u003e\n" }, { "commit": "95a8b6efc5d07103583f706c8a5889437d537939", "tree": "a8e9161eea03b0eb21e838826c547771158ecdce", "parents": [ "499a2673713c85734a54c37dd90b4b729de399c4" ], "author": { "name": "Mike Travis", "email": "travis@sgi.com", "time": "Tue Feb 02 14:38:13 2010 -0800" }, "committer": { "name": "H. Peter Anvin", "email": "hpa@zytor.com", "time": "Fri Feb 05 14:05:41 2010 -0800" }, "message": "pci: Update pci_set_vga_state() to call arch functions\n\nUpdate pci_set_vga_state to call arch dependent functions to enable Legacy\nVGA I/O transactions to be redirected to correct target.\n\n[akpm@linux-foundation.org: make pci_register_set_vga_state() __init]\nSigned-off-by: Mike Travis \u003ctravis@sgi.com\u003e\nLKML-Reference: \u003c201002022238.o12McE1J018723@imap1.linux-foundation.org\u003e\nCc: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nCc: Robin Holt \u003cholt@sgi.com\u003e\nCc: Jack Steiner \u003csteiner@sgi.com\u003e\nCc: Ingo Molnar \u003cmingo@elte.hu\u003e\nCc: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nCc: David Airlie \u003cairlied@linux.ie\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: H. Peter Anvin \u003chpa@zytor.com\u003e\n" }, { "commit": "1ae861e652b5457e7fa98ccbc55abea1e207916e", "tree": "d0326aab2746a779f3ab140ec9fdea2508f2e99b", "parents": [ "6be954d1f91b81ca85c74792b13654069278c577" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Thu Dec 31 12:15:54 2009 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Jan 04 15:41:47 2010 -0800" }, "message": "PCI/PM: Use per-device D3 delays\n\nIt turns out that some PCI devices require extra delays when changing\npower state from D3 to D0 (and the other way around). Although this\nis against the PCI specification, we can handle it quite easily by\nallowing drivers to define arbitrary D3 delays for devices known to\nrequire extra time for switching power states.\n\nIntroduce additional field d3_delay in struct pci_dev and use it to\nstore the value of the device\u0027s D0-\u003eD3 delay, in miliseconds. Make\nthe PCI PM core code use the per-device d3_delay unless\npci_pm_d3_delay is greater (in which case the latter is used).\n[This also allows the driver to specify d3_delay shorter than the\n 10 ms required by the PCI standard if the device is known to be able\n to handle that.]\n\nMake the sky2 driver set d3_delay to 150 for devices handled by it.\n\nFixes http://bugzilla.kernel.org/show_bug.cgi?id\u003d14730 which is a\nlisted regression from 2.6.30.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "5b889bf237fca383b5807ad69fde3ad1e2287e42", "tree": "91c1df6fe04a187d31b62d96b1aa70abf3e04710", "parents": [ "9de54606d3d55095e4426a81a79a41d8e5e5b6be" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Thu Dec 31 19:06:35 2009 +0100" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Dec 31 12:00:45 2009 -0800" }, "message": "PCI: Fix build if quirks are not enabled\n\nAfter commit b9c3b266411d27f1a6466c19d146d08db576bfea (\"PCI: support\ndevice-specific reset methods\") the kernel build is broken if\nCONFIG_PCI_QUIRKS is unset.\n\nFix this by moving pci_dev_specific_reset() to drivers/pci/quirks.c and\nproviding an empty replacement for !CONFIG_PCI_QUIRKS builds.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nReported-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "2d1c861871d767153538a77c498752b36d4bb4b8", "tree": "2ed80140487cd68e539c55876ba361199a4b92c1", "parents": [ "7e8af37a9a71b479f58d2fd5f0ddaa6780c51f11" ], "author": { "name": "Benjamin Herrenschmidt", "email": "benh@kernel.crashing.org", "time": "Wed Dec 09 17:52:13 2009 +1100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Dec 16 18:55:51 2009 -0800" }, "message": "PCI/cardbus: Add a fixup hook and fix powerpc\n\nThe cardbus code creates PCI devices without ever going through the\nnecessary fixup bits and pieces that normal PCI devices go through.\n\nThere\u0027s in fact a commented out call to pcibios_fixup_bus() in there,\nit\u0027s commented because ... it doesn\u0027t work.\n\nI could make pcibios_fixup_bus() do the right thing on powerpc easily\nbut I felt it cleaner instead to provide a specific hook pci_fixup_cardbus\nfor which a weak empty implementation is provided by the PCI core.\n\nThis fixes cardbus on powerbooks and probably all other PowerPC\nplatforms which was broken completely for ever on some platforms and\nsince 2.6.31 on others such as PowerBooks when we made the DMA ops\nmandatory (since those are setup by the fixups).\n\nAcked-by: Dominik Brodowski \u003clinux@dominikbrodowski.net\u003e\nSigned-off-by: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "45e829ea412760d2404d7dfc42528df46aedbf62", "tree": "869581b5828f9eb16a5ce38231b58a80a30be67c", "parents": [ "5714868812b563ba8816c1d974f4f07c76941c30" ], "author": { "name": "Stefan Assmann", "email": "sassmann@redhat.com", "time": "Thu Dec 03 06:49:24 2009 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Dec 16 13:37:53 2009 -0800" }, "message": "PCI: change PCI nomenclature in drivers/pci/ (comment changes)\n\nChanging occurrences of variants of PCI-X and PCIe to the PCI-SIG\nterms listed in the \"Trademark and Logo Usage Guidelines\".\nhttp://www.pcisig.com/developers/procedures/logos/Trademark_and_Logo_Usage_Guidelines_updated_112206.pdf\n\nPatch is limited to drivers/pci/ and changes concern comments only.\n\nSigned-off-by: Stefan Assmann \u003csassmann@redhat.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "b9c3b266411d27f1a6466c19d146d08db576bfea", "tree": "c310b37e7dff6607e22eca0b690c2a3f290c85a9", "parents": [ "2820f333e3b4ad96590093efbed7b3400bcf492b" ], "author": { "name": "Dexuan Cui", "email": "dexuan.cui@intel.com", "time": "Mon Dec 07 13:03:21 2009 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Dec 16 13:37:50 2009 -0800" }, "message": "PCI: support device-specific reset methods\n\nAdd a new type of quirk for resetting devices at pci_dev_reset time.\nThis is necessary to handle device with nonstandard reset procedures,\nespecially useful for guest drivers.\n\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: Dexuan Cui \u003cdexuan.cui@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "9e0b5b2c447ad0caa075a5cfef86def62e1782ff", "tree": "ef8f5d5646ea7d1cd6cba366c5588b9c93ac61ff", "parents": [ "5d990b627537e59a3a2f039ff588a4750e9c1a6a" ], "author": { "name": "Kleber Sacilotto de Souza", "email": "klebers@linux.vnet.ibm.com", "time": "Wed Nov 25 00:55:51 2009 -0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 16:21:02 2009 -0800" }, "message": "PCI: fix coding style issue in pci_save_state()\n\nRemove a stray space in pci_save_state().\n\nSigned-off-by: Kleber Sacilotto de Souza \u003cklebers@linux.vnet.ibm.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "5d990b627537e59a3a2f039ff588a4750e9c1a6a", "tree": "8c0e723c3f9146da52b30c087a80fc417df2b41b", "parents": [ "b26a34aa4792b3db2500b8a98cb7702765c1a92e" ], "author": { "name": "Chris Wright", "email": "chrisw@sous-sol.org", "time": "Fri Dec 04 12:15:21 2009 -0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 16:19:24 2009 -0800" }, "message": "PCI: add pci_request_acs\n\nCommit ae21ee65e8bc228416bbcc8a1da01c56a847a60c \"PCI: acs p2p upsteram\nforwarding enabling\" doesn\u0027t actually enable ACS.\n\nAdd a function to pci core to allow an IOMMU to request that ACS\nbe enabled. The existing mechanism of using iommu_found() in the pci\ncore to know when ACS should be enabled doesn\u0027t actually work due to\ninitialization order; iommu has only been detected not initialized.\n\nHave Intel and AMD IOMMUs request ACS, and Xen does as well during early\ninit of dom0.\n\nCc: Allen Kay \u003callen.m.kay@intel.com\u003e\nCc: David Woodhouse \u003cdwmw2@infradead.org\u003e\nCc: Jeremy Fitzhardinge \u003cjeremy@goop.org\u003e\nCc: Joerg Roedel \u003cjoerg.roedel@amd.com\u003e\nSigned-off-by: Chris Wright \u003cchrisw@sous-sol.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "04b55c4732780381410e52db0e9bfb7661f2b4b3", "tree": "6c8a96438f40aa60038a9bd422c38833bdc7aa7a", "parents": [ "bb965401fd2afa26629b244e7bb2e48a117dc238" ], "author": { "name": "Shmulik Ravid", "email": "shmulikr@broadcom.com", "time": "Thu Dec 03 22:27:51 2009 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 15:49:44 2009 -0800" }, "message": "PCI: read-modify-write the pcie device control register when initiating pcie flr\n\nThe pcie_flr routine writes the device control register with the FLR bit\nset clearing all other fields for the FLR duration. Among other fields,\nthe Max_Payload_Size is also cleared which can cause errors if there are\ntransactions lurking in the HW pipeline. The patch replaces the blank\nwrite with read-modify-write of the control register keeping the other\nfields intact.\n\nSigned-off-by: Shmulik Ravid \u003cshmulikr@broadcom.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "c6a415761c59adabb53699c84e5cb42868d97c67", "tree": "0f5f8e1478c46d24748d804de90e4e3268f96c6b", "parents": [ "5c788a695ab5740413d9f9c0035d0d7aeef1c708" ], "author": { "name": "Yinghai Lu", "email": "yinghai@kernel.org", "time": "Wed Nov 25 16:28:50 2009 -0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 15:46:20 2009 -0800" }, "message": "PCI: add debug output for DMA mask info\n\nThis allows us to find out what DMA mask is used for each PCI device at boot\ntime; useful for debugging.\n\nAfter the patch:\nehci_hcd 0000:00:02.1: using 31bit consistent DMA mask\ne1000 0000:0b:01.0: using 64bit DMA mask\ne1000 0000:0b:01.0: using 64bit consistent DMA mask\ne1000e 0000:04:00.0: using 64bit DMA mask\ne1000e 0000:04:00.0: using 64bit consistent DMA mask\nixgb 0000:0c:01.0: using 64bit DMA mask\nixgb 0000:0c:01.0: using 64bit consistent DMA mask\naacraid 0000:86:00.0: using 32bit DMA mask\naacraid 0000:86:00.0: using 32bit consistent DMA mask\naacraid 0000:86:00.0: using 64bit DMA mask\naacraid 0000:86:00.0: using 64bit consistent DMA mask\nqla2xxx 0000:0c:02.0: using 64bit consistent DMA mask\nqla2xxx 0000:0c:02.1: using 64bit consistent DMA mask\nlpfc 0000:06:00.0: using 64bit DMA mask\nlpfc 0000:06:00.1: using 64bit DMA mask\npata_amd 0000:00:06.0: using 32bit DMA mask\npata_amd 0000:00:06.0: using 32bit consistent DMA mask\nmptsas 0000:0c:04.0: using 64bit DMA mask\nmptsas 0000:0c:04.0: using 64bit consistent DMA mask\n\nforcedeth 0000:00:08.0: using 39bit DMA mask\nforcedeth 0000:00:08.0: using 39bit consistent DMA mask\nniu 0000:02:00.0: using 44bit DMA mask\nniu 0000:02:00.0: using 44bit consistent DMA mask\nsata_nv 0000:00:05.0: using 32bit DMA mask\nsata_nv 0000:00:05.0: using 32bit consistent DMA mask\nib_mthca 0000:03:00.0: using 64bit DMA mask\nib_mthca 0000:03:00.0: using 64bit consistent DMA mask\n\nReviewed-by: Grant Grundler \u003cgrundler@google.com\u003e\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "5f4d91a1228ac85c75b099efd36fff1a3407335c", "tree": "ed0d13811c60bf3357ef70ea2931e29a358ed023", "parents": [ "7eb776c42e75d17bd8107a1359068d8c742639d1" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 11 14:36:17 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Nov 24 15:25:16 2009 -0800" }, "message": "PCI: use pci_is_pcie() in pci core\n\nChange for PCI core to use pci_is_pcie() instead of checking\npci_dev-\u003eis_pcie.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "06a1cbafb253c4c60d6a54a994887f5fbceabcc0", "tree": "e534c369ab1878a5d86996c29d629d1f5d8f9f75", "parents": [ "d7b7e60526d54da4c94afe5f137714cee7d05c41" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 11 14:30:56 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Nov 24 15:25:12 2009 -0800" }, "message": "PCI: use pci_pcie_cap() in pci core\n\nUse pcie_cap() instead of pci_find_capability() to get PCIe capability\noffset in PCI core code. This avoids unnecessary search in PCI\nconfiguration space.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "8c8def26bfaa704db67d515da3eb92cf26067548", "tree": "72e5ffc30964e2838ea3ea985c5bd451c31f5478", "parents": [ "e9d1e4921d5b62a80ed02851639249e2548d24f1" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Nov 09 12:04:32 2009 -0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 11 08:19:52 2009 +0000" }, "message": "PCI: allow matching of prefetchable resources to non-prefetchable windows\n\nI\u0027m not entirely sure it needs to go into 32, but it\u0027s probably the right\nthing to do. Another way of explaining the patch is:\n\n - we currently pick the _first_ exactly matching bus resource entry, but\n the _last_ inexactly matching one. Normally first/last shouldn\u0027t\n matter, but bus resource entries aren\u0027t actually all created equal: in\n a transparent bus, the last resources will be the parent resources,\n which we should generally try to avoid unless we have no choice. So\n \"first matching\" is the thing we should always aim for.\n\n - the patch is a bit bigger than it needs to be, because I simplified the\n logic at the same time. It used to be a fairly incomprehensible\n\n\tif ((res-\u003eflags \u0026 IORESOURCE_PREFETCH) \u0026\u0026 !(r-\u003eflags \u0026 IORESOURCE_PREFETCH))\n\t\tbest \u003d r; /* Approximating prefetchable by non-prefetchable */\n\n and technically, all the patch did was to make that complex choice be\n even more complex (it basically added a \"\u0026\u0026 !best\" to say that if we\n already gound a non-prefetchable window for the prefetchable resource,\n then we won\u0027t override an earlier one with that later one: remember\n \"first matching\").\n\n - So instead of that complex one with three separate conditionals in one,\n I split it up a bit, and am taking advantage of the fact that we\n already handled the exact case, so if \u0027res-\u003eflags\u0027 has the PREFETCH\n bit, then we already know that \u0027r-\u003eflags\u0027 will _not_ have it. So the\n simplified code drops the redundant test, and does the new \u0027!best\u0027 test\n separately. It also uses \u0027continue\u0027 as a way to ignore the bus\n resource we know doesn\u0027t work (ie a prefetchable bus resource is _not_\n acceptable for anything but an exact match), so it turns into:\n\n\t/* We can\u0027t insert a non-prefetch resource inside a prefetchable parent .. */\n\tif (r-\u003eflags \u0026 IORESOURCE_PREFETCH)\n\t\tcontinue;\n\t/* .. but we can put a prefetchable resource inside a non-prefetchable one */\n\tif (!best)\n\t\tbest \u003d r;\n\n instead. With the comments, it\u0027s now six lines instead of two, but it\u0027s\n conceptually simpler, and I _could_ have written it as two lines:\n\n\tif ((res-\u003eflags \u0026 IORESOURCE_PREFETCH) \u0026\u0026 !best)\n\t\tbest \u003d r;\t/* Approximating prefetchable by non-prefetchable */\n\n but I thought that was too damn subtle.\n\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "e9d1e4921d5b62a80ed02851639249e2548d24f1", "tree": "5fff809404f6de05ad610cffcb5b912c7dc049f3", "parents": [ "5b5d94487d934be6b0aa966c9acbdf15b07ef627" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Fri Nov 06 22:41:23 2009 +0000" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Nov 06 15:06:27 2009 -0800" }, "message": "PCI: Replace old style lock initializer\n\nSPIN_LOCK_UNLOCKED is deprecated. Use DEFINE_SPINLOCK instead.\n\nMake the lock static while at it.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "865df576e8fc70daf297b53e61a4fbefc719d065", "tree": "59abb13e1dd402bf8cb4496ab94bbceb2ac2ee2b", "parents": [ "0207c356ef0e2bae6ce4603080d42c130d7debc6" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Wed Nov 04 10:32:57 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 13:06:44 2009 -0800" }, "message": "PCI: improve discovery/configuration messages\n\nThis makes PCI resource management messages more consistent and adds a few\nnew messages to aid debugging.\n\nWhenever we assign resources to a device, update a BAR, or change a\nbridge aperture, it\u0027s worth noting it.\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "10c3d71d42f341775d96187eedd3e50eb34939d0", "tree": "1b0f751cd43ce628625b3b6abf05507bf3b12c37", "parents": [ "8d6cfdcdb50e94c92b3621422d909fa7cc41f866" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Wed Nov 04 10:32:42 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 13:06:42 2009 -0800" }, "message": "PCI: make PME# messages KERN_DEBUG\n\nMessages about PME# being supported and enabled/disabled are probably\nuseful for debug, but maybe don\u0027t need to be on the console.\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "c7dabef8a2c59e6a3de9d66fc35fb6a43ef7172d", "tree": "0f8b0021e693a0e380ef9026083b59d0909dffc6", "parents": [ "4fd8bdc567e70c02fab7eeaaa7d2a64232add789" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Tue Oct 27 13:26:47 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 13:06:41 2009 -0800" }, "message": "vsprintf: use %pR, %pr instead of %pRt, %pRf\n\nJesse accidentally applied v1 [1] of the patchset instead of v2 [2]. This\nis the diff between v1 and v2.\n\nThe changes in this patch are:\n - tidied vsprintf stack buffer to shrink and compute size more\n accurately\n - use %pR for decoding and %pr for \"raw\" (with type and flags) instead\n of adding %pRt and %pRf\n\n[1] http://lkml.org/lkml/2009/10/6/491\n[2] http://lkml.org/lkml/2009/10/13/441\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "ae21ee65e8bc228416bbcc8a1da01c56a847a60c", "tree": "cbcd109c764a8fed06f18a0a4bd3d63208405552", "parents": [ "1ccbf5344c3daef046d2323190cc6807c44f1917" ], "author": { "name": "Allen Kay", "email": "allen.m.kay@intel.com", "time": "Wed Oct 07 10:27:17 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 08:47:25 2009 -0800" }, "message": "PCI: acs p2p upsteram forwarding enabling\n\nNote: dom0 checking in v4 has been separated out into 2/2.\n\nThis patch enables P2P upstream forwarding in ACS capable PCIe switches.\nIt solves two potential problems in virtualization environment where a PCIe\ndevice is assigned to a guest domain using a HW iommu such as VT-d:\n\n1) Unintentional failure caused by guest physical address programmed\n into the device\u0027s DMA that happens to match the memory address range\n of other downstream ports in the same PCIe switch. This causes the PCI\n transaction to go to the matching downstream port instead of go to the\n root complex to get translated by VT-d as it should be.\n\n2) Malicious guest software intentionally attacks another downstream\n PCIe device by programming the DMA address into the assigned device\n that matches memory address range of the downstream PCIe port.\n\nWe are in process of implementing device filtering software in KVM/XEN\nmanagement software to allow device assignment of PCIe devices behind a PCIe\nswitch only if it has ACS capability and with the P2P upstream forwarding bits\nenabled. This patch is intended to work for both KVM and Xen environments.\n\nSigned-off-by: Allen Kay \u003callen.m.kay@intel.com\u003e\nReviewed-by: Mathew Wilcox \u003cwilly@linux.intel.com\u003e\nReviewed-by: Chris Wright \u003cchris@sous-sol.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" } ], "next": "a369c791e881503a6253dafc0d0ad5e41e5557e5" }