)]}' { "log": [ { "commit": "6e5fdeedca610df600aabc393c4b1f44b128fe49", "tree": "52a34c30bef1501f19c691a759b81b6f2603cd32", "parents": [ "bdfa97bf7263657b83bc5b68567a3a60dde84c5b" ], "author": { "name": "Paul Gortmaker", "email": "paul.gortmaker@windriver.com", "time": "Thu May 26 16:00:52 2011 -0400" }, "committer": { "name": "Paul Gortmaker", "email": "paul.gortmaker@windriver.com", "time": "Mon Oct 31 19:30:05 2011 -0400" }, "message": "kernel: Fix files explicitly needing EXPORT_SYMBOL infrastructure\n\nThese files were getting \u003clinux/module.h\u003e via an implicit non-obvious\npath, but we want to crush those out of existence since they cost\ntime during compiles of processing thousands of lines of headers\nfor no reason. Give them the lightweight header that just contains\nthe EXPORT_SYMBOL infrastructure.\n\nSigned-off-by: Paul Gortmaker \u003cpaul.gortmaker@windriver.com\u003e\n" }, { "commit": "825de2e9007439977aed63771db570fc2235e8cd", "tree": "261a210e0c075995831efd447b3c81deceea1d2a", "parents": [ "a7aaa4f888968b1261c2701cc66f18a3d4b9777b" ], "author": { "name": "Nobuhiro Iwamatsu", "email": "nobuhiro.iwamatsu.yj@renesas.com", "time": "Mon Oct 17 11:08:46 2011 +0900" }, "committer": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Mon Oct 24 15:22:33 2011 +0200" }, "message": "irq: Add EXPORT_SYMBOL_GPL to function of irq generic-chip\n\nSome functions of irq generic-chip is undefined, because\nEXPORT_SYMBOL_GPL is not set to these.\n\nERROR: \"irq_setup_generic_chip\" [drivers/gpio/gpio-pch.ko] undefined!\nERROR: \"irq_alloc_generic_chip\" [drivers/gpio/gpio-pch.ko] undefined!\nERROR: \"irq_setup_generic_chip\" [drivers/gpio/gpio-ml-ioh.ko] undefined!\nERROR: \"irq_alloc_generic_chip\" [drivers/gpio/gpio-ml-ioh.ko] undefined!\n\nThis is revised that EXPORT_SYMBOL_GPL can be added and referred\nto in functions.\n\nSigned-off-by: Nobuhiro Iwamatsu \u003cnobuhiro.iwamatsu.yj@renesas.com\u003e\nAcked-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\n" }, { "commit": "1dd75f91ae713049eb6baaa640078f3a6549e522", "tree": "24ce9355ca74a6fe6a179e61a9ab9418b17f2eae", "parents": [ "02f8c6aee8df3cdc935e9bdd4f2d020306035dbe" ], "author": { "name": "jhbird.choi@samsung.com", "email": "jhbird.choi@samsung.com", "time": "Thu Jul 21 15:29:14 2011 +0900" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Tue Jul 26 16:24:02 2011 +0200" }, "message": "genirq: Fix wrong bit operation\n\n(!msk \u0026 0x01) should be !(msk \u0026 0x01)\n\nSigned-off-by: Jonghwan Choi \u003cjhbird.choi@samsung.com\u003e\nLink: http://lkml.kernel.org/r/1311229754-6003-1-git-send-email-jhbird.choi@samsung.com\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nCc: stable@kernel.org\n" }, { "commit": "659fb32d1b67476f4ade25e9ea0e2642a5b9c4b5", "tree": "a875904f1c457f321563060491956266a57c6514", "parents": [ "d30e1521b2afb5e6f21ca8bc1a4b6ec2afc93597" ], "author": { "name": "Simon Guinot", "email": "sguinot@lacie.com", "time": "Wed Jul 06 12:41:31 2011 -0400" }, "committer": { "name": "Arnd Bergmann", "email": "arnd@arndb.de", "time": "Thu Jul 07 16:02:26 2011 +0000" }, "message": "genirq: replace irq_gc_ack() with {set,clr}_bit variants (fwd)\n\nThis fixes a regression introduced by e59347a \"arm: orion:\nUse generic irq chip\".\n\nDepending on the device, interrupts acknowledgement is done by setting\nor by clearing a dedicated register. Replace irq_gc_ack() with some\n{set,clr}_bit variants allows to handle both cases.\n\nNote that this patch affects the following SoCs: Davinci, Samsung and\nOrion. Except for this last, the change is minor: irq_gc_ack() is just\nrenamed into irq_gc_ack_set_bit().\n\nFor the Orion SoCs, the edge GPIO interrupts support is currently\nbroken. irq_gc_ack() try to acknowledge a such interrupt by setting\nthe corresponding cause register bit. The Orion GPIO device expect the\nopposite. To fix this issue, the irq_gc_ack_clr_bit() variant is used.\n\nTested on Network Space v2.\n\nReported-by: Joey Oravec \u003cjoravec@drewtech.com\u003e\nSigned-off-by: Simon Guinot \u003csguinot@lacie.com\u003e\nSigned-off-by: Arnd Bergmann \u003carnd@arndb.de\u003e\n" }, { "commit": "cfefd21e693dca791bf9ecfc9dd3794facad533c", "tree": "20915250e5c9749eea148cab17534b70c094386f", "parents": [ "7d8280624797bbe2f5170bd3c85c75a8c9c74242" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Fri Apr 15 22:36:08 2011 +0200" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sat Apr 23 15:56:24 2011 +0200" }, "message": "genirq: Add chip suspend and resume callbacks\n\nThese callbacks are only called in the syscore suspend/resume code on\ninterrupt chips which have been registered via the generic irq chip\nmechanism. Calling those callbacks per irq would be rather icky, but\nwith the generic irq chip mechanism we can call this per registered\nchip.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nCc: linux-arm-kernel@lists.infradead.org\n" }, { "commit": "7d8280624797bbe2f5170bd3c85c75a8c9c74242", "tree": "8028581a9a51eeb3c168409b5645c68b7a32e7dd", "parents": [ "7f1b1244e159a8490d7fb13667c6cb7e1e75046b" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sun Apr 03 11:42:53 2011 +0200" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sat Apr 23 15:56:24 2011 +0200" }, "message": "genirq: Implement a generic interrupt chip\n\nImplement a generic interrupt chip, which is configurable and is able\nto handle the most common irq chip implementations.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nCc: linux-arm-kernel@lists.infradead.org\nTested-by: H Hartley Sweeten \u003chsweeten@visionengravers.com\u003e\nTested-by: Tony Lindgren \u003ctony@atomide.com\u003e\nTested-by; Kevin Hilman \u003ckhilman@ti.com\u003e\n" } ] }