)]}' { "log": [ { "commit": "0244ad004a54e39308d495fee0a2e637f8b5c317", "tree": "b59152dc7cf57e7ffb9c8388ae9095e665406633", "parents": [ "5a7d8a28080caed7fd4cb1b81d092adac4445e8e" ], "author": { "name": "Martin Schwidefsky", "email": "schwidefsky@de.ibm.com", "time": "Fri Aug 30 09:39:53 2013 +0200" }, "committer": { "name": "Martin Schwidefsky", "email": "schwidefsky@de.ibm.com", "time": "Fri Sep 13 15:09:52 2013 +0200" }, "message": "Remove GENERIC_HARDIRQ config option\n\nAfter the last architecture switched to generic hard irqs the config\noptions HAVE_GENERIC_HARDIRQS \u0026 GENERIC_HARDIRQS and the related code\nfor !CONFIG_GENERIC_HARDIRQS can be removed.\n\nSigned-off-by: Martin Schwidefsky \u003cschwidefsky@de.ibm.com\u003e\n" }, { "commit": "1f6236bfd7c38d5f9f7648fae7215e65274b9e63", "tree": "756c6965b6d3ed842decc4d4ebfd70e8919fa8fc", "parents": [ "6fff8314046276331314ae32cea34c6d11c440d2" ], "author": { "name": "Javier Martinez Canillas", "email": "javier.martinez@collabora.co.uk", "time": "Fri Jun 14 18:40:43 2013 +0200" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Tue Jun 25 11:48:24 2013 +0200" }, "message": "genirq: Add irq_get_trigger_type() to get IRQ flags\n\nDrivers that want to get the trigger edge/level type flags for a given\ninterrupt have to call irq_get_irq_data(irq) to get the struct\nirq_data and then irqd_get_trigger_type(irq_data) to obtain the IRQ\nflags.\n\nThis is not only error prone but also unnecessary exposes the struct\nirq_data to callers.\n\nIt\u0027s better to have an irq_get_trigger_type() function to obtain the\nedge/level flags for an IRQ.\n\nSigned-off-by: Javier Martinez Canillas \u003cjavier.martinez@collabora.co.uk\u003e\nAcked-by: Grant Likely \u003cgrant.likely@linaro.org\u003e\nCc: Linus Walleij \u003clinus.walleij@linaro.org\u003e\nCc: Samuel Ortiz \u003csameo@linux.intel.com\u003e\nCc: Jason Cooper \u003cjason@lakedaemon.net\u003e\nCc: Andrew Lunn \u003candrew@lunn.ch\u003e\nCc: Russell King \u003clinux@arm.linux.org.uk\u003e\nCc: Ralf Baechle \u003cralf@linux-mips.org\u003e\nCc: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nCc: linux-arm-kernel@lists.infradead.org\nCc: linux-mips@linux-mips.org\nLink: http://lkml.kernel.org/r/1371228049-27080-2-git-send-email-javier.martinez@collabora.co.uk\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "e8bd834f73714378ef110a64287db1b77033c8da", "tree": "344493bc19c638aca611e3b5c7e44e234288685a", "parents": [ "088f40b7b027dad6519712ff224a5798dd62a204" ], "author": { "name": "Grant Likely", "email": "grant.likely@linaro.org", "time": "Wed May 29 03:10:52 2013 +0100" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Wed May 29 10:57:11 2013 +0200" }, "message": "genirq: irqchip: Add mask to block out invalid irqs\n\nSome controllers have irqs that aren\u0027t wired up and must never be used.\nFor the generic chip attached to an irq_domain this provides a mask that\ncan be used to block out particular irqs so that they never get mapped.\n\nSigned-off-by: Grant Likely \u003cgrant.likely@linaro.org\u003e\nLink: http://lkml.kernel.org/r/1369793454-19197-2-git-send-email-grant.likely@linaro.org\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "088f40b7b027dad6519712ff224a5798dd62a204", "tree": "bae6f2d67cc4516471d3b4a6a80da31962cb804b", "parents": [ "3528d82b684680b72fa31881c8c572c5a98b51de" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Mon May 06 14:30:27 2013 +0000" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Wed May 29 10:57:11 2013 +0200" }, "message": "genirq: Generic chip: Add linear irq domain support\n\nProvide infrastructure for irq chip implementations which work on\nlinear irq domains.\n\n- Interface to allocate multiple generic chips which are associated to\n the irq domain.\n\n- Interface to get the generic chip pointer for a particular hardware\n interrupt in the domain.\n\n- irq domain mapping function to install the chip for a particular\n interrupt.\n\nNote: This lacks a removal function for now.\n\n[ Sebastian Hesselbarth: Mask cache and pointer math fixups ]\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nCc: Thomas Petazzoni \u003cthomas.petazzoni@free-electrons.com\u003e\nCc: Andrew Lunn \u003candrew@lunn.ch\u003e\nCc: Russell King - ARM Linux \u003clinux@arm.linux.org.uk\u003e\nCc: Jason Cooper \u003cjason@lakedaemon.net\u003e\nCc: Arnd Bergmann \u003carnd@arndb.de\u003e\nCc: Jean-Francois Moine \u003cmoinejf@free.fr\u003e\nCc: devicetree-discuss@lists.ozlabs.org\nCc: Rob Herring \u003crob.herring@calxeda.com\u003e\nCc: Jason Gunthorpe \u003cjgunthorpe@obsidianresearch.com\u003e\nCc: Gregory Clement \u003cgregory.clement@free-electrons.com\u003e\nCc: Gerlando Falauto \u003cgerlando.falauto@keymile.com\u003e\nCc: Rob Landley \u003crob@landley.net\u003e\nAcked-by: Grant Likely \u003cgrant.likely@linaro.org\u003e\nCc: Maxime Ripard \u003cmaxime.ripard@free-electrons.com\u003e\nCc: Ezequiel Garcia \u003cezequiel.garcia@free-electrons.com\u003e\nCc: linux-arm-kernel@lists.infradead.org\nCc: Sebastian Hesselbarth \u003csebastian.hesselbarth@gmail.com\u003e\nLink: http://lkml.kernel.org/r/20130506142539.450634298@linutronix.de\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "d0051816e619f8f082582bec07ffa51bdb4f2104", "tree": "5ae8874599ad25d7ac35847f7a25c44a70e2a5b7", "parents": [ "966dc736b819999cd2d3a6408d47d33b579f7d56" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Mon May 06 14:30:24 2013 +0000" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Wed May 29 10:57:10 2013 +0200" }, "message": "genirq: irqchip: Add a mask calculation function\n\nSome chips have weird bit mask access patterns instead of the linear\nyou expect. Allow them to calculate the cached mask themself.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nCc: Thomas Petazzoni \u003cthomas.petazzoni@free-electrons.com\u003e\nCc: Andrew Lunn \u003candrew@lunn.ch\u003e\nCc: Russell King - ARM Linux \u003clinux@arm.linux.org.uk\u003e\nCc: Jason Cooper \u003cjason@lakedaemon.net\u003e\nCc: Arnd Bergmann \u003carnd@arndb.de\u003e\nCc: Jean-Francois Moine \u003cmoinejf@free.fr\u003e\nCc: devicetree-discuss@lists.ozlabs.org\nCc: Rob Herring \u003crob.herring@calxeda.com\u003e\nCc: Jason Gunthorpe \u003cjgunthorpe@obsidianresearch.com\u003e\nCc: Gregory Clement \u003cgregory.clement@free-electrons.com\u003e\nCc: Gerlando Falauto \u003cgerlando.falauto@keymile.com\u003e\nCc: Rob Landley \u003crob@landley.net\u003e\nAcked-by: Grant Likely \u003cgrant.likely@linaro.org\u003e\nCc: Maxime Ripard \u003cmaxime.ripard@free-electrons.com\u003e\nCc: Ezequiel Garcia \u003cezequiel.garcia@free-electrons.com\u003e\nCc: linux-arm-kernel@lists.infradead.org\nCc: Sebastian Hesselbarth \u003csebastian.hesselbarth@gmail.com\u003e\nLink: http://lkml.kernel.org/r/20130506142539.302898834@linutronix.de\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "966dc736b819999cd2d3a6408d47d33b579f7d56", "tree": "49935202236e9d0b66cf7f9330d8c99eecc89b51", "parents": [ "af80b0fed67261dcba2ce2406db1d553d07cbe75" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Mon May 06 14:30:22 2013 +0000" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Wed May 29 10:57:10 2013 +0200" }, "message": "genirq: Generic chip: Cache per irq bit mask\n\nCache the per irq bit mask instead of recalculating it over and over.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nCc: Thomas Petazzoni \u003cthomas.petazzoni@free-electrons.com\u003e\nCc: Andrew Lunn \u003candrew@lunn.ch\u003e\nCc: Russell King - ARM Linux \u003clinux@arm.linux.org.uk\u003e\nCc: Jason Cooper \u003cjason@lakedaemon.net\u003e\nCc: Arnd Bergmann \u003carnd@arndb.de\u003e\nCc: Jean-Francois Moine \u003cmoinejf@free.fr\u003e\nCc: devicetree-discuss@lists.ozlabs.org\nCc: Rob Herring \u003crob.herring@calxeda.com\u003e\nCc: Jason Gunthorpe \u003cjgunthorpe@obsidianresearch.com\u003e\nCc: Gregory Clement \u003cgregory.clement@free-electrons.com\u003e\nCc: Gerlando Falauto \u003cgerlando.falauto@keymile.com\u003e\nCc: Rob Landley \u003crob@landley.net\u003e\nAcked-by: Grant Likely \u003cgrant.likely@linaro.org\u003e\nCc: Maxime Ripard \u003cmaxime.ripard@free-electrons.com\u003e\nCc: Ezequiel Garcia \u003cezequiel.garcia@free-electrons.com\u003e\nCc: linux-arm-kernel@lists.infradead.org\nCc: Sebastian Hesselbarth \u003csebastian.hesselbarth@gmail.com\u003e\nLink: http://lkml.kernel.org/r/20130506142539.227119865@linutronix.de\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "af80b0fed67261dcba2ce2406db1d553d07cbe75", "tree": "002d93bdc9e20eb11602e6ed3792e743f5a8e869", "parents": [ "899f0e66fff36ebb6dd6a83af9aa631f6cb7e0dc" ], "author": { "name": "Gerlando Falauto", "email": "gerlando.falauto@keymile.com", "time": "Mon May 06 14:30:21 2013 +0000" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Wed May 29 10:57:10 2013 +0200" }, "message": "genirq: Generic chip: Handle separate mask registers\n\nThere are cases where all irq_chip_type instances have separate mask\nregisters, making a shared mask register cache unsuitable for the\npurpose.\n\nIntroduce a new flag IRQ_GC_MASK_CACHE_PER_TYPE. If set, point the per\nchip mask pointer to the per chip private mask cache instead.\n\n[ tglx: Simplified code, renamed flag and massaged changelog ]\n\nSigned-off-by: Gerlando Falauto \u003cgerlando.falauto@keymile.com\u003e\nCc: Andrew Lunn \u003candrew@lunn.ch\u003e\nCc: Joey Oravec \u003cjoravec@drewtech.com\u003e\nCc: Lennert Buytenhek \u003ckernel@wantstofly.org\u003e\nCc: Russell King - ARM Linux \u003clinux@arm.linux.org.uk\u003e\nCc: Jason Gunthorpe \u003cjgunthorpe@obsidianresearch.com\u003e\nCc: Holger Brunck \u003cHolger.Brunck@keymile.com\u003e\nCc: Ezequiel Garcia \u003cezequiel.garcia@free-electrons.com\u003e\nAcked-by: Grant Likely \u003cgrant.likely@linaro.org\u003e\nCc: Sebastian Hesselbarth \u003csebastian.hesselbarth@gmail.com\u003e\nCc: Jason Cooper \u003cjason@lakedaemon.net\u003e\nCc: Arnd Bergmann \u003carnd@arndb.de\u003e\nCc: devicetree-discuss@lists.ozlabs.org\nCc: Rob Herring \u003crob.herring@calxeda.com\u003e\nCc: Ben Dooks \u003cben-linux@fluff.org\u003e\nCc: Gregory Clement \u003cgregory.clement@free-electrons.com\u003e\nCc: Simon Guinot \u003csimon@sequanux.org\u003e\nCc: linux-arm-kernel@lists.infradead.org\nCc: Thomas Petazzoni \u003cthomas.petazzoni@free-electrons.com\u003e\nCc: Jean-Francois Moine \u003cmoinejf@free.fr\u003e\nCc: Nicolas Pitre \u003cnico@fluxnic.net\u003e\nCc: Rob Landley \u003crob@landley.net\u003e\nCc: Maxime Ripard \u003cmaxime.ripard@free-electrons.com\u003e\nLink: http://lkml.kernel.org/r/20130506142539.152569748@linutronix.de\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "899f0e66fff36ebb6dd6a83af9aa631f6cb7e0dc", "tree": "ae6f3d0ee7f7c55c103aae9e987427709fe70b33", "parents": [ "cfeaa93f8a13ae9117ae20933a38a406de80849e" ], "author": { "name": "Gerlando Falauto", "email": "gerlando.falauto@keymile.com", "time": "Mon May 06 14:30:19 2013 +0000" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Wed May 29 10:57:10 2013 +0200" }, "message": "genirq: Generic chip: Add support for per chip type mask cache\n\nToday the same interrupt mask cache (stored within struct irq_chip_generic)\nis shared between all the irq_chip_type instances. As there are instances\nwhere each irq_chip_type uses a distinct mask register (as it is the case\nfor Orion SoCs), sharing a single mask cache may be incorrect.\nSo add a distinct pointer for each irq_chip_type, which for now\npoints to the original mask register within irq_chip_generic.\nSo no functional changes here.\n\n[ tglx: Minor cosmetic tweaks ]\n\nReported-by: Joey Oravec \u003cjoravec@drewtech.com\u003e\nSigned-off-by: Simon Guinot \u003csguinot@lacie.com\u003e\nSigned-off-by: Holger Brunck \u003cholger.brunck@keymile.com\u003e\nSigned-off-by: Gerlando Falauto \u003cgerlando.falauto@keymile.com\u003e\nCc: Andrew Lunn \u003candrew@lunn.ch\u003e\nCc: Lennert Buytenhek \u003ckernel@wantstofly.org\u003e\nCc: Russell King - ARM Linux \u003clinux@arm.linux.org.uk\u003e\nCc: Jason Gunthorpe \u003cjgunthorpe@obsidianresearch.com\u003e\nCc: Holger Brunck \u003cHolger.Brunck@keymile.com\u003e\nCc: Ezequiel Garcia \u003cezequiel.garcia@free-electrons.com\u003e\nAcked-by: Grant Likely \u003cgrant.likely@linaro.org\u003e\nCc: Sebastian Hesselbarth \u003csebastian.hesselbarth@gmail.com\u003e\nCc: Jason Cooper \u003cjason@lakedaemon.net\u003e\nCc: Arnd Bergmann \u003carnd@arndb.de\u003e\nCc: devicetree-discuss@lists.ozlabs.org\nCc: Rob Herring \u003crob.herring@calxeda.com\u003e\nCc: Ben Dooks \u003cben-linux@fluff.org\u003e\nCc: Gregory Clement \u003cgregory.clement@free-electrons.com\u003e\nCc: Simon Guinot \u003csimon@sequanux.org\u003e\nCc: linux-arm-kernel@lists.infradead.org\nCc: Thomas Petazzoni \u003cthomas.petazzoni@free-electrons.com\u003e\nCc: Jean-Francois Moine \u003cmoinejf@free.fr\u003e\nCc: Nicolas Pitre \u003cnico@fluxnic.net\u003e\nCc: Rob Landley \u003crob@landley.net\u003e\nCc: Maxime Ripard \u003cmaxime.ripard@free-electrons.com\u003e\nLink: http://lkml.kernel.org/r/20130506142539.082226607@linutronix.de\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "5afba62cc8a16716508605e02c1b02ee5f969184", "tree": "ea92242734bb94960f215a352b1774938f578cc3", "parents": [ "71054d8841b442bb3d8be60bde2bfac0483c19da" ], "author": { "name": "Joerg Roedel", "email": "joro@8bytes.org", "time": "Wed Sep 26 12:44:38 2012 +0200" }, "committer": { "name": "Joerg Roedel", "email": "joro@8bytes.org", "time": "Mon Jan 28 12:17:25 2013 +0100" }, "message": "x86, msi: Use IRQ remapping specific setup_msi_irqs routine\n\nUse seperate routines to setup MSI IRQs for both\nirq_remapping_enabled cases.\n\nSigned-off-by: Joerg Roedel \u003cjoro@8bytes.org\u003e\nAcked-by: Sebastian Andrzej Siewior \u003csebastian@breakpoint.cc\u003e\nReviewed-by: Konrad Rzeszutek Wilk \u003ckonrad.wilk@oracle.com\u003e\n" }, { "commit": "51906e779f2b13b38f8153774c4c7163d412ffd9", "tree": "970633752f6a5cea156226cd31457289ba16f1c5", "parents": [ "4cca6ea04d31c22a7d0436949c072b27bde41f86" ], "author": { "name": "Alexander Gordeev", "email": "agordeev@redhat.com", "time": "Mon Nov 19 16:01:29 2012 +0100" }, "committer": { "name": "Ingo Molnar", "email": "mingo@kernel.org", "time": "Thu Jan 24 17:25:12 2013 +0100" }, "message": "x86/MSI: Support multiple MSIs in presense of IRQ remapping\n\nThe MSI specification has several constraints in comparison with\nMSI-X, most notable of them is the inability to configure MSIs\nindependently. As a result, it is impossible to dispatch\ninterrupts from different queues to different CPUs. This is\nlargely devalues the support of multiple MSIs in SMP systems.\n\nAlso, a necessity to allocate a contiguous block of vector\nnumbers for devices capable of multiple MSIs might cause a\nconsiderable pressure on x86 interrupt vector allocator and\ncould lead to fragmentation of the interrupt vectors space.\n\nThis patch overcomes both drawbacks in presense of IRQ remapping\nand lets devices take advantage of multiple queues and per-IRQ\naffinity assignments.\n\nSigned-off-by: Alexander Gordeev \u003cagordeev@redhat.com\u003e\nCc: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\nCc: Suresh Siddha \u003csuresh.b.siddha@intel.com\u003e\nCc: Yinghai Lu \u003cyinghai@kernel.org\u003e\nCc: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nCc: Jeff Garzik \u003cjgarzik@pobox.com\u003e\nCc: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\nCc: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nCc: Peter Zijlstra \u003ca.p.zijlstra@chello.nl\u003e\nCc: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nLink: http://lkml.kernel.org/r/c8bd86ff56b5fc118257436768aaa04489ac0a4c.1353324359.git.agordeev@redhat.com\nSigned-off-by: Ingo Molnar \u003cmingo@kernel.org\u003e\n" }, { "commit": "c7708fac5a878d6e0f2de0aa19f9749cff4f707f", "tree": "21a59cbe503ca526697f7d0bce5e0e30980bcbc0", "parents": [ "3127f23f013eabe9b58132c05061684c49146ba3", "6726a807c38d7fd09bc23a0adc738efec6ff9492" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Dec 13 14:20:19 2012 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Dec 13 14:20:19 2012 -0800" }, "message": "Merge branch \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux\n\nPull s390 update from Martin Schwidefsky:\n \"Add support to generate code for the latest machine zEC12, MOD and XOR\n instruction support for the BPF jit compiler, the dasd safe offline\n feature and the big one: the s390 architecture gets PCI support!!\n Right before the world ends on the 21st ;-)\"\n\n* \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux: (41 commits)\n s390/qdio: rename the misleading PCI flag of qdio devices\n s390/pci: remove obsolete email addresses\n s390/pci: speed up __iowrite64_copy by using pci store block insn\n s390/pci: enable NEED_DMA_MAP_STATE\n s390/pci: no msleep in potential IRQ context\n s390/pci: fix potential NULL pointer dereference in dma_free_seg_table()\n s390/pci: use kmem_cache_zalloc instead of kmem_cache_alloc/memset\n s390/bpf,jit: add support for XOR instruction\n s390/bpf,jit: add support MOD instruction\n s390/cio: fix pgid reserved check\n vga: compile fix, disable vga for s390\n s390/pci: add PCI Kconfig options\n s390/pci: s390 specific PCI sysfs attributes\n s390/pci: PCI hotplug support via SCLP\n s390/pci: CHSC PCI support for error and availability events\n s390/pci: DMA support\n s390/pci: PCI adapter interrupts for MSI/MSI-X\n s390/bitops: find leftmost bit instruction support\n s390/pci: CLP interface\n s390/pci: base support\n ...\n" }, { "commit": "9a4da8a5b109906a64bed5aaeb83bf4edb1f5888", "tree": "2788d7c8fe3e90333555435c7539d9f31d2c520e", "parents": [ "e56e4e87e370a0f121450d52337969aa1be21ff7" ], "author": { "name": "Jan Glauber", "email": "jang@linux.vnet.ibm.com", "time": "Thu Nov 29 13:05:05 2012 +0100" }, "committer": { "name": "Martin Schwidefsky", "email": "schwidefsky@de.ibm.com", "time": "Fri Nov 30 17:47:21 2012 +0100" }, "message": "s390/pci: PCI adapter interrupts for MSI/MSI-X\n\nSupport PCI adapter interrupts using the Single-IRQ-mode. Single-IRQ-mode\ndisables an adapter IRQ automatically after delivering it until the SIC\ninstruction enables it again. This is used to reduce the number of IRQs\nfor streaming workloads.\n\nUp to 64 MSI handlers can be registered per PCI function.\nA hash table is used to map interrupt numbers to MSI descriptors.\nThe interrupt vector is scanned using the flogr instruction.\nOnly MSI/MSI-X interrupts are supported, no legacy INTs.\n\nSigned-off-by: Jan Glauber \u003cjang@linux.vnet.ibm.com\u003e\nSigned-off-by: Martin Schwidefsky \u003cschwidefsky@de.ibm.com\u003e\n" }, { "commit": "293a7a0a165c4f8327bbcf396cee9ec672727c98", "tree": "6f4dca36e85e5d7cd3648bb322b7db9c29fb8c85", "parents": [ "1e207eb1c3f0e8b690401f02fe08e7b53903f010" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Tue Oct 16 15:07:49 2012 -0700" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Thu Nov 01 12:11:31 2012 +0100" }, "message": "genirq: Provide means to retrigger parent\n\nAttempts to retrigger nested threaded IRQs currently fail because they\nhave no primary handler. In order to support retrigger of nested\nIRQs, the parent IRQ needs to be retriggered.\n\nTo fix, when an IRQ needs to be resent, if the interrupt has a parent\nIRQ and runs in the context of the parent IRQ, then resend the parent.\n\nAlso, handle_nested_irq() needs to clear the replay flag like the\nother handlers, otherwise check_irq_resend() will set it and it will\nnever be cleared. Without clearing, it results in the first resend\nworking fine, but check_irq_resend() returning early on subsequent\nresends because the replay flag is still set.\n\nProblem discovered on ARM/OMAP platforms where a nested IRQ that\u0027s\nalso a wakeup IRQ happens late in suspend and needed to be retriggered\nduring the resume process.\n\n[khilman@ti.com: changelog edits, clear IRQS_REPLAY in handle_nested_irq()]\n\nReported-by: Kevin Hilman \u003ckhilman@ti.com\u003e\nTested-by: Kevin Hilman \u003ckhilman@ti.com\u003e\nCc: linux-arm-kernel@lists.infradead.org\nLink: http://lkml.kernel.org/r/1350425269-11489-1-git-send-email-khilman@deeprootsystems.com\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "dc9b229a58dc0dfed34272ff26c6d5fd17c674e0", "tree": "722795c29e6037d971e76d52d607d7a70cbbefaf", "parents": [ "e2b34e311be3a57c9abcb927e37a57e38913714c" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Fri Jul 13 19:29:45 2012 +0200" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Wed Jul 25 12:46:38 2012 +0200" }, "message": "genirq: Allow irq chips to mark themself oneshot safe\n\nSome interrupt chips like MSI are oneshot safe by implementation. For\nthose interrupts we can avoid the mask/unmask sequence for threaded\ninterrupt handlers.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nLink: http://lkml.kernel.org/r/alpine.LFD.2.02.1207132056540.32033@ionos\nCc: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\nCc: Avi Kivity \u003cavi@redhat.com\u003e\nCc: Marcelo Tosatti \u003cmtosatti@redhat.com\u003e\nCc: Jan Kiszka \u003cjan.kiszka@web.de\u003e\n" }, { "commit": "bd3e57f9132ac55e2848aa10cf50341de2508e1d", "tree": "3633129fe02e804852a18c8e9b3045f35db6db0b", "parents": [ "3fad0953a12f92289f1e35f091c4fa09d8e1884e", "36d93d88a5396baa135f8bcde7b8501dfe3b8e53" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sun Jul 22 12:19:36 2012 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sun Jul 22 12:19:36 2012 -0700" }, "message": "Merge branch \u0027x86-platform-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip\n\nPull x86 platform changes from Ingo Molnar:\n \"This tree mostly involves various APIC driver cleanups/robustization,\n and vSMP motivated platform callback improvements/cleanups\"\n\nFix up trivial conflict due to printk cleanup right next to return value\nchange.\n\n* \u0027x86-platform-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (29 commits)\n Revert \"x86/early_printk: Replace obsolete simple_strtoul() usage with kstrtoint()\"\n x86/apic/x2apic: Use multiple cluster members for the irq destination only with the explicit affinity\n x86/apic/x2apic: Limit the vector reservation to the user specified mask\n x86/apic: Optimize cpu traversal in __assign_irq_vector() using domain membership\n x86/vsmp: Fix vector_allocation_domain\u0027s return value\n irq/apic: Use config_enabled(CONFIG_SMP) checks to clean up irq_set_affinity() for UP\n x86/vsmp: Fix linker error when CONFIG_PROC_FS is not set\n x86/apic/es7000: Make apicid of a cluster (not CPU) from a cpumask\n x86/apic/es7000+summit: Always make valid apicid from a cpumask\n x86/apic/es7000+summit: Fix compile warning in cpu_mask_to_apicid()\n x86/apic: Fix ugly casting and branching in cpu_mask_to_apicid_and()\n x86/apic: Eliminate cpu_mask_to_apicid() operation\n x86/x2apic/cluster: Vector_allocation_domain() should return a value\n x86/apic/irq_remap: Silence a bogus pr_err()\n x86/vsmp: Ignore IOAPIC IRQ affinity if possible\n x86/apic: Make cpu_mask_to_apicid() operations check cpu_online_mask\n x86/apic: Make cpu_mask_to_apicid() operations return error code\n x86/apic: Avoid useless scanning thru a cpumask in assign_irq_vector()\n x86/apic: Try to spread IRQ vectors to different priority levels\n x86/apic: Factor out default vector_allocation_domain() operation\n ...\n" }, { "commit": "87fac288083db40b5d5ab845393be268357c8827", "tree": "1d64ae431471dfafb82d7e9fc51d0e157d17cc7e", "parents": [ "c76760926a802d0b13e0a7c200224ec289611998" ], "author": { "name": "Randy Dunlap", "email": "rdunlap@xenotime.net", "time": "Sat Jun 30 15:30:46 2012 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sat Jun 30 15:56:40 2012 -0700" }, "message": "linux/irq.h: fix kernel-doc warning\n\nFix kernel-doc warning. This struct member was removed in commit\n875682648b89 (\"irq: Remove irq_chip-\u003erelease()\") so remove its\nassociated kernel-doc entry also.\n\n Warning(include/linux/irq.h:338): Excess struct/union/enum/typedef member \u0027release\u0027 description in \u0027irq_chip\u0027\n\nSigned-off-by: Randy Dunlap \u003crdunlap@xenotime.net\u003e\nCc: Richard Weinberger \u003crichard@nod.at\u003e\nCc: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "7eb9ae0799b1e9f0b77733b432bc5f6f055b020b", "tree": "368645d861bcffeabf7cc56763c6337d9e4cbd0d", "parents": [ "879060d5745250c6f38304fd548d42b76f9df093" ], "author": { "name": "Suresh Siddha", "email": "suresh.b.siddha@intel.com", "time": "Thu Jun 14 18:28:49 2012 -0700" }, "committer": { "name": "Ingo Molnar", "email": "mingo@kernel.org", "time": "Fri Jun 15 14:17:29 2012 +0200" }, "message": "irq/apic: Use config_enabled(CONFIG_SMP) checks to clean up irq_set_affinity() for UP\n\nMove the -\u003eirq_set_affinity() routines out of the #ifdef CONFIG_SMP\nsections and use config_enabled(CONFIG_SMP) checks inside those\nroutines. Thus making those routines simple null stubs for\n!CONFIG_SMP and retaining those routines with no additional\nruntime overhead for CONFIG_SMP kernels.\n\nCleans up the ifdef CONFIG_SMP in and around routines related to\nirq_set_affinity in io_apic and irq_remapping subsystems.\n\nSigned-off-by: Suresh Siddha \u003csuresh.b.siddha@intel.com\u003e\nCc: torvalds@linux-foundation.org\nCc: joerg.roedel@amd.com\nCc: Sam Ravnborg \u003csam@ravnborg.org\u003e\nCc: Paul Gortmaker \u003cpaul.gortmaker@windriver.com\u003e\nLink: http://lkml.kernel.org/r/1339723729.3475.63.camel@sbsiddha-desk.sc.intel.com\nSigned-off-by: Ingo Molnar \u003cmingo@kernel.org\u003e\n" }, { "commit": "875682648b89a3ebc06176d60dc280f810647839", "tree": "515e2e1d69b18954b6e750e5e1aa042cc29c6bee", "parents": [ "985a94a96d294fe6d2c72d013de09b81b637ed58" ], "author": { "name": "Richard Weinberger", "email": "richard@nod.at", "time": "Tue Apr 17 22:37:16 2012 +0200" }, "committer": { "name": "Richard Weinberger", "email": "richard@nod.at", "time": "Mon May 21 21:09:38 2012 +0200" }, "message": "irq: Remove irq_chip-\u003erelease()\n\nAs it\u0027s only user (UML) does no longer need it we can get\nrid of it.\n\nSigned-off-by: Richard Weinberger \u003crichard@nod.at\u003e\nReviewed-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "3fca40c704dd013797f2c0c518f37cd2cc8e19fe", "tree": "250169398a74aca872c11717135f84826cbfbdad", "parents": [ "3a2b4f7c355ff1c97e4adebadf0a1aefd7c4518a" ], "author": { "name": "Benjamin Herrenschmidt", "email": "benh@kernel.crashing.org", "time": "Thu Apr 19 17:29:42 2012 +0000" }, "committer": { "name": "Benjamin Herrenschmidt", "email": "benh@kernel.crashing.org", "time": "Mon Apr 23 11:04:29 2012 +1000" }, "message": "irq: Add IRQ_TYPE_DEFAULT for use by PIC drivers\n\nThis is meant typically to allow a PIC driver\u0027s irq domain map() callback\nto establish sane defaults for the interrupt (and make sure that the HW\nand the irq_desc are in sync as far as the trigger is concerned).\n\nThe irq core may not call the set_trigger callback if it thinks the\ntrigger is already set to the right setting, so we need to ensure new\ndescriptors are properly synchronized with the hardware.\n\nSigned-off-by: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\n" }, { "commit": "a699e4e49ec3fb62c4a44394357d14081df10bef", "tree": "4a64e6fd8bc6a71fe7212a69f552f4aef3bd473c", "parents": [ "5b7526e3a640e491075557acaa842c59c652c0c3" ], "author": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Tue Apr 03 07:11:04 2012 -0600" }, "committer": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Tue Apr 10 22:39:17 2012 -0600" }, "message": "irq: Kill pointless irqd_to_hw export\n\nIt makes no sense to export this trivial function. Make it a static inline\ninstead.\n\nThis patch also drops virq_to_hw from arch/c6x since it is unused by that\narchitecture.\n\nv2: Move irq_hw_number_t into types.h to fix ARM build failure\n\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\nAcked-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nCc: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\n" }, { "commit": "ec53cf23c0ddb0c29950b9a4ac46964c4c6c6c2f", "tree": "198b2e172c5d9043ee10341092900e584c5f97f6", "parents": [ "1d58996da6a8045c8df2899ce5689a19c721322f" ], "author": { "name": "Paul Gortmaker", "email": "paul.gortmaker@windriver.com", "time": "Mon Sep 19 20:33:19 2011 -0400" }, "committer": { "name": "Paul Gortmaker", "email": "paul.gortmaker@windriver.com", "time": "Mon Oct 31 19:32:35 2011 -0400" }, "message": "irq: don\u0027t put module.h into irq.h for tracking irqgen modules.\n\nRecent commit \"irq: Track the owner of irq descriptor\" in\ncommit ID b6873807a7143b7 placed module.h into linux/irq.h\nbut we are trying to limit module.h inclusion to just C files\nthat really need it, due to its size and number of children\nincludes. This targets just reversing that include.\n\nAdd in the basic \"struct module\" since that is all we really need\nto ensure things compile. In theory, b687380 should have added the\nmodule.h include to the irqdesc.h header as well, but the implicit\nmodule.h everywhere presence masked this from showing up. So give\nit the \"struct module\" as well.\n\nAs for the C files, irqdesc.c is only using THIS_MODULE, so it\ndoes not need module.h - give it export.h instead. The C file\nirq/manage.c is now (as of b687380) using try_module_get and\nmodule_put and so it needs module.h (which it already has).\n\nAlso convert the irq_alloc_descs variants to macros, since all\nthey really do is is call the __irq_alloc_descs primitive.\nThis avoids including export.h and no debug info is lost.\n\nSigned-off-by: Paul Gortmaker \u003cpaul.gortmaker@windriver.com\u003e\n" }, { "commit": "31d9d9b6d83030f748d013e61502fa5477e2ac0e", "tree": "503670b94d594c09daa83c047b426e7b5328aa76", "parents": [ "60f96b41f71d2a13d1c0a457b8b77958f77142d1" ], "author": { "name": "Marc Zyngier", "email": "marc.zyngier@arm.com", "time": "Fri Sep 23 17:03:06 2011 +0100" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Mon Oct 03 15:35:26 2011 +0200" }, "message": "genirq: Add support for per-cpu dev_id interrupts\n\nThe ARM GIC interrupt controller offers per CPU interrupts (PPIs),\nwhich are usually used to connect local timers to each core. Each CPU\nhas its own private interface to the GIC, and only sees the PPIs that\nare directly connect to it.\n\nWhile these timers are separate devices and have a separate interrupt\nline to a core, they all use the same IRQ number.\n\nFor these devices, request_irq() is not the right API as it assumes\nthat an IRQ number is visible by a number of CPUs (through the\naffinity setting), but makes it very awkward to express that an IRQ\nnumber can be handled by all CPUs, and yet be a different interrupt\nline on each CPU, requiring a different dev_id cookie to be passed\nback to the handler.\n\nThe *_percpu_irq() functions is designed to overcome these\nlimitations, by providing a per-cpu dev_id vector:\n\nint request_percpu_irq(unsigned int irq, irq_handler_t handler,\n\t\t const char *devname, void __percpu *percpu_dev_id);\nvoid free_percpu_irq(unsigned int, void __percpu *);\nint setup_percpu_irq(unsigned int irq, struct irqaction *new);\nvoid remove_percpu_irq(unsigned int irq, struct irqaction *act);\nvoid enable_percpu_irq(unsigned int irq);\nvoid disable_percpu_irq(unsigned int irq);\n\nThe API has a number of limitations:\n- no interrupt sharing\n- no threading\n- common handler across all the CPUs\n\nOnce the interrupt is requested using setup_percpu_irq() or\nrequest_percpu_irq(), it must be enabled by each core that wishes its\nlocal interrupt to be delivered.\n\nBased on an initial patch by Thomas Gleixner.\n\nSigned-off-by: Marc Zyngier \u003cmarc.zyngier@arm.com\u003e\nCc: linux-arm-kernel@lists.infradead.org\nLink: http://lkml.kernel.org/r/1316793788-14500-2-git-send-email-marc.zyngier@arm.com\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "60f96b41f71d2a13d1c0a457b8b77958f77142d1", "tree": "3fdfa3f9a2e762139383938f0199ed2ed9ee5640", "parents": [ "ed585a651681e822089087b426e6ebfb6d3d9873" ], "author": { "name": "Santosh Shilimkar", "email": "santosh.shilimkar@ti.com", "time": "Fri Sep 09 13:59:35 2011 +0530" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Mon Sep 12 09:52:49 2011 +0200" }, "message": "genirq: Add IRQCHIP_SKIP_SET_WAKE flag\n\nSome irq chips need the irq_set_wake() functionality, but do not\nrequire a irq_set_wake() callback. Instead of forcing an empty\ncallback to be implemented add a flag which notes this fact. Check for\nthe flag in set_irq_wake_real() and return success when set.\n\nSigned-off-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\nCc: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "950d0a10d12578a270f3dfa9fd76fe5c2deb343f", "tree": "2467458b05ab13dd8875e43f3701fbc0c38cef0d", "parents": [ "ab7e2dbf9b5da4d4eb4fdb019cc8881fbeb1299b", "b6873807a7143b7d6d8b06809295e559d07d7deb" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Aug 17 10:23:50 2011 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Aug 17 10:23:50 2011 -0700" }, "message": "Merge branch \u0027irq-urgent-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip\n\n* \u0027irq-urgent-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:\n irq: Track the owner of irq descriptor\n irq: Always set IRQF_ONESHOT if no primary handler is specified\n genirq: Fix wrong bit operation\n" }, { "commit": "b6873807a7143b7d6d8b06809295e559d07d7deb", "tree": "1187413ab85f1a7b7d5da91bf61ae21601da3855", "parents": [ "f3637a5f2e2eb391ff5757bc83fb5de8f9726464" ], "author": { "name": "Sebastian Andrzej Siewior", "email": "sebastian@breakpoint.cc", "time": "Mon Jul 11 12:17:31 2011 +0200" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Thu Jul 28 11:23:21 2011 +0200" }, "message": "irq: Track the owner of irq descriptor\n\nInterrupt descriptors can be allocated from modules. The interrupts\nare used by other modules, but we have no refcount on the module which\nprovides the interrupts and there is no way to establish one on the\ndevice level as the interrupt using module is agnostic to the fact\nthat the interrupt is provided by a module rather than by some builtin\ninterrupt controller.\n\nTo prevent removal of the interrupt providing module, we can track the\nowner of the interrupt descriptor, which also provides the relevant\nirq chip functions in the irq descriptor.\n\nrequest/setup_irq() can now acquire a refcount on the owner module to\nprevent unloading. free_irq() drops the refcount.\n\nSigned-off-by: Sebastian Andrzej Siewior \u003csebastian@breakpoint.cc\u003e\nLink: http://lkml.kernel.org/r/20110711101731.GA13804@Chamillionaire.breakpoint.cc\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "08a543ad33fc188650801bd36eed4ffe272643e1", "tree": "cf2b41b922e77190425f999c2268f1558dd52d18", "parents": [ "5fd1a2ed0ec6fb5449c71a988cc15edb8671b3d0" ], "author": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Tue Jul 26 03:19:06 2011 -0600" }, "committer": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Thu Jul 28 01:32:04 2011 -0600" }, "message": "irq: add irq_domain translation infrastructure\n\nThis patch adds irq_domain infrastructure for translating from\nhardware irq numbers to linux irqs. This is particularly important\nfor architectures adding device tree support because the current\nimplementation (excluding PowerPC and SPARC) cannot handle\ntranslation for more than a single interrupt controller. irq_domain\nsupports device tree translation for any number of interrupt\ncontrollers.\n\nThis patch converts x86, Microblaze, ARM and MIPS to use irq_domain\nfor device tree irq translation. x86 is untested beyond compiling it,\nirq_domain is enabled for MIPS and Microblaze, but the old behaviour is\npreserved until the core code is modified to actually register an\nirq_domain yet. On ARM it works and is required for much of the new\nARM device tree board support.\n\nPowerPC has /not/ been converted to use this new infrastructure. It\nis still missing some features before it can replace the virq\ninfrastructure already in powerpc (see documentation on\nirq_domain_map/unmap for details). Followup patches will add the\nmissing pieces and migrate PowerPC to use irq_domain.\n\nSPARC has its own method of managing interrupts from the device tree\nand is unaffected by this change.\n\nAcked-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\n" }, { "commit": "c0c463d34adf0c150e5e24fa412fa23f3f7ddc27", "tree": "dfdf2ee7c6bb6662e8aa750c9145618085b092fd", "parents": [ "e72542191cbba4cf7fda21cb22e26b42d7415daf", "a03fc8c375511b6ab43184ab191af3218a919646", "f505c553dbe24b18a8590eb0eb5890a839acd0c3", "a7de915383a6d5c05663f9badbd10d5a87bc1586", "08a4a43fc407d780bdde36d98f89c0dbb2a6be6b" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sat Jul 23 10:33:08 2011 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sat Jul 23 10:33:08 2011 -0700" }, "message": "Merge branches \u0027x86-urgent-for-linus\u0027, \u0027core-debug-for-linus\u0027, \u0027irq-core-for-linus\u0027 and \u0027perf-urgent-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip\n\n* \u0027x86-urgent-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:\n um: Make rwsem.S depend on CONFIG_RWSEM_XCHGADD_ALGORITHM\n\n* \u0027core-debug-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:\n debug: Make CONFIG_EXPERT select CONFIG_DEBUG_KERNEL to unhide debug options\n\n* \u0027irq-core-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:\n genirq: Remove unused CHECK_IRQ_PER_CPU()\n\n* \u0027perf-urgent-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:\n perf tools, x86: Fix 32-bit compile on 64-bit system\n" }, { "commit": "659fb32d1b67476f4ade25e9ea0e2642a5b9c4b5", "tree": "a875904f1c457f321563060491956266a57c6514", "parents": [ "d30e1521b2afb5e6f21ca8bc1a4b6ec2afc93597" ], "author": { "name": "Simon Guinot", "email": "sguinot@lacie.com", "time": "Wed Jul 06 12:41:31 2011 -0400" }, "committer": { "name": "Arnd Bergmann", "email": "arnd@arndb.de", "time": "Thu Jul 07 16:02:26 2011 +0000" }, "message": "genirq: replace irq_gc_ack() with {set,clr}_bit variants (fwd)\n\nThis fixes a regression introduced by e59347a \"arm: orion:\nUse generic irq chip\".\n\nDepending on the device, interrupts acknowledgement is done by setting\nor by clearing a dedicated register. Replace irq_gc_ack() with some\n{set,clr}_bit variants allows to handle both cases.\n\nNote that this patch affects the following SoCs: Davinci, Samsung and\nOrion. Except for this last, the change is minor: irq_gc_ack() is just\nrenamed into irq_gc_ack_set_bit().\n\nFor the Orion SoCs, the edge GPIO interrupts support is currently\nbroken. irq_gc_ack() try to acknowledge a such interrupt by setting\nthe corresponding cause register bit. The Orion GPIO device expect the\nopposite. To fix this issue, the irq_gc_ack_clr_bit() variant is used.\n\nTested on Network Space v2.\n\nReported-by: Joey Oravec \u003cjoravec@drewtech.com\u003e\nSigned-off-by: Simon Guinot \u003csguinot@lacie.com\u003e\nSigned-off-by: Arnd Bergmann \u003carnd@arndb.de\u003e\n" }, { "commit": "a7de915383a6d5c05663f9badbd10d5a87bc1586", "tree": "7844a4f86dd8414c1edf59bef76723c65d225cd0", "parents": [ "e08f6d4131ab964420f0bcabecc68d75fb49df79" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Wed Jun 22 22:53:27 2011 +0200" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Wed Jun 22 22:55:02 2011 +0200" }, "message": "genirq: Remove unused CHECK_IRQ_PER_CPU()\n\nNo more users. Kill it.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "cfefd21e693dca791bf9ecfc9dd3794facad533c", "tree": "20915250e5c9749eea148cab17534b70c094386f", "parents": [ "7d8280624797bbe2f5170bd3c85c75a8c9c74242" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Fri Apr 15 22:36:08 2011 +0200" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sat Apr 23 15:56:24 2011 +0200" }, "message": "genirq: Add chip suspend and resume callbacks\n\nThese callbacks are only called in the syscore suspend/resume code on\ninterrupt chips which have been registered via the generic irq chip\nmechanism. Calling those callbacks per irq would be rather icky, but\nwith the generic irq chip mechanism we can call this per registered\nchip.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nCc: linux-arm-kernel@lists.infradead.org\n" }, { "commit": "7d8280624797bbe2f5170bd3c85c75a8c9c74242", "tree": "8028581a9a51eeb3c168409b5645c68b7a32e7dd", "parents": [ "7f1b1244e159a8490d7fb13667c6cb7e1e75046b" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sun Apr 03 11:42:53 2011 +0200" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sat Apr 23 15:56:24 2011 +0200" }, "message": "genirq: Implement a generic interrupt chip\n\nImplement a generic interrupt chip, which is configurable and is able\nto handle the most common irq chip implementations.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nCc: linux-arm-kernel@lists.infradead.org\nTested-by: H Hartley Sweeten \u003chsweeten@visionengravers.com\u003e\nTested-by: Tony Lindgren \u003ctony@atomide.com\u003e\nTested-by; Kevin Hilman \u003ckhilman@ti.com\u003e\n" }, { "commit": "7f1b1244e159a8490d7fb13667c6cb7e1e75046b", "tree": "1d5f5ff0ec14e3ac84d4ec17b0de4d43dacf8118", "parents": [ "770767787c23040dc152e7ae230597ff55b39470" ], "author": { "name": "Paul Mundt", "email": "lethal@linux-sh.org", "time": "Thu Apr 07 06:01:44 2011 +0900" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sat Apr 23 15:56:24 2011 +0200" }, "message": "genirq: Support per-IRQ thread disabling.\n\nThis adds support for disabling threading on a per-IRQ basis via the IRQ\nstatus instead of the IRQ flow, which is necessary for interrupts that\ndon\u0027t follow the natural IRQ flow channels, such as those that are\nvirtually created.\n\nThe new APIs added are simply:\n\n\tirq_set_thread()\n\tirq_set_nothread()\n\nwhich follow the rest of the IRQ status routines.\n\nChained handlers also have IRQ_NOTHREAD set on them automatically, making\nthe lack of threading explicit rather than implicit. Subsequently, the\nnothread flag can be viewed through the standard genirq debugging\nfacilities.\n\n[ tglx: Fixed cleanup fallout ]\n\nSigned-off-by: Paul Mundt \u003clethal@linux-sh.org\u003e\nLink: http://lkml.kernel.org/r/%3C20110406210135.GF18426%40linux-sh.org%3E\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n\n" }, { "commit": "0911f124bf55357803d53197cc1ae5479f5e37e2", "tree": "1c12a540ebc2527c14872183a51c2ddf2c5c3ae9", "parents": [ "f0e615c3cb72b42191b558c130409335812621d8" ], "author": { "name": "Geert Uytterhoeven", "email": "geert@linux-m68k.org", "time": "Sun Apr 10 11:01:51 2011 +0200" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sat Apr 23 15:56:23 2011 +0200" }, "message": "genirq: Forgotten updates/deletions after removal of compat code\n\ncommit 0c6f8a8b917ad361319c8ace3e9f28e69bfdb4c1 (\"genirq: Remove compat code\")\nremoved the compat code, but forgot to update some references in comments and\ndelete some of its documentation.\n\nSigned-off-by: Geert Uytterhoeven \u003cgeert@linux-m68k.org\u003e\nLink: http://lkml.kernel.org/r/%3C1302426113-13808-1-git-send-email-geert%40linux-m68k.org%3E\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "28959f268f910b2cd1c25e838b63c342062e28f2", "tree": "d1771510d76f7f6b5bae15a2e9dacc0bd6517600", "parents": [ "380a26be7d5af83f3831c3b6697031dffbb1c8f3" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Wed Mar 30 00:37:41 2011 +0200" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Wed Mar 30 00:37:41 2011 +0200" }, "message": "genirq: Remove obsolete comment\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "851d7cf647e0d31668eb5dc496f7698a2f6136b4", "tree": "15a292814827ef43cbfa6d28e41c7058bf71ebf7", "parents": [ "0c6f8a8b917ad361319c8ace3e9f28e69bfdb4c1" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Tue Mar 29 02:51:13 2011 +0200" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Tue Mar 29 14:50:32 2011 +0200" }, "message": "genirq: Remove move_*irq leftovers\n\nAll users converted to new interface.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "0c6f8a8b917ad361319c8ace3e9f28e69bfdb4c1", "tree": "b4b0cb4b619368bc93ff883f4b667e05a185549b", "parents": [ "dced35aeb0367dda2636ee9ee914bda14510dcc9" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Mon Mar 28 13:32:20 2011 +0200" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Tue Mar 29 14:48:19 2011 +0200" }, "message": "genirq: Remove compat code\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "30398bf6c684a77274dbdabf7efc1f24e4a99028", "tree": "d4ee5d514a53fbb8186bdbc726a525bb488c7dcf", "parents": [ "ee38c04b58983a236b43bae71b2415d38bceaf75" ], "author": { "name": "Randy Dunlap", "email": "randy.dunlap@oracle.com", "time": "Fri Mar 18 09:33:56 2011 -0700" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Mon Mar 28 20:13:57 2011 +0200" }, "message": "genirq: Fix new kernel-doc warnings\n\nFix new irq-related kernel-doc warnings in 2.6.38:\n\nWarning(kernel/irq/manage.c:149): No description found for parameter \u0027mask\u0027\nWarning(kernel/irq/manage.c:149): Excess function parameter \u0027cpumask\u0027 description in \u0027irq_set_affinity\u0027\nWarning(include/linux/irq.h:161): No description found for parameter \u0027state_use_accessors\u0027\nWarning(include/linux/irq.h:161): Excess struct/union/enum/typedef member \u0027state_use_accessor\u0027 description in \u0027irq_data\u0027\n\nSigned-off-by: Randy Dunlap \u003crandy.dunlap@oracle.com\u003e\nLKML-Reference: \u003c20110318093356.b939558d.randy.dunlap@oracle.com\u003e\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "ee38c04b58983a236b43bae71b2415d38bceaf75", "tree": "85c4c5d2ed68a7338743a74cde89643783551ce5", "parents": [ "9cff60dfc3d54b60bc069627cee5624bfaa3f823" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Mon Mar 28 17:11:13 2011 +0200" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Mon Mar 28 17:31:40 2011 +0200" }, "message": "genirq: Add setter for AFFINITY_SET in irq_data state\n\nSome archs want to prevent the default affinity being set on their\nchips in the reqeust_irq() path.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "9cff60dfc3d54b60bc069627cee5624bfaa3f823", "tree": "488202912c3d197baaf63202db61f9393201760f", "parents": [ "33b054b867b84015173a38d9cd9ff513b6498818" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Mon Mar 28 16:41:14 2011 +0200" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Mon Mar 28 16:55:12 2011 +0200" }, "message": "genirq: Provide setter inline for IRQD_IRQ_INPROGRESS\n\nSpecial function for demultiplexing handlers which can be disabled via\ndisable_irq().\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "33b054b867b84015173a38d9cd9ff513b6498818", "tree": "341f935d57af66fe82d384940b577fa9215ce5e6", "parents": [ "6829310548a76d343205029bb41c14e75bf6a7fb" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Mon Mar 28 16:27:31 2011 +0200" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Mon Mar 28 16:55:11 2011 +0200" }, "message": "genirq: Remove handle_IRQ_event\n\nLast user gone.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "0521c8fbb3da45c2a58cd551ca6e9644983f6028", "tree": "d2ed3452a75f1d3ff516cd02c86f4371db81e06e", "parents": [ "32f4125ebffee4f3c4dbc6a437fc656129eb9e60" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Mon Mar 28 16:13:24 2011 +0200" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Mon Mar 28 16:55:11 2011 +0200" }, "message": "genirq: Provide edge_eoi flow handler\n\nThis is a replacment for the cell flow handler which is in the way of\ncleanups. Must be selected to avoid general bloat.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "32f4125ebffee4f3c4dbc6a437fc656129eb9e60", "tree": "d64c6bb7ba40c33734896303734416ea5b4f3290", "parents": [ "c2d0c555c22242c3a76e366074c4d83ef9fa3b8c" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Mon Mar 28 14:10:52 2011 +0200" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Mon Mar 28 16:55:10 2011 +0200" }, "message": "genirq: Move INPROGRESS, MASKED and DISABLED state flags to irq_data\n\nWe really need these flags for some of the interrupt chips. Move it\nfrom internal state to irq_data and provide proper accessors.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nCc: David Daney \u003cddaney@caviumnetworks.com\u003e\n" }, { "commit": "c2d0c555c22242c3a76e366074c4d83ef9fa3b8c", "tree": "7426945b566129163639229fa0a5f420cdce13a8", "parents": [ "b3d422329f2e061d66af4f933ef316e50e5edcac" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Fri Mar 25 12:38:50 2011 -0700" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sun Mar 27 17:45:59 2011 +0200" }, "message": "genirq: Split irq_set_affinity() so it can be called with lock held.\n\nThe .irq_cpu_online() and .irq_cpu_offline() functions may need to\nadjust affinity, but they are called with the descriptor lock held.\nCreate __irq_set_affinity_locked() which is called with the lock held.\nMake irq_set_affinity() just a wrapper that acquires the lock.\n\n[ tglx: Changed the argument to irq_data, added a !desc check and\n moved the !irq_set_affinity check where it belongs ]\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nCc: linux-mips@linux-mips.org\nCc: ralf@linux-mips.org\nLKML-Reference: \u003c1301081931-11240-4-git-send-email-ddaney@caviumnetworks.com\u003e\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "b3d422329f2e061d66af4f933ef316e50e5edcac", "tree": "530100dd1733e24a017f4b3df4959c667369d236", "parents": [ "0fdb4b259ed3e91b687ac26848202f5e7c217e62" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sun Mar 27 16:05:36 2011 +0200" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sun Mar 27 17:45:58 2011 +0200" }, "message": "genirq: Add chip flag for restricting cpu_on/offline calls\n\nAdd a flag which indicates that the on/offline callback should only be\ncalled on enabled interrupts.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "0fdb4b259ed3e91b687ac26848202f5e7c217e62", "tree": "52503c0c5c35f95ab88a9867fc46c43fc7d9c200", "parents": [ "801a0e9ae36e9b487092e31699d28c0b9a21ad52" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Fri Mar 25 12:38:49 2011 -0700" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sun Mar 27 17:45:58 2011 +0200" }, "message": "genirq: Add chip hooks for taking CPUs on/off line.\n\n[ tglx: Removed the enabled argument as this is now available in\nirq_data ]\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nCc: linux-mips@linux-mips.org\nCc: ralf@linux-mips.org\nLKML-Reference: \u003c1301081931-11240-3-git-send-email-ddaney@caviumnetworks.com\u003e\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "801a0e9ae36e9b487092e31699d28c0b9a21ad52", "tree": "c448d150797272b09417f5410e7570742e59368b", "parents": [ "d72274e5895d11570a0a4a3214a1933c86d5ccb7" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sun Mar 27 11:02:49 2011 +0200" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sun Mar 27 17:45:58 2011 +0200" }, "message": "genirq: Add irq disabled flag to irq_data state\n\nSome irq_chip implementation require to know the disabled state of the\ninterrupt in certain callbacks. Add a state flag and accessor to\nirq_data.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "ab7798ffcf98b11a9525cf65bacdae3fd58d357f", "tree": "834ed73e8ab309895934bcf8bfe9e531ec10b32b", "parents": [ "08f1b807355c8d355885a71e7fd462fe9d499411" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Fri Mar 25 16:48:50 2011 +0100" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Fri Mar 25 17:04:20 2011 +0100" }, "message": "genirq: Expand generic show_interrupts()\n\nSome archs want to print extra information for certain irq_chips which\nis per irq and not per chip. Allow them to provide a chip callback to\nprint the chip name and the extra information.\n\nPowerPC wants to print the LEVEL/EDGE type information. Make it configurable.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "d209a699a0b975ad47f399d70ddc3791f1b84496", "tree": "225ee2dd5e51acc769cd272ce86d36405e933ed2", "parents": [ "d9936bb3952a08d701f7b03f8f62d158f94d8085" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Fri Mar 11 21:22:14 2011 +0100" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sat Mar 12 11:12:58 2011 +0100" }, "message": "genirq: Add chip flag to force mask on suspend\n\nOn suspend we disable all interrupts in the core code, but this does\nnot mask the interrupt line in the default implementation as we use a\nlazy disable approach. That means we mark the interrupt disabled, but\nleave the hardware unmasked. That\u0027s an optimization because we avoid\nthe hardware access for the common case where no interrupt happens\nafter we marked it disabled. If an interrupt happens, then the\ninterrupt flow handler masks the line at the hardware level and marks\nit pending.\n\nSuspend makes use of this delayed disable as it \"disables\" all\ninterrupts when preparing the suspend transition. Right before the\nsystem goes into hardware suspend state it checks whether one of the\ninterrupts which is marked as a wakeup interrupt came in after\ndisabling it.\n\nMost interrupt chips have a separate register which selects the\ninterrupts which can wake up the system from suspend, so we don\u0027t have\nto mask any on the non wakeup interrupts.\n\nBut now we have to deal with brilliant designed hardware which lacks\nsuch a wakeup configuration facility. For such hardware it\u0027s necessary\nto mask all non wakeup interrupts before going into suspend in order\nto avoid the wakeup from random interrupts.\n\nRather than working around this in the affected interrupt chip\nimplementations we can solve this elegant in the core code itself.\n\nAdd a flag IRQCHIP_MASK_ON_SUSPEND which can be set by the irq chip\nimplementation to indicate, that the interrupts which are not selected\nas wakeup sources must be masked in the suspend path. Mask them in the\nloop which checks the wakeup interrupts pending flag.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nReviewed-by: Abhijeet Dharmapurikar \u003cadharmap@codeaurora.org\u003e\nLKML-Reference: \u003calpine.LFD.2.00.1103112112310.2787@localhost6.localdomain6\u003e\n\n" }, { "commit": "a439520f8b18917b322f576be04c54aba84bb044", "tree": "b835a4b32c057408ed35292c02ad214341e317ed", "parents": [ "77694b408abb8f92195ad5ed6ce5492f1d794c77" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Fri Feb 04 18:46:16 2011 +0100" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sat Feb 19 12:58:25 2011 +0100" }, "message": "genirq: Implement irq_data based move_*_irq() versions\n\nNo need to lookup the irq descriptor when calling from a chip callback\nfunction which has irq_data already handy.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "77694b408abb8f92195ad5ed6ce5492f1d794c77", "tree": "a0f7e81a0a155523f69146cd560cc2f49543a99e", "parents": [ "781295762defc709a609efc01d8bb065276cd9a2" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Tue Feb 15 10:33:57 2011 +0100" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sat Feb 19 12:58:24 2011 +0100" }, "message": "genirq; Add fasteoi irq_chip quirk\n\nSome chips want irq_eoi() only called when an interrupt is actually\nhandled. So they have checks for INPROGRESS and DISABLED in their\nirq_eoi callbacks. Add a chip flag, which allows to handle that in the\ngeneric code. No impact on the fastpath.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "781295762defc709a609efc01d8bb065276cd9a2", "tree": "21f035b5f92571c8c3559b5e94eb0e1aa4113a36", "parents": [ "3836ca08aad4575c120ccf328652f3873eea9063" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Thu Feb 10 15:14:20 2011 +0100" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sat Feb 19 12:58:24 2011 +0100" }, "message": "genirq: Add preflow handler support\n\nsparc64 needs to call a preflow handler on certain interrupts befor\ncalling the action chain. Integrate it into handle_fasteoi_irq. Must\nbe enabled via CONFIG_IRQ_FASTEOI_PREFLOW. No impact when disabled.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nCc: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "3836ca08aad4575c120ccf328652f3873eea9063", "tree": "d5aa92880d2a44836cb7f3decdae761d0a780068", "parents": [ "02725e7471b8dd58fa96f6604bdb5dde45405a2e" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Mon Feb 14 20:09:19 2011 +0100" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sat Feb 19 12:58:23 2011 +0100" }, "message": "genirq: Consolidate set_chip_handler functions\n\nNo need to have separate functions if we have one plus inline wrappers.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "e1ef824146131709d7466e37f889f2dab24ca98e", "tree": "d66f8423fce8e4d04aa509e1cbbaea2fb99a812c", "parents": [ "7f94226f03299f1ca32f118f02f2a0295e0e5e93" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Thu Feb 10 22:25:31 2011 +0100" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sat Feb 19 12:58:22 2011 +0100" }, "message": "genirq: Reflect IRQ_MOVE_PCNTXT in irq_data state\n\nRequired by x86.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "7f94226f03299f1ca32f118f02f2a0295e0e5e93", "tree": "049a83a3c264d4378f341991800c345bf4eeb5a5", "parents": [ "d4d5e08960844a062da8387ee5f16ca7a33200d0" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Thu Feb 10 19:46:26 2011 +0100" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sat Feb 19 12:58:22 2011 +0100" }, "message": "genirq: Move wakeup state to irq_data\n\nSome irq_chips need to know the state of wakeup mode for\nsetting the trigger type etc. Reflect it in irq_data state.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "d4d5e08960844a062da8387ee5f16ca7a33200d0", "tree": "1154fd87e25595ae9391740a1d9a3d60f69770de", "parents": [ "2bff17ad2107c66fc8ca96501a7128dd7fa7a390" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Thu Feb 10 13:16:14 2011 +0100" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sat Feb 19 12:58:22 2011 +0100" }, "message": "genirq: Add IRQCHIP_SET_TYPE_MASKED flag\n\nirq_chips, which require to mask the chip before changing the trigger\ntype should set this flag. So the core takes care of it and the\nrequirement for looking into desc-\u003estatus in the chip goes away.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nCc: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nCc: Lars-Peter Clausen \u003clars@metafoo.de\u003e\n" }, { "commit": "2bff17ad2107c66fc8ca96501a7128dd7fa7a390", "tree": "a022acf5cdc290b1ede54f3d4a26b6365c3cc94b", "parents": [ "5d4d8fc9ac3e9a90bbdf90bae6864cb2c01f2208" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Thu Feb 10 13:08:38 2011 +0100" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sat Feb 19 12:58:21 2011 +0100" }, "message": "genirq: Add flags to irq_chip\n\nLooking through irq_chip implementations I noticed that some of them\nhave special requirements, like setting the type masked and therefor\nfiddle in irq_desc-\u003estatus. Add a flag field, so the core code can\nhandle it.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "5d4d8fc9ac3e9a90bbdf90bae6864cb2c01f2208", "tree": "5ec451adff8792ed345bac22c91d8565b11ba61a", "parents": [ "f9e4989eb8183a1f33581fa1b99274287b0639d2" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Tue Feb 08 17:27:18 2011 +0100" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sat Feb 19 12:58:21 2011 +0100" }, "message": "genirq: Cleanup irq.h\n\nPut the constants into an enum and document them.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "876dbd4cc1b35c1a4cb96a2be1d43ea0eabce3b4", "tree": "9be1e7e4cd4a4c9fadd98a9ac637020417215521", "parents": [ "2bdd10558c8d93009cb6c32ce9e30800fbb08add" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Tue Feb 08 17:28:12 2011 +0100" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sat Feb 19 12:58:20 2011 +0100" }, "message": "genirq: Mirror irq trigger type bits in irq_data.state\n\nThat\u0027s the data structure chip functions get provided. Also allow them\nto signal the core code that they updated the flags in irq_data.state\nby returning IRQ_SET_MASK_OK_NOCOPY. The default is unchanged.\n\nThe type bits should be accessed via:\n\nval \u003d irqd_get_trigger_type(irqdata);\nand\nirqd_set_trigger_type(irqdata, val);\n\nCoders who access them directly will be tracked down and slapped with\nstinking trouts.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "2bdd10558c8d93009cb6c32ce9e30800fbb08add", "tree": "f25b36c02faa8709628e2dbb93748f370678bb52", "parents": [ "bce43032ad79fae0ce5b6174ce1321e643ceb54b" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Tue Feb 08 17:22:00 2011 +0100" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sat Feb 19 12:58:20 2011 +0100" }, "message": "genirq: Move IRQ_AFFINITY_SET to core\n\nKeep status in sync until last abuser is gone.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "a005677b3dd05decdd8880cf3044ae709856f58f", "tree": "529d1454940fe8c6723bd54f01e009d9be2ab840", "parents": [ "1ce6068dac1924f7095be5850481e790cbf1b3c1" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Tue Feb 08 17:11:03 2011 +0100" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sat Feb 19 12:58:20 2011 +0100" }, "message": "genirq: Mirror IRQ_PER_CPU and IRQ_NO_BALANCING in irq_data.state\n\nThat\u0027s the right data structure to look at for arch code.\n\nAccessor functions are provided.\n\n\t irqd_is_per_cpu(irqdata);\n\t irqd_can_balance(irqdata);\n\nCoders who access them directly will be tracked down and slapped with\nstinking trouts.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "8f53f92404bead2ab2154d45c8f508880bb5d95d", "tree": "08a3f21df856f7d9b9561e6cf14462092cee8d0d", "parents": [ "6a58fb3bad099076f36f0f30f44507bc3275cdb6" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Tue Feb 08 16:50:00 2011 +0100" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sat Feb 19 12:58:19 2011 +0100" }, "message": "genirq: Make CHECK_IRQ_PER_CPU an inline and deprecate it\n\nIts\u0027 too ugly and needs to go. The only users are core code and\nparisc. Core code does not need it and parisc gets a new check once\nIRQ_PER_CPU is reflected in irq_data.state.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "6a58fb3bad099076f36f0f30f44507bc3275cdb6", "tree": "9a40117c941d914b1ef13463436657ae9721fea3", "parents": [ "f230b6d5c48f8d12f4dfa1f8b5ab0b0320076d21" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Tue Feb 08 15:40:05 2011 +0100" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sat Feb 19 12:58:19 2011 +0100" }, "message": "genirq: Remove CONFIG_IRQ_PER_CPU\n\nThe saving of this switch is minimal versus the ifdef mess it\ncreates. Simple enable PER_CPU unconditionally and remove the config\nswitch.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "f230b6d5c48f8d12f4dfa1f8b5ab0b0320076d21", "tree": "d4d30f77ab196930dd2d2982e90b1f2b5fd9bbe2", "parents": [ "91c499178139d6597e68db19638e4135510a34b8" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sat Feb 05 15:20:04 2011 +0100" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sat Feb 19 12:58:18 2011 +0100" }, "message": "genirq: Add IRQ_MOVE_PENDING to irq_data.state\n\nchip implementations need to know about it. Keep status in sync until\nall users are fixed. \n\nAccessor function: irqd_is_setaffinity_pending(irqdata)\n\nCoders who access them directly will be tracked down and slapped with\nstinking trouts.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "91c499178139d6597e68db19638e4135510a34b8", "tree": "9f2a58301e73178009d99e181d8de417659eda60", "parents": [ "6d2cd17fde1fc3e93302815f049f255bb2b3123e" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Thu Feb 03 20:48:29 2011 +0100" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sat Feb 19 12:58:18 2011 +0100" }, "message": "genirq: Add state field to irq_data\n\nSome chip implementations need to access certain status flags. With\nsparse irqs that requires a lookup of the irq descriptor. Add a state\nfield which contains such flags.\n\nName it in a way which will make coders happy to access it with the\nproper accessor functions. And it\u0027s easy to grep for.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "c531e8361f1968d664e6e97fbd3bfa4cf0e62e42", "tree": "45b5dbd85203033af684a9588224044289236b0c", "parents": [ "6e40262ea43c4b0e3f435b3a083e4461ef921c17" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Tue Feb 08 12:44:58 2011 +0100" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sat Feb 19 12:58:18 2011 +0100" }, "message": "genirq: Move IRQ_SUSPENDED to core\n\nNo users outside of core.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "6e40262ea43c4b0e3f435b3a083e4461ef921c17", "tree": "4548c1607f81701b77c0d63b544096cdee8ccde0", "parents": [ "2a0d6fb335d4428285dab2d254911748e6040807" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Tue Feb 08 12:36:06 2011 +0100" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sat Feb 19 12:58:17 2011 +0100" }, "message": "genirq: Move IRQ_MASKED to core\n\nKeep status in sync until all users are fixed.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "2a0d6fb335d4428285dab2d254911748e6040807", "tree": "16090086899df6886436b89cc76e6d0d5b36d083", "parents": [ "c1594b77e46124bb462f961e536120e471c67446" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Tue Feb 08 12:17:57 2011 +0100" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sat Feb 19 12:58:17 2011 +0100" }, "message": "genirq: Move IRQ_PENDING flag to core\n\nKeep status in sync until all users are fixed.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "c1594b77e46124bb462f961e536120e471c67446", "tree": "3f52ad5809125ab5be6db1fd4b1212fe6127df66", "parents": [ "163ef3091195f514a06f064b12914597d2644c55" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Mon Feb 07 22:11:30 2011 +0100" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sat Feb 19 12:58:17 2011 +0100" }, "message": "genirq: Move IRQ_DISABLED to core\n\nKeep status in sync until all abusers are fixed.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "163ef3091195f514a06f064b12914597d2644c55", "tree": "a6e222b1a7366aa93c884257063aa36ef17cf91f", "parents": [ "3d67baec7f1b01fc289ac1a2f1a7e6d5e43391c6" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Tue Feb 08 11:39:15 2011 +0100" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sat Feb 19 12:58:16 2011 +0100" }, "message": "genirq: Move IRQ_REPLAY and IRQ_WAITING to core\n\nNo users outside of core.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "3d67baec7f1b01fc289ac1a2f1a7e6d5e43391c6", "tree": "f496998278faa653174e185924acb0c74ac2e1b2", "parents": [ "009b4c3b8ad584b3462734127a5bec680d5d6af4" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Mon Feb 07 21:02:10 2011 +0100" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sat Feb 19 12:58:16 2011 +0100" }, "message": "genirq: Move IRQ_ONESHOT to core\n\nNo users outside of core.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "009b4c3b8ad584b3462734127a5bec680d5d6af4", "tree": "f7cb860dde86ba96afcc085ec7a75ca2a41e49b6", "parents": [ "6954b75b488dd740950573f244ddd66fd28620aa" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Mon Feb 07 21:48:49 2011 +0100" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sat Feb 19 12:58:16 2011 +0100" }, "message": "genirq: Add IRQ_INPROGRESS to core\n\nWe need to maintain the flag for now in both fields status and istate.\nAdd a CONFIG_GENERIC_HARDIRQS_NO_COMPAT switch to allow testing w/o\nthe status one. Wrap the access to status IRQ_INPROGRESS in a inline\nwhich can be turned of with CONFIG_GENERIC_HARDIRQS_NO_COMPAT along\nwith the define.\n\nThere is no reason that anything outside of core looks at this. That\nneeds some modifications, but we\u0027ll get there.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "6954b75b488dd740950573f244ddd66fd28620aa", "tree": "66a423d8d09c19d428e3e73373944a826f31f38e", "parents": [ "6f91a52d9bb28396177662f1da0f2e2cef9cf5d0" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Mon Feb 07 20:55:35 2011 +0100" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sat Feb 19 12:58:15 2011 +0100" }, "message": "genirq: Move IRQ_POLL_INPROGRESS to core\n\nNo users outside of core.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "6f91a52d9bb28396177662f1da0f2e2cef9cf5d0", "tree": "0be983e2d1c1a622716cff61354f02e85ef3352e", "parents": [ "7acdd53e5b2c55b6f7e3427e85e2f91fa814a4f9" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Mon Feb 14 13:33:16 2011 +0100" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sat Feb 19 12:58:15 2011 +0100" }, "message": "genirq: Use modify_status for set_irq_nested_thread\n\nNo need for a separate function in the core code.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "7acdd53e5b2c55b6f7e3427e85e2f91fa814a4f9", "tree": "4806536bae32605a3107d6c4384547693eda566c", "parents": [ "bd062e7667ac173afef57fbfe9327f3b914a9d4c" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Mon Feb 07 20:40:54 2011 +0100" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sat Feb 19 12:58:15 2011 +0100" }, "message": "genirq: Move IRQ_SPURIOUS_DISABLED to core state\n\nNo users outside.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "bd062e7667ac173afef57fbfe9327f3b914a9d4c", "tree": "29e798cb397311abec53ad45b73efdede1fc37b7", "parents": [ "e6bea9c404699223322d7411c6f2ceaec02fa83c" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Mon Feb 07 20:25:25 2011 +0100" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sat Feb 19 12:58:15 2011 +0100" }, "message": "genirq: Move IRQ_AUTODETECT to internal state\n\nNo users outside of core\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "fe200ae48ef5c79bf7941fe8046ff9505c570ff6", "tree": "767d2cf011437a266a655ce2ec39360cb85f7f28", "parents": [ "d05c65fff0ef672be75429266751f0e015b54d94" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Mon Feb 07 10:34:30 2011 +0100" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sat Feb 19 12:58:09 2011 +0100" }, "message": "genirq: Mark polled irqs and defer the real handler\n\nWith the chip.end() function gone we might run into a situation where\na poll call runs and the real interrupt comes in, sees IRQ_INPROGRESS\nand disables the line. That might be a perfect working one, which will\nthen be masked forever.\n\nSo mark them polled while the poll runs. When the real handler sees\nIRQ_INPROGRESS it checks the poll flag and waits for the polling to\ncomplete. Add the necessary amount of sanity checks to it to avoid\ndeadlocks.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "3b8249e759c701c4a82f99d957be651a7657bf6f", "tree": "f758675da3bb37282eefd50e57456d09b208b452", "parents": [ "569bda8df11effa03e618729293c7961696abb10" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Mon Feb 07 16:02:20 2011 +0100" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sat Feb 19 12:58:07 2011 +0100" }, "message": "genirq: Do not copy affinity before set\n\nWhile rumaging through arch code I found that there are a few\nworkarounds which deal with the fact that the initial affinity setting\nfrom request_irq() copies the mask into irq_data-\u003eaffinity before the\nchip code is called. In the normal path we unconditionally copy the\nmask when the chip code returns 0.\n\nCopy after the code is called and add a return code\nIRQ_SET_MASK_OK_NOCOPY for the chip functions, which prevents the\ncopy. That way we see the real mask when the chip function decided to\ntruncate it further as some arches do. IRQ_SET_MASK_OK is 0, which is\nthe current behaviour.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "a0cd9ca2b907d7ee26575e7b63ac92dad768a75e", "tree": "4b46f7951b9cd76531caf6d4d68d687e1b622336", "parents": [ "43abe43ce0619d744c7a5bb15cce075e532b53b7" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Thu Feb 10 11:36:33 2011 +0100" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sat Feb 19 12:58:06 2011 +0100" }, "message": "genirq: Namespace cleanup\n\nThe irq namespace has become quite convoluted. My bad. Clean it up\nand deprecate the old functions. All new functions follow the scheme:\n\nirq number based:\n irq_set/get/xxx/_xxx(unsigned int irq, ...)\n\nirq_data based:\n\t irq_data_set/get/xxx/_xxx(struct irq_data *d, ....)\n\nirq_desc based:\n\t irq_desc_get_xxx(struct irq_desc *desc)\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "872434d69c644b8aa5088b835598dc3cd9832aff", "tree": "82f55a0ff9ed1fc9eb814fb80dfb5e605f47e07a", "parents": [ "44f2c5c841da1b1e0864d768197ab1497b5c2cc1" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sat Feb 05 16:25:25 2011 +0100" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Sat Feb 05 16:33:56 2011 +0100" }, "message": "genirq: Add missing status flags to modification mask\n\nThe mask which filters out the valid bits which can be set via\nirq_modify_status() is missing IRQ_NO_BALANCING, which breaks UV.\n\nAdd IRQ_PER_CPU as well to avoid another one line patch for 39.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "639bd12f778d55a2632fde5af7d0719abc1871b9", "tree": "cb065e0919d261e5b8faffe34edb948967a5e7e5", "parents": [ "2656c36699677238edc9ec1fea79039f1fddbcb6" ], "author": { "name": "Paul Mundt", "email": "lethal@linux-sh.org", "time": "Tue Oct 26 16:19:13 2010 +0900" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Tue Oct 26 10:33:27 2010 +0200" }, "message": "genirq: Add single IRQ reservation helper\n\nFor cases that wish to reserve a single IRQ at a given place simply\nprovide a wrapper in to the ranged reservation routine.\n\nSigned-off-by: Paul Mundt \u003clethal@linux-sh.org\u003e\nLKML-Reference: \u003c20101026071912.GD4733@linux-sh.org\u003e\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n\n" }, { "commit": "b7b29338dc7111ed8bd4d6555d84afae13ebe752", "tree": "4c3159ea8bb0489ba463a061d3e6446dbfb45af2", "parents": [ "b7d0d8258a9f71949b810e0f82a3d75088f4d364" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Wed Sep 29 18:46:55 2010 +0200" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Tue Oct 12 16:53:44 2010 +0200" }, "message": "genirq: Sanitize dynamic irq handling\n\nUse the cleanup functions of the dynamic allocator. No need to have\nseparate implementations.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nReviewed-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "10ba1e0eeef6a3c9453d96364e28cb4d911e1ac3", "tree": "c535feadce8d57e5e96f401e156617c7e9ab4237", "parents": [ "1a0730d6649113c820217387a011a17dd4aff3ad" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Mon Oct 11 12:21:18 2010 +0200" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Tue Oct 12 16:53:43 2010 +0200" }, "message": "genirq: Remove irq_2_iommu\n\nirq_2_iommu is now in the x86 code where it belongs. Remove all\nleftovers.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nReviewed-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nAcked-by: Suresh Siddha \u003csuresh.b.siddha@intel.com\u003e\nCc: David Woodhouse \u003cdwmw2@infradead.org\u003e\nCc: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "b683de2b3cb17bb10fa6fd4af614dc75b5749fe0", "tree": "e1a799293b218f5c13d4903c57fab144b2f433b3", "parents": [ "aa99ec0f3f26bf2bcd0fa5176de93598427f1e5e" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Mon Sep 27 20:55:03 2010 +0200" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Tue Oct 12 16:39:08 2010 +0200" }, "message": "genirq: Query arch for number of early descriptors\n\nsparse irq sets up NR_IRQS_LEGACY irq descriptors and archs then go\nahead and allocate more.\n\nUse the unused return value of arch_probe_nr_irqs() to let the\narchitecture return the number of early allocations. Fix up all users.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nReviewed-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "06f6c3399e9f9ff6eafc200e80f9226c3cee0eaf", "tree": "f4d8fc67194b1a50bfe501634088b3776ca6bbd4", "parents": [ "a98d24b71b6e229965f18dc00d28dc71cb8fe324" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Tue Oct 12 12:31:46 2010 +0200" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Tue Oct 12 16:39:07 2010 +0200" }, "message": "genirq: Implement irq reservation\n\nMark a range of interrupts as allocated. In the SPARSE_IRQ\u003dn case we\nneed this to update the bitmap for the legacy irqs so the enumerator\nvia irq_get_next_irq() works.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "1f5a5b87f78fade3ae48dfd55e8765d1d622ea4e", "tree": "762a5dbf40129ffd9667a170b2503a77c95320f7", "parents": [ "1318a481fc37c503a901b96ae06b692ca2b21af5" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Mon Sep 27 17:48:26 2010 +0200" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Tue Oct 12 16:39:07 2010 +0200" }, "message": "genirq: Implement a sane sparse_irq allocator\n\nThe current sparse_irq allocator has several short comings due to\nfailures in the design or the lack of it:\n\n - Requires iteration over the number of active irqs to find a free slot\n (Some architectures have grown their own workarounds for this)\n - Removal of entries is not possible\n - Racy between create_irq_nr and destroy_irq (plugged by horrible\n callbacks)\n - Migration of active irq descriptors is not possible\n - No bulk allocation of irq ranges\n - Sprinkeled irq_desc references all over the place outside of kernel/irq/\n (The previous chip functions series is addressing this issue)\n\nImplement a sane allocator which fixes the above short comings (though\nmigration of active descriptors needs a full tree wide cleanup of the\ndirect and mostly unlocked access to irq_desc).\n\nThe new allocator still uses a radix_tree, but uses a bitmap for\nkeeping track of allocated irq numbers. That allows:\n\n - Fast lookup of a free slot\n - Allows the removal of descriptors\n - Prevents the create/destroy race\n - Bulk allocation of consecutive irq ranges\n - Basic design is ready for migration of life descriptors after\n further cleanups\n\nThe bitmap is also used in the SPARSE_IRQ\u003dn case for lookup and\nraceless (de)allocation of irq numbers. So it removes the requirement\nfor looping through the descriptor array to find slots.\n\nRight now it uses sparse_irq_lock to protect the bitmap and the radix\ntree, but after cleaning up all users we should be able convert that\nto a mutex and to switch the radix_tree and decriptor allocations to\nGFP_KERNEL.\n\n[ Folded in a bugfix from Yinghai Lu ]\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nReviewed-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "1318a481fc37c503a901b96ae06b692ca2b21af5", "tree": "2b1bb8f52af5938759af38efdfa8a868b02d5804", "parents": [ "d895f51ebb54cefe367bda135fcf2cd734d51d03" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Mon Sep 27 21:01:37 2010 +0200" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Tue Oct 12 16:39:06 2010 +0200" }, "message": "genirq: Provide default irq init flags\n\nArch code sets it\u0027s own irq_desc.status flags right after boot and for\ndynamically allocated interrupts. That might involve iterating over a\nhuge array.\n\nAllow ARCH_IRQ_INIT_FLAGS to set separate flags aside of IRQ_DISABLED\nwhich is the default.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nReviewed-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "f303a6dd127b5ec6de90d1cd79ed19820c7e9658", "tree": "8060ccc63ab56406e6a9535b21cca29f17956052", "parents": [ "442471848f5abb55b99cba1229301655f67492b4" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Tue Sep 28 17:34:01 2010 +0200" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Tue Oct 12 16:39:05 2010 +0200" }, "message": "genirq: Sanitize irq_data accessors\n\nGet the data structure from the core and provide inline wrappers to\naccess the irq_data members.\n\nProvide accessor inlines for irq_data as well.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nReviewed-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "442471848f5abb55b99cba1229301655f67492b4", "tree": "4265a98a62db515d2b0a63d95a7c7e5badb1dbc0", "parents": [ "3a3856d00c74560a7b8d9f8a13c1ca94ee786b78" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Tue Sep 28 10:40:18 2010 +0200" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Tue Oct 12 16:39:05 2010 +0200" }, "message": "genirq: Provide status modifier\n\nProvide a irq_desc.status modifier function to cleanup the direct\naccess to irq_desc in arch and driver code.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nReviewed-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n\n" }, { "commit": "3a3856d00c74560a7b8d9f8a13c1ca94ee786b78", "tree": "c161c40e8c443547d936e276689587bd340da855", "parents": [ "e144710b302525de5b90b9c3ba43562458d8957f" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Mon Oct 04 13:47:12 2010 +0200" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Tue Oct 12 16:39:05 2010 +0200" }, "message": "genirq: Remove unsused inline\n\nmove_irq() has no users. Remove it and simplify the ifdef forrest while at it.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nReviewed-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "e144710b302525de5b90b9c3ba43562458d8957f", "tree": "0a6ef61ccb4957512ebf4a1887ba3bc54e78f99e", "parents": [ "fe21221386e46b8e0f2cbd83559a29680c28473b" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Fri Oct 01 16:03:45 2010 +0200" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Tue Oct 12 16:39:04 2010 +0200" }, "message": "genirq: Distangle irq.h\n\nMove irq_desc and internal functions out of irq.h\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nReviewed-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "bd151412263a67b5321e9dd1d5b4bf6d96fdebf3", "tree": "7571b3eaf7ebc2ef200fb00688543f00a451c5f9", "parents": [ "21e2b8c62cca8f7dbec0c8c131ca1637e4a5670f" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Fri Oct 01 15:17:14 2010 +0200" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Mon Oct 04 13:40:24 2010 +0200" }, "message": "genirq: Provide config option to disable deprecated code\n\nThis option covers now the old chip functions and the irq_desc data\nfields which are moving to struct irq_data. More stuff will follow.\n\nPretty handy for testing a conversion, whether something broke or not.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nReviewed-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "f8822657e799b02c55556c99a601261e207a299d", "tree": "5a263bd4df600d7b090d1216e2b8462c121a7588", "parents": [ "6b8ff3120c758340505dddf08ad685ebb841d5d5" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Mon Sep 27 12:44:32 2010 +0000" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Mon Oct 04 12:43:32 2010 +0200" }, "message": "genirq: Provide advanced irq chip functions\n\nThe low level irq chip functions want access to irq_desc-\u003eirq_data.\nProvide new functions which hand down irq_data instead of the irq\nnumber so these functions avoid to call irq_to_desc() which is a radix\ntree lookup in case of sparse irq.\n\nThis provides all the old functions except one: end(). end() is a\nrelict of __do_IRQ() and will just go away with the __do_IRQ() code.\n\nThe replacement for set_affinity() has an extra argument \"bool\nforce\". The reason for this is to notify the low level code, that the\nmove has to be done right away and cannot be delayed until the next\ninterrupt happens. That\u0027s necessary to handle the irq fixup on cpu\nunplug in the generic code.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nCc: Peter Zijlstra \u003cpeterz@infradead.org\u003e\nLKML-Reference: \u003c20100927121841.742126604@linutronix.de\u003e\nReviewed-by: H. Peter Anvin \u003chpa@zytor.com\u003e\nReviewed-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "6b8ff3120c758340505dddf08ad685ebb841d5d5", "tree": "794eed27c6f9a8931b8fdf4a7ae60a1560b237fc", "parents": [ "ff7dcd44dd446db2c3e13bdedf2d52b8e0127f16" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Fri Oct 01 12:58:38 2010 +0200" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Mon Oct 04 12:36:26 2010 +0200" }, "message": "genirq: Convert core code to irq_data\n\nConvert all references in the core code to orq, chip, handler_data,\nchip_data, msi_desc, affinity to irq_data.*\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nReviewed-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "ff7dcd44dd446db2c3e13bdedf2d52b8e0127f16", "tree": "ca03e829ea08aa536124a7777d99233dbbd89984", "parents": [ "3bb9808e99bcc36eecb8e082bf70efb2a0bcdcb7" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Mon Sep 27 12:44:25 2010 +0000" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Mon Oct 04 12:27:16 2010 +0200" }, "message": "genirq: Create irq_data\n\nLow level chip functions need access to irq_desc-\u003ehandler_data,\nirq_desc-\u003echip_data and irq_desc-\u003emsi_desc. We hand down the irq\nnumber to the low level functions, so they need to lookup irq_desc.\nWith sparse irq this means a radix tree lookup.\n\nWe could hand down irq_desc itself, but low level chip functions have\nno need to fiddle with it directly and we want to restrict access to\nirq_desc further.\n\nPreparatory patch for new chip functions.\n\nNote, that the ugly anon union/struct is there to avoid a full tree\nwide clean up for now. This is not going to last 3 years like __do_IRQ()\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nCc: Peter Zijlstra \u003cpeterz@infradead.org\u003e\nLKML-Reference: \u003c20100927121841.645542300@linutronix.de\u003e\nReviewed-by: H. Peter Anvin \u003chpa@zytor.com\u003e\nReviewed-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "d1ea13c6e2cce0106531852daaa93dd97aec9580", "tree": "9a49b1029af4e63e08267d2b4d6e2f66396be0aa", "parents": [ "a800c7cc5380fbb6b4f2f3bd89f6776eb3da2242" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Thu Sep 23 18:40:07 2010 +0200" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Thu Sep 23 19:12:26 2010 +0200" }, "message": "genirq: Cleanup irq_chip-\u003etypename leftovers\n\n3 years transition phase is enough. Cleanup the last users and remove\nthe cruft.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nCc: Leo Chen \u003cleochen@broadcom.com\u003e\nCc: Hirokazu Takata \u003ctakata@linux-m32r.org\u003e\nCc: Chris Metcalf \u003ccmetcalf@tilera.com\u003e\nCc: Jeff Dike \u003cjdike@addtoit.com\u003e\nCc: Chris Zankel \u003cchris@zankel.net\u003e\n" }, { "commit": "e7a297b0d7d6049bd4e423ac1e17da31e4c401b8", "tree": "f10f12806a637b09bec89ef5428d981c4c1a4bc9", "parents": [ "6932bf37bed45ce8ed531928b1b0f98162fe6df6" ], "author": { "name": "Peter P Waskiewicz Jr", "email": "peter.p.waskiewicz.jr@intel.com", "time": "Fri Apr 30 14:44:50 2010 -0700" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Mon May 03 11:50:57 2010 +0200" }, "message": "genirq: Add CPU mask affinity hint\n\nThis patch adds a cpumask affinity hint to the irq_desc structure,\nalong with a registration function and a read-only proc entry for each\ninterrupt.\n\nThis affinity_hint handle for each interrupt can be used by underlying\ndrivers that need a better mechanism to control interrupt affinity.\nThe underlying driver can register a cpumask for the interrupt, which\nwill allow the driver to provide the CPU mask for the interrupt to\nanything that requests it. The intent is to extend the userspace\ndaemon, irqbalance, to help hint to it a preferred CPU mask to balance\nthe interrupt into.\n\n[ tglx: Fixed compile warnings, added WARN_ON, made SMP only ]\n\nSigned-off-by: Peter P Waskiewicz Jr \u003cpeter.p.waskiewicz.jr@intel.com\u003e\nCc: davem@davemloft.net\nCc: arjan@linux.jf.intel.com\nCc: bhutchings@solarflare.com\nLKML-Reference: \u003c20100430214445.3992.41647.stgit@ppwaskie-hc2.jf.intel.com\u003e\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "fb7b096d949fa852442ed9d8f982bce526ccfe7e", "tree": "883e7e43331d9962bcc6050a3bf88615a8c61063", "parents": [ "a626b46e17d0762d664ce471d40bc506b6e721ab", "fad539956c9e69749a03f7817d22d1bab87657bf" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Mar 03 08:15:37 2010 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Mar 03 08:15:37 2010 -0800" }, "message": "Merge branch \u0027x86-apic-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip\n\n* \u0027x86-apic-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (25 commits)\n x86: Fix out of order of gsi\n x86: apic: Fix mismerge, add arch_probe_nr_irqs() again\n x86, irq: Keep chip_data in create_irq_nr and destroy_irq\n xen: Remove unnecessary arch specific xen irq functions.\n smp: Use nr_cpus\u003d to set nr_cpu_ids early\n x86, irq: Remove arch_probe_nr_irqs\n sparseirq: Use radix_tree instead of ptrs array\n sparseirq: Change irq_desc_ptrs to static\n init: Move radix_tree_init() early\n irq: Remove unnecessary bootmem code\n x86: Add iMac9,1 to pci_reboot_dmi_table\n x86: Convert i8259_lock to raw_spinlock\n x86: Convert nmi_lock to raw_spinlock\n x86: Convert ioapic_lock and vector_lock to raw_spinlock\n x86: Avoid race condition in pci_enable_msix()\n x86: Fix SCI on IOAPIC !\u003d 0\n x86, ia32_aout: do not kill argument mapping\n x86, irq: Move __setup_vector_irq() before the first irq enable in cpu online path\n x86, irq: Update the vector domain for legacy irqs handled by io-apic\n x86, irq: Don\u0027t block IRQ0_VECTOR..IRQ15_VECTOR\u0027s on all cpu\u0027s\n ...\n" }, { "commit": "ced5b697a76d325e7a7ac7d382dbbb632c765093", "tree": "1a0a56d4415afcd16d034aa3bc5c0a6ba06c8a52", "parents": [ "e28cab42f384745c8a947a9ccd51e4aae52f5d51" ], "author": { "name": "Brandon Phiilps", "email": "bphilips@suse.de", "time": "Wed Feb 10 01:20:06 2010 -0800" }, "committer": { "name": "H. Peter Anvin", "email": "hpa@zytor.com", "time": "Wed Feb 10 14:27:28 2010 -0800" }, "message": "x86: Avoid race condition in pci_enable_msix()\n\nKeep chip_data in create_irq_nr and destroy_irq.\n\nWhen two drivers are setting up MSI-X at the same time via\npci_enable_msix() there is a race. See this dmesg excerpt:\n\n[ 85.170610] ixgbe 0000:02:00.1: irq 97 for MSI/MSI-X\n[ 85.170611] alloc irq_desc for 99 on node -1\n[ 85.170613] igb 0000:08:00.1: irq 98 for MSI/MSI-X\n[ 85.170614] alloc kstat_irqs on node -1\n[ 85.170616] alloc irq_2_iommu on node -1\n[ 85.170617] alloc irq_desc for 100 on node -1\n[ 85.170619] alloc kstat_irqs on node -1\n[ 85.170621] alloc irq_2_iommu on node -1\n[ 85.170625] ixgbe 0000:02:00.1: irq 99 for MSI/MSI-X\n[ 85.170626] alloc irq_desc for 101 on node -1\n[ 85.170628] igb 0000:08:00.1: irq 100 for MSI/MSI-X\n[ 85.170630] alloc kstat_irqs on node -1\n[ 85.170631] alloc irq_2_iommu on node -1\n[ 85.170635] alloc irq_desc for 102 on node -1\n[ 85.170636] alloc kstat_irqs on node -1\n[ 85.170639] alloc irq_2_iommu on node -1\n[ 85.170646] BUG: unable to handle kernel NULL pointer dereference\nat 0000000000000088\n\nAs you can see igb and ixgbe are both alternating on create_irq_nr()\nvia pci_enable_msix() in their probe function.\n\nixgbe: While looping through irq_desc_ptrs[] via create_irq_nr() ixgbe\nchoses irq_desc_ptrs[102] and exits the loop, drops vector_lock and\ncalls dynamic_irq_init. Then it sets irq_desc_ptrs[102]-\u003echip_data \u003d\nNULL via dynamic_irq_init().\n\nigb: Grabs the vector_lock now and starts looping over irq_desc_ptrs[]\nvia create_irq_nr(). It gets to irq_desc_ptrs[102] and does this:\n\n\tcfg_new \u003d irq_desc_ptrs[102]-\u003echip_data;\n\tif (cfg_new-\u003evector !\u003d 0)\n\t\tcontinue;\n\nThis hits the NULL deref.\n\nAnother possible race exists via pci_disable_msix() in a driver or in\nthe number of error paths that call free_msi_irqs():\n\ndestroy_irq()\ndynamic_irq_cleanup() which sets desc-\u003echip_data \u003d NULL\n...race window...\ndesc-\u003echip_data \u003d cfg;\n\nRemove the save and restore code for cfg in create_irq_nr() and\ndestroy_irq() and take the desc-\u003elock when checking the irq_cfg.\n\nReported-and-analyzed-by: Brandon Philips \u003cbphilips@suse.de\u003e\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nLKML-Reference: \u003c1265793639-15071-3-git-send-email-yinghai@kernel.org\u003e\nSigned-off-by: Brandon Phililps \u003cbphilips@suse.de\u003e\nCc: stable@kernel.org\nSigned-off-by: H. Peter Anvin \u003chpa@zytor.com\u003e\n" }, { "commit": "599faa0e264fe2e7f563f87b4aad8c83e9dc46d1", "tree": "6800280e4f882709767d30e1e5329b4e507e74f6", "parents": [ "7284ce6c9f6153d1777df5f310c959724d1bd446" ], "author": { "name": "Mark Brown", "email": "broonie@opensource.wolfsonmicro.com", "time": "Tue Jan 05 13:29:58 2010 +0000" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Wed Jan 13 11:14:18 2010 +0100" }, "message": "genirq: Fix documentation of default chip disable()\n\nThe documentation says that by default disable() will be\nchip-\u003emask but in fact default_disable() is a noop.\n\nSigned-off-by: Mark Brown \u003cbroonie@opensource.wolfsonmicro.com\u003e\nLKML-Reference: \u003c1262698198-30392-1-git-send-email-broonie@opensource.wolfsonmicro.com\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "239007b8440abff689632f50cdf0f2b9e895b534", "tree": "569cab843af4a999d6d868ec9a824530d2bfa733", "parents": [ "9f5a5621e78cf48d86682a71ceb3fcdbde38b222" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Tue Nov 17 16:46:45 2009 +0100" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Mon Dec 14 23:55:33 2009 +0100" }, "message": "genirq: Convert irq_desc.lock to raw_spinlock\n\nConvert locks which cannot be sleeping locks in preempt-rt to\nraw_spinlocks.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nAcked-by: Peter Zijlstra \u003cpeterz@infradead.org\u003e\nAcked-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" } ], "next": "bebd04cc4569844effbdae49c01a48e57fa77864" }