)]}' { "log": [ { "commit": "b4b50fd78b1e31989940dfc647e64453d0f7176a", "tree": "1a55f110e021c02963b63759f3f18ea7ba3aa228", "parents": [ "dccfd1e439c11422d7aca0d834b0430d24650e85", "f97c43bbdf8a1ea42477b1a804a48e7e368cb13c" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Sep 06 13:30:06 2013 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Sep 06 13:30:06 2013 -0700" }, "message": "Merge tag \u0027soc-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc\n\nPull ARM SoC platform changes from Olof Johansson:\n \"This branch contains mostly additions and changes to platform\n enablement and SoC-level drivers. Since there\u0027s sometimes a\n dependency on device-tree changes, there\u0027s also a fair amount of\n those in this branch.\n\n Pieces worth mentioning are:\n\n - Mbus driver for Marvell platforms, allowing kernel configuration\n and resource allocation of on-chip peripherals.\n - Enablement of the mbus infrastructure from Marvell PCI-e drivers.\n - Preparation of MSI support for Marvell platforms.\n - Addition of new PCI-e host controller driver for Tegra platforms\n - Some churn caused by sharing of macro names between i.MX 6Q and 6DL\n platforms in the device tree sources and header files.\n - Various suspend/PM updates for Tegra, including LP1 support.\n - Versatile Express support for MCPM, part of big little support.\n - Allwinner platform support for A20 and A31 SoCs (dual and quad\n Cortex-A7)\n - OMAP2+ support for DRA7, a new Cortex-A15-based SoC.\n\n The code that touches other architectures are patches moving MSI\n arch-specific functions over to weak symbols and removal of\n ARCH_SUPPORTS_MSI, acked by PCI maintainers\"\n\n* tag \u0027soc-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (266 commits)\n tegra-cpuidle: provide stub when !CONFIG_CPU_IDLE\n PCI: tegra: replace devm_request_and_ioremap by devm_ioremap_resource\n ARM: tegra: Drop ARCH_SUPPORTS_MSI and sort list\n ARM: dts: vf610-twr: enable i2c0 device\n ARM: dts: i.MX51: Add one more I2C2 pinmux entry\n ARM: dts: i.MX51: Move pins configuration under \"iomuxc\" label\n ARM: dtsi: imx6qdl-sabresd: Add USB OTG vbus pin to pinctrl_hog\n ARM: dtsi: imx6qdl-sabresd: Add USB host 1 VBUS regulator\n ARM: dts: imx27-phytec-phycore-som: Enable AUDMUX\n ARM: dts: i.MX27: Disable AUDMUX in the template\n ARM: dts: wandboard: Add support for SDIO bcm4329\n ARM: i.MX5 clocks: Remove optional clock setup (CKIH1) from i.MX51 template\n ARM: dts: imx53-qsb: Make USBH1 functional\n ARM i.MX6Q: dts: Enable I2C1 with EEPROM and PMIC on Phytec phyFLEX-i.MX6 Ouad module\n ARM i.MX6Q: dts: Enable SPI NOR flash on Phytec phyFLEX-i.MX6 Ouad module\n ARM: dts: imx6qdl-sabresd: Add touchscreen support\n ARM: imx: add ocram clock for imx53\n ARM: dts: imx: ocram size is different between imx6q and imx6dl\n ARM: dts: imx27-phytec-phycore-som: Fix regulator settings\n ARM: dts: i.MX27: Remove clock name from CPU node\n ...\n" }, { "commit": "cc998ff8811530be521f6b316f37ab7676a07938", "tree": "a054b3bf4b2ef406bf756a6cfc9be2f9115f17ae", "parents": [ "57d730924d5cc2c3e280af16a9306587c3a511db", "0d40f75bdab241868c0eb6f97aef9f8b3a66f7b3" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Sep 05 14:54:29 2013 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Sep 05 14:54:29 2013 -0700" }, "message": "Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next\n\nPull networking changes from David Miller:\n \"Noteworthy changes this time around:\n\n 1) Multicast rejoin support for team driver, from Jiri Pirko.\n\n 2) Centralize and simplify TCP RTT measurement handling in order to\n reduce the impact of bad RTO seeding from SYN/ACKs. Also, when\n both timestamps and local RTT measurements are available prefer\n the later because there are broken middleware devices which\n scramble the timestamp.\n\n From Yuchung Cheng.\n\n 3) Add TCP_NOTSENT_LOWAT socket option to limit the amount of kernel\n memory consumed to queue up unsend user data. From Eric Dumazet.\n\n 4) Add a \"physical port ID\" abstraction for network devices, from\n Jiri Pirko.\n\n 5) Add a \"suppress\" operation to influence fib_rules lookups, from\n Stefan Tomanek.\n\n 6) Add a networking development FAQ, from Paul Gortmaker.\n\n 7) Extend the information provided by tcp_probe and add ipv6 support,\n from Daniel Borkmann.\n\n 8) Use RCU locking more extensively in openvswitch data paths, from\n Pravin B Shelar.\n\n 9) Add SCTP support to openvswitch, from Joe Stringer.\n\n 10) Add EF10 chip support to SFC driver, from Ben Hutchings.\n\n 11) Add new SYNPROXY netfilter target, from Patrick McHardy.\n\n 12) Compute a rate approximation for sending in TCP sockets, and use\n this to more intelligently coalesce TSO frames. Furthermore, add\n a new packet scheduler which takes advantage of this estimate when\n available. From Eric Dumazet.\n\n 13) Allow AF_PACKET fanouts with random selection, from Daniel\n Borkmann.\n\n 14) Add ipv6 support to vxlan driver, from Cong Wang\"\n\nResolved conflicts as per discussion.\n\n* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next: (1218 commits)\n openvswitch: Fix alignment of struct sw_flow_key.\n netfilter: Fix build errors with xt_socket.c\n tcp: Add missing braces to do_tcp_setsockopt\n caif: Add missing braces to multiline if in cfctrl_linkup_request\n bnx2x: Add missing braces in bnx2x:bnx2x_link_initialize\n vxlan: Fix kernel panic on device delete.\n net: mvneta: implement -\u003endo_do_ioctl() to support PHY ioctls\n net: mvneta: properly disable HW PHY polling and ensure adjust_link() works\n icplus: Use netif_running to determine device state\n ethernet/arc/arc_emac: Fix huge delays in large file copies\n tuntap: orphan frags before trying to set tx timestamp\n tuntap: purge socket error queue on detach\n qlcnic: use standard NAPI weights\n ipv6:introduce function to find route for redirect\n bnx2x: VF RSS support - VF side\n bnx2x: VF RSS support - PF side\n vxlan: Notify drivers for listening UDP port changes\n net: usbnet: update addr_assign_type if appropriate\n driver/net: enic: update enic maintainers and driver\n driver/net: enic: Exposing symbols for Cisco\u0027s low latency driver\n ...\n" }, { "commit": "2e8b5f621dbe29425906852c6079afb6b28720cb", "tree": "178a58a6dee0599d8b119d6c72969f9b6f4e37ac", "parents": [ "07f2daad094bc9e9770143cd2d619de24d84bb3e", "fed2451512495f0f0820ac9e53936bd208569bc8" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Wed Aug 28 20:55:41 2013 -0600" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Wed Aug 28 20:55:41 2013 -0600" }, "message": "Merge branch \u0027pci/misc\u0027 into next\n\n* pci/misc:\n PCI: Remove pcie_cap_has_devctl()\n PCI: Support PCIe Capability Slot registers only for ports with slots\n PCI: Remove PCIe Capability version checks\n PCI: Allow PCIe Capability link-related register access for switches\n PCI: Add offsets of PCIe capability registers\n PCI: Tidy bitmasks and spacing of PCIe capability definitions\n PCI: Remove obsolete comment reference to pci_pcie_cap2()\n PCI: Clarify PCI_EXP_TYPE_PCI_BRIDGE comment\n PCI: Rename PCIe capability definitions to follow convention\n PCI: Disable decoding for BAR sizing only when it was actually enabled\n PCI: Add comment about needing pci_msi_off() even when CONFIG_PCI_MSI\u003dn\n PCI: Add pcibios_pm_ops for optional arch-specific hibernate functionality\n" }, { "commit": "07f2daad094bc9e9770143cd2d619de24d84bb3e", "tree": "202f930177f85456a129cfb3f7b5abc9615d52a4", "parents": [ "1193725f543c92a77c73769bc2fbe48c53275f53", "5895af79158a55562753f7f05762f3bd766d32b9" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Mon Aug 26 15:40:34 2013 -0600" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Mon Aug 26 15:40:34 2013 -0600" }, "message": "Merge branch \u0027pci/yijing-mps-v8\u0027 into next\n\n* pci/yijing-mps-v8:\n PCI: Warn if unsafe MPS settings detected\n PCI: Fix MPS peer-to-peer DMA comment syntax\n PCI: Don\u0027t restrict MPS for slots below Root Ports\n PCI: Simplify MPS test for Downstream Port\n PCI: Remove unnecessary check for pcie_get_mps() failure\n PCI: Simplify pcie_bus_configure_settings() interface\n PCI: Drop \"PCI-E\" prefix from Max Payload Size message\n" }, { "commit": "1193725f543c92a77c73769bc2fbe48c53275f53", "tree": "71ef007260a1584f4f48d7a7118a3157d01eb5f7", "parents": [ "7d8c4a2c5ae6d76f1142fb052d698b3c40ce518c", "39772038ea93e85ea4f1307ec9c1f48a063d89a0" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Mon Aug 26 15:40:03 2013 -0600" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Mon Aug 26 15:40:03 2013 -0600" }, "message": "Merge branch \u0027pci/yinghai-assign-unassigned-v6\u0027 into next\n\n* pci/yinghai-assign-unassigned-v6:\n PCI: Assign resources for hot-added host bridge more aggressively\n PCI: Move resource reallocation code to non-__init\n PCI: Delay enabling bridges until they\u0027re needed\n PCI: Assign resources on a per-bus basis\n PCI: Enable unassigned resource reallocation on per-bus basis\n PCI: Turn on reallocation for unassigned resources with host bridge offset\n PCI: Look for unassigned resources on per-bus basis\n PCI: Drop temporary variable in pci_assign_unassigned_resources()\n" }, { "commit": "699c1985587aad3432c5ae19801efb4186db8b7a", "tree": "fe169fdbf3111a1ce264115da81b30837adf6079", "parents": [ "4b1ced841b2e31470ae4bb47988891754ce4d8c7" ], "author": { "name": "Sebastian Ott", "email": "sebott@linux.vnet.ibm.com", "time": "Tue Aug 20 16:41:02 2013 +0200" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Thu Aug 22 14:11:32 2013 -0600" }, "message": "PCI: Add pcibios_pm_ops for optional arch-specific hibernate functionality\n\nPlatforms may want to provide architecture-specific functionality when\na PCI device is doing a hibernate transition. Add a weak symbol\npcibios_pm_ops that architectures can override to do so.\n\n[bhelgaas: fold in return value checks from v2 patch]\nSigned-off-by: Sebastian Ott \u003csebott@linux.vnet.ibm.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "a58674ff8383f5b8f6a77f03c48f6a47840b9325", "tree": "b07c7f08dc3bd929131d6dc164d27cf8c0903cff", "parents": [ "2c25e34c7531ca1849b85cbcdb5a2f507ffe240c" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Thu Aug 22 11:24:44 2013 +0800" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Thu Aug 22 10:47:02 2013 -0600" }, "message": "PCI: Simplify pcie_bus_configure_settings() interface\n\nBased on a patch by Jon Mason (see URL below).\n\nAll users of pcie_bus_configure_settings() pass arguments of the form\n\"bus, bus-\u003eself-\u003epcie_mpss\". The \"mpss\" argument is redundant since we\ncan easily look it up internally. In addition, all callers check\n\"bus-\u003eself\" for NULL, which we can also do internally.\n\nThis patch simplifies the interface and the callers. No functional change.\n\nReference: http://lkml.kernel.org/r/1317048850-30728-2-git-send-email-mason@myri.com\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\n" }, { "commit": "7d8c4a2c5ae6d76f1142fb052d698b3c40ce518c", "tree": "e5f4d7779bd2e6b4e9ccc3e73d5c40bb537513e8", "parents": [ "63ef41811b86432101b4627ff07c9671f93a483f", "9a3d2b9beefd5b07c1d8f70ded01b88f203ee304" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Thu Aug 15 14:41:33 2013 -0600" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Thu Aug 15 14:41:33 2013 -0600" }, "message": "Merge branch \u0027pci/aw-reset-v5\u0027 into next\n\n* pci/aw-reset-v5:\n PCI: Add pci_probe_reset_slot() and pci_probe_reset_bus()\n PCI: Remove aer_do_secondary_bus_reset()\n PCI: Tune secondary bus reset timing\n PCI: Wake-up devices before saving config space for reset\n PCI: Add pci_reset_slot() and pci_reset_bus()\n PCI: Split out pci_dev lock/unlock and save/restore\n PCI: Add slot reset option to pci_dev_reset()\n PCI: pciehp: Add reset_slot() method\n PCI: Add hotplug_slot_ops.reset_slot()\n PCI: Add pci_reset_bridge_secondary_bus()\n" }, { "commit": "9a3d2b9beefd5b07c1d8f70ded01b88f203ee304", "tree": "51aba33f4963d835195368743e31d116e3493199", "parents": [ "1b95ce8fc9c12fdb60047f2f9950f29e76e7c66d" ], "author": { "name": "Alex Williamson", "email": "alex.williamson@redhat.com", "time": "Wed Aug 14 14:06:05 2013 -0600" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Thu Aug 15 11:38:45 2013 -0600" }, "message": "PCI: Add pci_probe_reset_slot() and pci_probe_reset_bus()\n\nUsers of pci_reset_bus() and pci_reset_slot() need a way to probe\nwhether the bus or slot supports reset. Add trivial helper functions\nand export them as vfio-pci will make use of these.\n\nSigned-off-by: Alex Williamson \u003calex.williamson@redhat.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "090a3c5322e900f468b3205b76d0837003ad57b2", "tree": "8363cd8326137b871778fac3e2f2c32bb0a13f31", "parents": [ "77cb985ad4acbe66a92ead1bb826deffa47dd33f" ], "author": { "name": "Alex Williamson", "email": "alex.williamson@redhat.com", "time": "Thu Aug 08 14:09:55 2013 -0600" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Wed Aug 14 15:20:37 2013 -0600" }, "message": "PCI: Add pci_reset_slot() and pci_reset_bus()\n\nSometimes pci_reset_function() is not sufficient. We have cases where\ndevices do not support any kind of reset, but there might be multiple\nfunctions on the bus preventing pci_reset_function() from doing a\nsecondary bus reset. We also have cases where a device will advertise\nthat it supports a PM reset, but really does nothing on D3hot-\u003eD0\n(graphics cards are notorious for this). These devices often also\nhave more than one function, so even blacklisting PM reset for them\nwouldn\u0027t allow a secondary bus reset through pci_reset_function().\n\nIf a driver supports multiple devices it should have the ability to\ninduce a bus reset when it needs to. This patch provides that ability\nthrough pci_reset_slot() and pci_reset_bus(). It\u0027s the caller\u0027s\nresponsibility when using these interfaces to understand that all of\nthe devices in or below the slot (or on or below the bus) will be\nreset and therefore should be under control of the caller. PCI state\nof all the affected devices is saved and restored around these resets,\nbut internal state of all of the affected devices is reset (which\nshould be the intention).\n\nSigned-off-by: Alex Williamson \u003calex.williamson@redhat.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "3775a209d38aa3a0c7ed89a7d0f529e0230f280e", "tree": "c3d6d6e76b2ddbfba682d613b131e7341afa396e", "parents": [ "3b2f64d00c46e1e4e9bd0bb9bb12619adac27a4b" ], "author": { "name": "Casey Leedom", "email": "leedom@chelsio.com", "time": "Tue Aug 06 15:48:36 2013 +0530" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Mon Aug 12 13:47:09 2013 -0600" }, "message": "PCI: Add pci_wait_for_pending_transaction()\n\nNew routine to avoid duplication of code to wait for pending PCI\ntransactions to complete.\n\nSigned-off-by: Casey Leedom \u003cleedom@chelsio.com\u003e\nSigned-off-by: Vipul Pandya \u003cvipul@chelsio.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "0cbdcfcf427b63b9670e56760ef5e67cd7081b35", "tree": "941122e2248ac4b8dd107bc1702c83cbc0961166", "parents": [ "ebd97be635bff43239f391a49c78b98818c589fe" ], "author": { "name": "Thierry Reding", "email": "thierry.reding@avionic-design.de", "time": "Fri Aug 09 22:27:08 2013 +0200" }, "committer": { "name": "Jason Cooper", "email": "jason@lakedaemon.net", "time": "Mon Aug 12 15:26:58 2013 +0000" }, "message": "PCI: Introduce new MSI chip infrastructure\n\nThe new struct msi_chip is used to associated an MSI controller with a\nPCI bus. It is automatically handed down from the root to its children\nduring bus enumeration.\n\nThis patch provides default (weak) implementations for the architecture-\nspecific MSI functions (arch_setup_msi_irq(), arch_teardown_msi_irq()\nand arch_msi_check_device()) which check if a PCI device\u0027s bus has an\nattached MSI chip and forward the call appropriately.\n\nSigned-off-by: Thierry Reding \u003cthierry.reding@avionic-design.de\u003e\nSigned-off-by: Thomas Petazzoni \u003cthomas.petazzoni@free-electrons.com\u003e\nAcked-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\nTested-by: Daniel Price \u003cdaniel.price@gmail.com\u003e\nTested-by: Thierry Reding \u003cthierry.reding@gmail.com\u003e\nSigned-off-by: Jason Cooper \u003cjason@lakedaemon.net\u003e\n" }, { "commit": "64e8674fbe6bc848333a9b7e19f8cc019dde9eab", "tree": "43321f9f0693954f38cf4b82fc0e1da3ea267d10", "parents": [ "3b2f64d00c46e1e4e9bd0bb9bb12619adac27a4b" ], "author": { "name": "Alex Williamson", "email": "alex.williamson@redhat.com", "time": "Thu Aug 08 14:09:24 2013 -0600" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Fri Aug 09 16:47:48 2013 -0600" }, "message": "PCI: Add pci_reset_bridge_secondary_bus()\n\nMove the secondary bus reset code from pci_parent_bus_reset() into its own\nfunction. Export it as we\u0027ll later be calling it from hotplug controllers\nand elsewhere.\n\nSigned-off-by: Alex Williamson \u003calex.williamson@redhat.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "81377c8d3563e7aec5c8baaaacacb48034f430a0", "tree": "fe58387e3bea2c5b5656e2a81d9bfd558b2a3d83", "parents": [ "59da381ee2afc806f85becf3aa64ffc952355552" ], "author": { "name": "Jacob Keller", "email": "jacob.e.keller@intel.com", "time": "Wed Jul 31 06:53:26 2013 +0000" }, "committer": { "name": "Jeff Kirsher", "email": "jeffrey.t.kirsher@intel.com", "time": "Wed Jul 31 00:30:20 2013 -0700" }, "message": "PCI: Add function to obtain minimum link width and speed\n\nA PCI Express device can potentially report a link width and speed which it will\nnot properly fulfill due to being plugged into a slower link higher in the\nchain. This function walks up the PCI bus chain and calculates the minimum link\nwidth and speed of this entire chain. This can be useful to enable a device to\ndetermine if it has enough bandwidth for optimum functionality.\n\nSigned-off-by: Jacob Keller \u003cjacob.e.keller@intel.com\u003e\nTested-by: Phil Schmitt \u003cphillip.j.schmitt@intel.com\u003e\nAcked-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\nSigned-off-by: Jeff Kirsher \u003cjeffrey.t.kirsher@intel.com\u003e\n" }, { "commit": "59da381ee2afc806f85becf3aa64ffc952355552", "tree": "55a063b61da3c7adaff933956d300ea662774c9f", "parents": [ "343e51ae6e3f64ed26d96f5560f4962529794c9f" ], "author": { "name": "Jacob Keller", "email": "jacob.e.keller@intel.com", "time": "Wed Jul 31 06:53:21 2013 +0000" }, "committer": { "name": "Jeff Kirsher", "email": "jeffrey.t.kirsher@intel.com", "time": "Tue Jul 30 18:30:34 2013 -0700" }, "message": "PCI: move enum pcie_link_width into pci.h\n\npcie_link_width is the enum used to define the link width values for a pcie\ndevice. This enum should not be contained solely in pci_hotplug.h, and this\npatch moves it next to pci_bus_speed in pci.h\n\nSigned-off-by: Jacob Keller \u003cjacob.e.keller@intel.com\u003e\nTested-by: Phil Schmitt \u003cphillip.j.schmitt@intel.com\u003e\nAcked-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\nSigned-off-by: Jeff Kirsher \u003cjeffrey.t.kirsher@intel.com\u003e\n" }, { "commit": "39772038ea93e85ea4f1307ec9c1f48a063d89a0", "tree": "310d32883c16365b532448a434a7b834f0d6404b", "parents": [ "ff35147cf15814e13c62831f6910f8663e4dc91e" ], "author": { "name": "Yinghai Lu", "email": "yinghai@kernel.org", "time": "Mon Jul 22 14:37:18 2013 -0700" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Thu Jul 25 12:35:03 2013 -0600" }, "message": "PCI: Assign resources for hot-added host bridge more aggressively\n\nWhen hot-adding an ACPI host bridge, use\npci_assign_unassigned_root_bus_resources() instead of\npci_assign_unassigned_bus_resources().\n\nThe former is more aggressive and will release and reassign existing\nresources if necessary. This is safe at hot-add time because no drivers\nare bound to devices below the new host bridge yet.\n\n[bhelgaas: changelog, split __init changes out for reviewability]\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "928bea964827d7824b548c1f8e06eccbbc4d0d7d", "tree": "13110a5f05a65aa487cee8be5bd58017986f4929", "parents": [ "55ed83a615730c2578da155bc99b68f4417ffe20" ], "author": { "name": "Yinghai Lu", "email": "yinghai@kernel.org", "time": "Mon Jul 22 14:37:17 2013 -0700" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Thu Jul 25 12:35:03 2013 -0600" }, "message": "PCI: Delay enabling bridges until they\u0027re needed\n\nWe currently enable PCI bridges after scanning a bus and assigning\nresources. This is often done in arch code.\n\nThis patch changes this so we don\u0027t enable a bridge until necessary, i.e.,\nuntil we enable a PCI device behind the bridge. We do this in the generic\npci_enable_device() path, so this also removes the arch-specific code to\nenable bridges.\n\n[bhelgaas: changelog]\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "df58f46c0f2a1d69268b734ac25c87ffb7aeb32a", "tree": "46540d251f4f1c1e44af8d5ce339b37e0045ffe0", "parents": [ "726246d2e6d0ed53ac22b6fec50d1345f25e6730", "050134864c1c76f49eb86c134a0e02fb3c196382" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Fri Jun 14 17:47:46 2013 -0600" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Fri Jun 14 17:47:46 2013 -0600" }, "message": "Merge branch \u0027pci/jiang-bus-lock-v3\u0027 into next\n\n* pci/jiang-bus-lock-v3:\n PCI: Return early on allocation failures to unindent mainline code\n PCI: Simplify IOV implementation and fix reference count races\n PCI: Drop redundant setting of bus-\u003eis_added in virtfn_add_bus()\n unicore32/PCI: Remove redundant call of pci_bus_add_devices()\n m68k/PCI: Remove redundant call of pci_bus_add_devices()\n PCI: Rename pci_release_bus_bridge_dev() to pci_release_host_bridge_dev()\n PCI: Fix refcount issue in pci_create_root_bus() error recovery path\n ia64/PCI: Clean up pci_scan_root_bus() usage\n PCI: Convert alloc_pci_dev(void) to pci_alloc_dev(bus)\n PCI: Introduce pci_alloc_dev(struct pci_bus*) to replace alloc_pci_dev()\n PCI: Introduce pci_bus_{get|put}() to manage PCI bus reference count\n\nConflicts:\n\tdrivers/pci/probe.c\n" }, { "commit": "6ae32c539c0412ca789fb6041be45eeabf78431c", "tree": "b36080d53311d18da30cd2ab502cb7c27200eedc", "parents": [ "9a994e8ec7e7d6b1a66c74a683596b0f38f4e345" ], "author": { "name": "Sebastian Ott", "email": "sebott@linux.vnet.ibm.com", "time": "Tue Jun 04 19:18:14 2013 +0200" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Tue Jun 04 17:24:31 2013 -0600" }, "message": "PCI: Add pcibios_release_device()\n\nPlatforms may want to provide architecture-specific functionality when\na PCI device is released. Add a pcibios_release_device() call that\narchitectures can override to do so.\n\nSigned-off-by: Sebastian Ott \u003csebott@linux.vnet.ibm.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "3c6e6ae770f338ef3e54c5823c21063204f53537", "tree": "7460a7cdf07d4e2a734b9c39706b34ab85b6e05f", "parents": [ "fe830ef62ac6d8814e27b7e2f632848694b0e5c7" ], "author": { "name": "Gu Zheng", "email": "guz.fnst@cn.fujitsu.com", "time": "Sat May 25 21:48:30 2013 +0800" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Mon May 27 16:23:28 2013 -0600" }, "message": "PCI: Introduce pci_alloc_dev(struct pci_bus*) to replace alloc_pci_dev()\n\nHere we introduce a new interface to replace alloc_pci_dev():\n\n struct pci_dev *pci_alloc_dev(struct pci_bus *bus)\n\nIt takes a \"struct pci_bus *\" argument, so we can alloc a PCI device\non a target PCI bus, and it acquires a reference on the pci_bus.\nWe use pci_alloc_dev(NULL) to simplify the old alloc_pci_dev(),\nand keep it for a while but mark it as __deprecated.\n\nHolding a reference to the pci_bus ensures that referencing\npci_dev-\u003ebus is valid as long as the pci_dev is valid.\n\n[bhelgaas: keep existing \"return error early\" structure in pci_alloc_dev()]\nSigned-off-by: Gu Zheng \u003cguz.fnst@cn.fujitsu.com\u003e\nSigned-off-by: Jiang Liu \u003cjiang.liu@huawei.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "fe830ef62ac6d8814e27b7e2f632848694b0e5c7", "tree": "7a75eef662b6186781efb11566f3a7aa01a7cc60", "parents": [ "f722406faae2d073cc1d01063d1123c35425939e" ], "author": { "name": "Jiang Liu", "email": "liuj97@gmail.com", "time": "Sat May 25 21:48:29 2013 +0800" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Mon May 27 16:22:09 2013 -0600" }, "message": "PCI: Introduce pci_bus_{get|put}() to manage PCI bus reference count\n\nIntroduce helper functions pci_bus_{get|put}() to manage PCI bus\nreference count.\n\nSigned-off-by: Jiang Liu \u003cjiang.liu@huawei.com\u003e\nSigned-off-by: Yijing Wang \u003cwangyijing@huawei.com\u003e\nSigned-off-by: Gu Zheng \u003cguz.fnst@cn.fujitsu.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "73287a43cc79ca06629a88d1a199cd283f42456a", "tree": "acf4456e260115bea77ee31a29f10ce17f0db45c", "parents": [ "251df49db3327c64bf917bfdba94491fde2b4ee0", "20074f357da4a637430aec2879c9d864c5d2c23c" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed May 01 14:08:52 2013 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed May 01 14:08:52 2013 -0700" }, "message": "Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next\n\nPull networking updates from David Miller:\n \"Highlights (1721 non-merge commits, this has to be a record of some\n sort):\n\n 1) Add \u0027random\u0027 mode to team driver, from Jiri Pirko and Eric\n Dumazet.\n\n 2) Make it so that any driver that supports configuration of multiple\n MAC addresses can provide the forwarding database add and del\n calls by providing a default implementation and hooking that up if\n the driver doesn\u0027t have an explicit set of handlers. From Vlad\n Yasevich.\n\n 3) Support GSO segmentation over tunnels and other encapsulating\n devices such as VXLAN, from Pravin B Shelar.\n\n 4) Support L2 GRE tunnels in the flow dissector, from Michael Dalton.\n\n 5) Implement Tail Loss Probe (TLP) detection in TCP, from Nandita\n Dukkipati.\n\n 6) In the PHY layer, allow supporting wake-on-lan in situations where\n the PHY registers have to be written for it to be configured.\n\n Use it to support wake-on-lan in mv643xx_eth.\n\n From Michael Stapelberg.\n\n 7) Significantly improve firewire IPV6 support, from YOSHIFUJI\n Hideaki.\n\n 8) Allow multiple packets to be sent in a single transmission using\n network coding in batman-adv, from Martin Hundebøll.\n\n 9) Add support for T5 cxgb4 chips, from Santosh Rastapur.\n\n 10) Generalize the VXLAN forwarding tables so that there is more\n flexibility in configurating various aspects of the endpoints.\n From David Stevens.\n\n 11) Support RSS and TSO in hardware over GRE tunnels in bxn2x driver,\n from Dmitry Kravkov.\n\n 12) Zero copy support in nfnelink_queue, from Eric Dumazet and Pablo\n Neira Ayuso.\n\n 13) Start adding networking selftests.\n\n 14) In situations of overload on the same AF_PACKET fanout socket, or\n per-cpu packet receive queue, minimize drop by distributing the\n load to other cpus/fanouts. From Willem de Bruijn and Eric\n Dumazet.\n\n 15) Add support for new payload offset BPF instruction, from Daniel\n Borkmann.\n\n 16) Convert several drivers over to mdoule_platform_driver(), from\n Sachin Kamat.\n\n 17) Provide a minimal BPF JIT image disassembler userspace tool, from\n Daniel Borkmann.\n\n 18) Rewrite F-RTO implementation in TCP to match the final\n specification of it in RFC4138 and RFC5682. From Yuchung Cheng.\n\n 19) Provide netlink socket diag of netlink sockets (\"Yo dawg, I hear\n you like netlink, so I implemented netlink dumping of netlink\n sockets.\") From Andrey Vagin.\n\n 20) Remove ugly passing of rtnetlink attributes into rtnl_doit\n functions, from Thomas Graf.\n\n 21) Allow userspace to be able to see if a configuration change occurs\n in the middle of an address or device list dump, from Nicolas\n Dichtel.\n\n 22) Support RFC3168 ECN protection for ipv6 fragments, from Hannes\n Frederic Sowa.\n\n 23) Increase accuracy of packet length used by packet scheduler, from\n Jason Wang.\n\n 24) Beginning set of changes to make ipv4/ipv6 fragment handling more\n scalable and less susceptible to overload and locking contention,\n from Jesper Dangaard Brouer.\n\n 25) Get rid of using non-type-safe NLMSG_* macros and use nlmsg_*()\n instead. From Hong Zhiguo.\n\n 26) Optimize route usage in IPVS by avoiding reference counting where\n possible, from Julian Anastasov.\n\n 27) Convert IPVS schedulers to RCU, also from Julian Anastasov.\n\n 28) Support cpu fanouts in xt_NFQUEUE netfilter target, from Holger\n Eitzenberger.\n\n 29) Network namespace support for nf_log, ebt_log, xt_LOG, ipt_ULOG,\n nfnetlink_log, and nfnetlink_queue. From Gao feng.\n\n 30) Implement RFC3168 ECN protection, from Hannes Frederic Sowa.\n\n 31) Support several new r8169 chips, from Hayes Wang.\n\n 32) Support tokenized interface identifiers in ipv6, from Daniel\n Borkmann.\n\n 33) Use usbnet_link_change() helper in USB net driver, from Ming Lei.\n\n 34) Add 802.1ad vlan offload support, from Patrick McHardy.\n\n 35) Support mmap() based netlink communication, also from Patrick\n McHardy.\n\n 36) Support HW timestamping in mlx4 driver, from Amir Vadai.\n\n 37) Rationalize AF_PACKET packet timestamping when transmitting, from\n Willem de Bruijn and Daniel Borkmann.\n\n 38) Bring parity to what\u0027s provided by /proc/net/packet socket dumping\n and the info provided by netlink socket dumping of AF_PACKET\n sockets. From Nicolas Dichtel.\n\n 39) Fix peeking beyond zero sized SKBs in AF_UNIX, from Benjamin\n Poirier\"\n\n* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next: (1722 commits)\n filter: fix va_list build error\n af_unix: fix a fatal race with bit fields\n bnx2x: Prevent memory leak when cnic is absent\n bnx2x: correct reading of speed capabilities\n net: sctp: attribute printl with __printf for gcc fmt checks\n netlink: kconfig: move mmap i/o into netlink kconfig\n netpoll: convert mutex into a semaphore\n netlink: Fix skb ref counting.\n net_sched: act_ipt forward compat with xtables\n mlx4_en: fix a build error on 32bit arches\n Revert \"bnx2x: allow nvram test to run when device is down\"\n bridge: avoid OOPS if root port not found\n drivers: net: cpsw: fix kernel warn on cpsw irq enable\n sh_eth: use random MAC address if no valid one supplied\n 3c509.c: call SET_NETDEV_DEV for all device types (ISA/ISAPnP/EISA)\n tg3: fix to append hardware time stamping flags\n unix/stream: fix peeking with an offset larger than data in queue\n unix/dgram: fix peeking with an offset larger than data in queue\n unix/dgram: peek beyond 0-sized skbs\n openvswitch: Remove unneeded ovs_netdev_get_ifindex()\n ...\n" }, { "commit": "96a3e8af5a54c324535472ca946215d5bafe6539", "tree": "e59b48aa3fa2b8c6c1f59f76b7b4c71f9c694093", "parents": [ "a87451052fb914744571fc3ab39fcbf4fa4ef944", "d4f09c5d7fbabd1389a5f03f5c9329d790f544e3" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Apr 29 09:30:25 2013 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Apr 29 09:30:25 2013 -0700" }, "message": "Merge tag \u0027pci-v3.10-changes\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci\n\nPull PCI updates from Bjorn Helgaas:\n \"PCI changes for the v3.10 merge window:\n\n PCI device hotplug\n - Remove ACPI PCI subdrivers (Jiang Liu, Myron Stowe)\n - Make acpiphp builtin only, not modular (Jiang Liu)\n - Add acpiphp mutual exclusion (Jiang Liu)\n\n Power management\n - Skip \"PME enabled/disabled\" messages when not supported (Rafael\n Wysocki)\n - Fix fallback to PCI_D0 (Rafael Wysocki)\n\n Miscellaneous\n - Factor quirk_io_region (Yinghai Lu)\n - Cache MSI capability offsets \u0026 cleanup (Gavin Shan, Bjorn Helgaas)\n - Clean up EISA resource initialization and logging (Bjorn Helgaas)\n - Fix prototype warnings (Andy Shevchenko, Bjorn Helgaas)\n - MIPS: Initialize of_node before scanning bus (Gabor Juhos)\n - Fix pcibios_get_phb_of_node() declaration \"weak\" annotation (Gabor\n Juhos)\n - Add MSI INTX_DISABLE quirks for AR8161/AR8162/etc (Xiong Huang)\n - Fix aer_inject return values (Prarit Bhargava)\n - Remove PME/ACPI dependency (Andrew Murray)\n - Use shared PCI_BUS_NUM() and PCI_DEVID() (Shuah Khan)\"\n\n* tag \u0027pci-v3.10-changes\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (63 commits)\n vfio-pci: Use cached MSI/MSI-X capabilities\n vfio-pci: Use PCI_MSIX_TABLE_BIR, not PCI_MSIX_FLAGS_BIRMASK\n PCI: Remove \"extern\" from function declarations\n PCI: Use PCI_MSIX_TABLE_BIR, not PCI_MSIX_FLAGS_BIRMASK\n PCI: Drop msi_mask_reg() and remove drivers/pci/msi.h\n PCI: Use msix_table_size() directly, drop multi_msix_capable()\n PCI: Drop msix_table_offset_reg() and msix_pba_offset_reg() macros\n PCI: Drop is_64bit_address() and is_mask_bit_support() macros\n PCI: Drop msi_data_reg() macro\n PCI: Drop msi_lower_address_reg() and msi_upper_address_reg() macros\n PCI: Drop msi_control_reg() macro and use PCI_MSI_FLAGS directly\n PCI: Use cached MSI/MSI-X offsets from dev, not from msi_desc\n PCI: Clean up MSI/MSI-X capability #defines\n PCI: Use cached MSI-X cap while enabling MSI-X\n PCI: Use cached MSI cap while enabling MSI interrupts\n PCI: Remove MSI/MSI-X cap check in pci_msi_check_device()\n PCI: Cache MSI/MSI-X capability offsets in struct pci_dev\n PCI: Use u8, not int, for PM capability offset\n [SCSI] megaraid_sas: Use correct #define for MSI-X capability\n PCI: Remove \"extern\" from function declarations\n ...\n" }, { "commit": "5a8eb24292ffd68604cedeb24ad2b4bc02cfc037", "tree": "f85a264eccef0fec9337be43d8ff5fa5bac7a250", "parents": [ "d44e7a9a1f1e56918f8e937dcf750626ac5ad9b4" ], "author": { "name": "Alexander Duyck", "email": "alexander.h.duyck@intel.com", "time": "Thu Apr 25 04:42:29 2013 +0000" }, "committer": { "name": "Jeff Kirsher", "email": "jeffrey.t.kirsher@intel.com", "time": "Wed Apr 24 19:31:58 2013 -0700" }, "message": "pci: Add SRIOV helper function to determine if VFs are assigned to guest\n\nThis function is meant to add a helper function that will determine if a PF\nhas any VFs that are currently assigned to a guest. We currently have been\nimplementing this function per driver, and going forward I would like to avoid\nthat by making this function generic and using this helper.\n\nv2: Removed extern from declaration of pci_vfs_assigned in pci.h and return\n 0 if SR-IOV is disabled with is inline with other PCI SRIOV functions.\n\nSigned-off-by: Alexander Duyck \u003calexander.h.duyck@intel.com\u003e\nAcked-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\nSigned-off-by: Jeff Kirsher \u003cjeffrey.t.kirsher@intel.com\u003e\n" }, { "commit": "d4f09c5d7fbabd1389a5f03f5c9329d790f544e3", "tree": "e7c5a84a9b20364fd21ae7f5ce6c4412440c0937", "parents": [ "42c34707f9d24ef159cce87e4353babcf2b417a6", "a9047f24df85b06d3fd443ff76e9993bc127c570" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Wed Apr 24 11:37:49 2013 -0600" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Wed Apr 24 11:37:49 2013 -0600" }, "message": "Merge branch \u0027pci/gavin-msi-cleanup\u0027 into next\n\n* pci/gavin-msi-cleanup:\n vfio-pci: Use cached MSI/MSI-X capabilities\n vfio-pci: Use PCI_MSIX_TABLE_BIR, not PCI_MSIX_FLAGS_BIRMASK\n PCI: Remove \"extern\" from function declarations\n PCI: Use PCI_MSIX_TABLE_BIR, not PCI_MSIX_FLAGS_BIRMASK\n PCI: Drop msi_mask_reg() and remove drivers/pci/msi.h\n PCI: Use msix_table_size() directly, drop multi_msix_capable()\n PCI: Drop msix_table_offset_reg() and msix_pba_offset_reg() macros\n PCI: Drop is_64bit_address() and is_mask_bit_support() macros\n PCI: Drop msi_data_reg() macro\n PCI: Drop msi_lower_address_reg() and msi_upper_address_reg() macros\n PCI: Drop msi_control_reg() macro and use PCI_MSI_FLAGS directly\n PCI: Use cached MSI/MSI-X offsets from dev, not from msi_desc\n PCI: Clean up MSI/MSI-X capability #defines\n PCI: Use cached MSI-X cap while enabling MSI-X\n PCI: Use cached MSI cap while enabling MSI interrupts\n PCI: Remove MSI/MSI-X cap check in pci_msi_check_device()\n PCI: Cache MSI/MSI-X capability offsets in struct pci_dev\n PCI: Use u8, not int, for PM capability offset\n [SCSI] megaraid_sas: Use correct #define for MSI-X capability\n" }, { "commit": "e375b561817d9ae098cc4296a729fc88924a0159", "tree": "7cd6f54166d29a1b7c612e407d57ce79b1024610", "parents": [ "703860ed4e36ded696bd44af6107243fdedfb746" ], "author": { "name": "Gavin Shan", "email": "shangw@linux.vnet.ibm.com", "time": "Thu Apr 04 16:54:30 2013 +0000" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Tue Apr 23 09:50:30 2013 -0600" }, "message": "PCI: Cache MSI/MSI-X capability offsets in struct pci_dev\n\nThe patch caches the MSI and MSI-X capability offset in PCI device\n(struct pci_dev) so that we needn\u0027t read it from the config space\nupon enabling or disabling MSI or MSI-X interrupts.\n\n[bhelgaas: moved pm_cap size change to separate patch]\nSigned-off-by: Gavin Shan \u003cshangw@linux.vnet.ibm.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "703860ed4e36ded696bd44af6107243fdedfb746", "tree": "eb5bd366144a03639ac8ae229c571381a1c98e96", "parents": [ "99369065970e9ea7d1ca489341ed29d1a72ec0b5" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Wed Apr 17 16:57:56 2013 -0600" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Tue Apr 23 09:50:30 2013 -0600" }, "message": "PCI: Use u8, not int, for PM capability offset\n\nThe Power Management Capability (PCI_CAP_ID_PM \u003d\u003d 0x01) is defined by PCI\nand must appear in the 256-byte PCI Configuration Space from 0-0xff. It\ncannot be in the PCIe Extended Configuration space from 0x100-0xfff, so\nwe only need a u8 to hold its offset.\n\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\nAcked-by: Rafael J. Wysocki \u003crafael.j.wysocki@intel.com\u003e" }, { "commit": "723ec4d06cb2eed481436cfe008f5f63c45e88fd", "tree": "e59112af8616e8fbc0cc6c2219b49fd2f05bfc41", "parents": [ "a3b6bbd5774c13dab89d72f79976ba762913b2f2", "f39d5b72913e2a9ff00ba5ab145ee05a888b1286" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Wed Apr 17 10:31:34 2013 -0600" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Wed Apr 17 10:31:34 2013 -0600" }, "message": "Merge branch \u0027pci/cleanup\u0027 into next\n\n* pci/cleanup:\n PCI: Remove \"extern\" from function declarations\n PCI: Warn about failures instead of \"must_check\" functions\n PCI: Remove __must_check from definitions\n PCI: Remove unused variables\n PCI: Move cpci_hotplug_init() proto to header file\n PCI: Make local functions/structs static\n PCI: Fix missing prototype for pcie_port_acpi_setup()\n\nConflicts:\n\tdrivers/pci/hotplug/acpiphp.h\n\tinclude/linux/pci.h\n" }, { "commit": "f39d5b72913e2a9ff00ba5ab145ee05a888b1286", "tree": "bf037ca60a3724a7636166093b4b2ede4aeaf464", "parents": [ "9fc9eea09f518b9bbdc0a14ef668698c913ba614" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Fri Apr 12 12:02:59 2013 -0600" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Wed Apr 17 10:21:17 2013 -0600" }, "message": "PCI: Remove \"extern\" from function declarations\n\nWe had an inconsistent mix of using and omitting the \"extern\" keyword\non function declarations in header files. This removes them all.\n\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "a3b6bbd5774c13dab89d72f79976ba762913b2f2", "tree": "e646832db42284e97e6b4d1edc616ce06e0fd407", "parents": [ "30e22b2337be44f4363fa52858d1ca7be6794ee8", "c309dbb4debb714566e4cf0d5d4e4023c3c4ff2f" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Tue Apr 16 10:37:22 2013 -0600" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Tue Apr 16 10:37:22 2013 -0600" }, "message": "Merge branch \u0027pci/jiang-subdrivers\u0027 into next\n\n* pci/jiang-subdrivers:\n PCI/ACPI: Remove support of ACPI PCI subdrivers\n PCI: acpiphp: Protect acpiphp data structures from concurrent updates\n PCI: acpiphp: Use normal list to simplify implementation\n PCI: acpiphp: Do not use ACPI PCI subdriver mechanism\n PCI: acpiphp: Convert acpiphp to be builtin only, not modular\n PCI/ACPI: Handle PCI slot devices when creating/destroying PCI buses\n x86/PCI: Implement pcibios_{add|remove}_bus() hooks\n ia64/PCI: Implement pcibios_{add|remove}_bus() hooks\n PCI/ACPI: Prepare stub functions to handle ACPI PCI (hotplug) slots\n PCI: Add pcibios hooks for adding and removing PCI buses\n PCI: acpiphp: Replace local macros with standard ACPI macros\n PCI: acpiphp: Remove all functions even if function 0 doesn\u0027t exist\n PCI: acpiphp: Use list_for_each_entry_safe() in acpiphp_sanitize_bus()\n PCI: Clean up usages of pci_bus-\u003eis_added\n PCI: When removing bus, always remove legacy files \u0026 unregister\n" }, { "commit": "272e70c0ded509906b7469ea0d487725ef1c17b3", "tree": "fe14da14dffbe51dc689f9bac3e6e85c145a08bf", "parents": [ "833260631178aa26c70a0b05eabc953f5e47167d", "9a97cd43f4ef62520a852b5a2348233b0f37455b" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Mon Apr 15 14:26:15 2013 -0600" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Mon Apr 15 14:26:15 2013 -0600" }, "message": "Merge branch \u0027pci/gabor-get-of-node\u0027 into next\n\n* pci/gabor-get-of-node:\n MIPS/PCI: Implement pcibios_get_phb_of_node\n PCI: Remove __weak annotation from pcibios_get_phb_of_node decl\n" }, { "commit": "10a9574756201fbbdd0cac11f370f00d3d02bfa1", "tree": "3e2985b5a56e2c5bbc95b1e81e043a2f3ae20f83", "parents": [ "ce15d873d05ebf3bf38579c4e0252140e28f1781" ], "author": { "name": "Jiang Liu", "email": "liuj97@gmail.com", "time": "Fri Apr 12 05:44:20 2013 +0000" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Fri Apr 12 15:38:25 2013 -0600" }, "message": "PCI: Add pcibios hooks for adding and removing PCI buses\n\nOn ACPI-based platforms, the pci_slot driver creates PCI slot devices\naccording to information from ACPI tables by registering an ACPI PCI\nsubdriver. The ACPI PCI subdriver will only be called when creating/\ndestroying PCI root buses, and it won\u0027t be called when hot-plugging\nP2P bridges. It may cause stale PCI slot devices after hot-removing\na P2P bridge if that bridge has associated PCI slots. And the acpiphp\ndriver has the same issue too.\n\nThis patch introduces two hook points into the PCI core, which will\nbe invoked when creating/destroying PCI buses for PCI host and P2P\nbridges. They could be used to setup/destroy platform dependent stuff\nin a unified way, both at boot time and for PCI hotplug operations.\n\nSigned-off-by: Jiang Liu \u003cjiang.liu@huawei.com\u003e\nSigned-off-by: Yijing Wang \u003cwangyijing@huawei.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\nReviewed-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nCc: \"Rafael J. Wysocki\" \u003crafael.j.wysocki@intel.com\u003e\nCc: Toshi Kani \u003ctoshi.kani@hp.com\u003e\nCc: Tony Luck \u003ctony.luck@intel.com\u003e\nCc: Fenghua Yu \u003cfenghua.yu@intel.com\u003e\nCc: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nCc: Ingo Molnar \u003cmingo@redhat.com\u003e\nCc: \"H. Peter Anvin\" \u003chpa@zytor.com\u003e\nCc: Myron Stowe \u003cmyron.stowe@redhat.com\u003e" }, { "commit": "10629d711ed780470937ecda50d9ffa0e925a4ee", "tree": "359e488fdc8478753a76ea034ea2c59826f03e22", "parents": [ "f6161aa153581da4a3867a2d1a7caf4be19b6ec9" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Wed Apr 10 09:56:54 2013 -0600" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Wed Apr 10 09:56:54 2013 -0600" }, "message": "PCI: Remove __weak annotation from pcibios_get_phb_of_node decl\n\nThe __weak annotation on the pcibios_get_phb_of_node() declaration\ncauses *every* definition to be marked \"weak.\" The linker then\nselects one based on link order, which may be the wrong one.\n\nGabor found that on MIPS, the linker selected the generic implementation\nfrom drivers/pci even though arch/mips supplied a definition without the\n__weak annotation:\n\n$ mipsel-openwrt-linux-readelf -s arch/mips/pci/built-in.o \\\n drivers/pci/built-in.o vmlinux.o | grep pcibios_get_phb_of_node\n 86: 0000046c 12 FUNC WEAK DEFAULT 2 pcibios_get_phb_of_node\n 1430: 00012e2c 104 FUNC WEAK DEFAULT 2 pcibios_get_phb_of_node\n 31898: 0017e4ec 104 FUNC WEAK DEFAULT 2 pcibios_get_phb_of_node\n\nThis removes the __weak annotation from the pcibios_get_phb_of_node()\ndeclaration so arch-specific non-weak implementations work reliably.\n\nSuggested-by: Gabor Juhos \u003cjuhosg@openwrt.org\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "fffe01f7a768d07cc50ace71abe28fbf2f786a43", "tree": "6e20b8c21f80d5d27f473e59fdb1696e165fbe1e", "parents": [ "8bb9660418e05bb1845ac1a2428444d78e322cc7" ], "author": { "name": "Matthew Garrett", "email": "matthew.garrett@nebula.com", "time": "Tue Mar 26 17:25:54 2013 -0400" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Tue Mar 26 17:19:41 2013 -0600" }, "message": "PCI: Add PCI ROM helper for platform-provided ROM images\n\nIt turns out that some UEFI systems provide apparently an apparently valid\nPCI ROM BAR that turns out to contain garbage, so the attempt in 547b52463\nto prefer the ROM from the BAR actually breaks a different set of machines.\nAs Linus pointed out, the graphics drivers are probably in the best\nposition to make this judgement, so this basically reverts 547b52463 and\nf9a37be0f and adds a new helper function. Followup patches will add support\nto nouveau and radeon for probing this ROM source if they can\u0027t find a ROM\nfrom some other source.\n\n[bhelgaas: added reporter and bugzilla pointers, s/f4eb5ff05/547b52463]\nReference: https://bugzilla.redhat.com/show_bug.cgi?id\u003d927451\nReference: http://lkml.kernel.org/r/kg69ef$vdb$1@ger.gmane.org\nReported-by: Mantas Mikulėnas \u003cgrawity@gmail.com\u003e\nReported-by: Chris Murphy \u003cbugzilla@colorremedies.com\u003e\nSigned-off-by: Matthew Garrett \u003cmatthew.garrett@nebula.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "85467136cdcc674f30beb0e5b79f048fe3a6a76f", "tree": "e82d7a226b5855b63e731ba714965d42a5122541", "parents": [ "f6161aa153581da4a3867a2d1a7caf4be19b6ec9" ], "author": { "name": "Shuah Khan", "email": "shuah.khan@hp.com", "time": "Wed Feb 27 17:06:45 2013 -0700" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Tue Mar 26 15:20:01 2013 -0600" }, "message": "PCI: Add PCI_BUS_NUM() and PCI_DEVID() interfaces\n\nPCI defines PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() interfaces; however,\nit doesn\u0027t have interfaces to return PCI bus and PCI device id. Drivers\n(AMD IOMMU, and AER) implement module specific definitions for PCI_BUS()\nand AMD_IOMMU driver also has a module specific interface to calculate PCI\ndevice id from bus number and devfn.\n\nAdd PCI_BUS_NUM and PCI_DEVID interfaces to return PCI bus number and PCI\ndevice id respectively to avoid the need for duplicate definitions in other\nmodules. AER driver code and AMD IOMMU driver define PCI_BUS. AMD IOMMU\ndriver defines an interface to calculate device id from bus number, and\ndevfn pair.\n\nPCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() interfaces are exported to\nuser-space via uapi/linux/pci.h. However, in the interest to keep the new\ninterfaces as kernel only and not export them to user-space unnecessarily,\nadded them to linux/pci.h instead.\n\nSigned-off-by: Shuah Khan \u003cshuah.khan@hp.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\nAcked-by: Joerg Roedel \u003cjoro@8bytes.org\u003e" }, { "commit": "556f12f602ac0a18a82ca83e9f8e8547688fc633", "tree": "d4051f6dd57968c8e8e660ad117c5bedc2aa7e8e", "parents": [ "fffddfd6c8e0c10c42c6e2cc54ba880fcc36ebbb", "018ba0a6efada61b9bc17500101d81c3d35807c2" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Feb 25 21:18:18 2013 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Feb 25 21:18:18 2013 -0800" }, "message": "Merge tag \u0027pci-v3.9-changes\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci\n\nPull PCI changes from Bjorn Helgaas:\n \"Host bridge hotplug\n - Major overhaul of ACPI host bridge add/start (Rafael Wysocki, Yinghai Lu)\n - Major overhaul of PCI/ACPI binding (Rafael Wysocki, Yinghai Lu)\n - Split out ACPI host bridge and ACPI PCI device hotplug (Yinghai Lu)\n - Stop caching _PRT and make independent of bus numbers (Yinghai Lu)\n\n PCI device hotplug\n - Clean up cpqphp dead code (Sasha Levin)\n - Disable ARI unless device and upstream bridge support it (Yijing Wang)\n - Initialize all hot-added devices (not functions 0-7) (Yijing Wang)\n\n Power management\n - Don\u0027t touch ASPM if disabled (Joe Lawrence)\n - Fix ASPM link state management (Myron Stowe)\n\n Miscellaneous\n - Fix PCI_EXP_FLAGS accessor (Alex Williamson)\n - Disable Bus Master in pci_device_shutdown (Konstantin Khlebnikov)\n - Document hotplug resource and MPS parameters (Yijing Wang)\n - Add accessor for PCIe capabilities (Myron Stowe)\n - Drop pciehp suspend/resume messages (Paul Bolle)\n - Make pci_slot built-in only (not a module) (Jiang Liu)\n - Remove unused PCI/ACPI bind ops (Jiang Liu)\n - Removed used pci_root_bus (Bjorn Helgaas)\"\n\n* tag \u0027pci-v3.9-changes\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (51 commits)\n PCI/ACPI: Don\u0027t cache _PRT, and don\u0027t associate them with bus numbers\n PCI: Fix PCI Express Capability accessors for PCI_EXP_FLAGS\n ACPI / PCI: Make pci_slot built-in only, not a module\n PCI/PM: Clear state_saved during suspend\n PCI: Use atomic_inc_return() rather than atomic_add_return()\n PCI: Catch attempts to disable already-disabled devices\n PCI: Disable Bus Master unconditionally in pci_device_shutdown()\n PCI: acpiphp: Remove dead code for PCI host bridge hotplug\n PCI: acpiphp: Create companion ACPI devices before creating PCI devices\n PCI: Remove unused \"rc\" in virtfn_add_bus()\n PCI: pciehp: Drop suspend/resume ENTRY messages\n PCI/ASPM: Don\u0027t touch ASPM if forcibly disabled\n PCI/ASPM: Deallocate upstream link state even if device is not PCIe\n PCI: Document MPS parameters pci\u003dpcie_bus_safe, pci\u003dpcie_bus_perf, etc\n PCI: Document hpiosize\u003d and hpmemsize\u003d resource reservation parameters\n PCI: Use PCI Express Capability accessor\n PCI: Introduce accessor to retrieve PCIe Capabilities Register\n PCI: Put pci_dev in device tree as early as possible\n PCI: Skip attaching driver in device_add()\n PCI: acpiphp: Keep driver loaded even if no slots found\n ...\n" }, { "commit": "f2dfcde4ccd101fa3ba8f6c27273a0e359ea9c9c", "tree": "2920a8164d5243bc4c6a5e0eb006f1256ccecf66", "parents": [ "ecb87e6609d3a559eacf7a61f5b4e088a797d07c", "775c739e0b08fbffb791595a4708460fc978b5b6" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Sat Feb 02 14:35:57 2013 -0700" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Sat Feb 02 14:35:57 2013 -0700" }, "message": "Merge branch \u0027pci/misc\u0027 into next\n\n* pci/misc:\n PCI: pciehp: Drop suspend/resume ENTRY messages\n PCI: Document MPS parameters pci\u003dpcie_bus_safe, pci\u003dpcie_bus_perf, etc\n PCI: Document hpiosize\u003d and hpmemsize\u003d resource reservation parameters\n PCI: Use PCI Express Capability accessor\n PCI: Introduce accessor to retrieve PCIe Capabilities Register\n PCI: Kill pci_is_reassigndev()\n" }, { "commit": "1c531d82ee1a220ae7132ba0eb31edaf186b56d1", "tree": "67736581bd5f36192ef9f2f27a1c28ec9b61e330", "parents": [ "7c9c003c68de51fb8712a01e904444ef40c742f5" ], "author": { "name": "Myron Stowe", "email": "myron.stowe@redhat.com", "time": "Fri Jan 25 17:55:45 2013 -0700" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Wed Jan 30 21:24:39 2013 -0700" }, "message": "PCI: Use PCI Express Capability accessor\n\nUse PCI Express Capability access functions to simplify device\nCapabilities Register usages.\n\nSigned-off-by: Myron Stowe \u003cmyron.stowe@redhat.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "7c9c003c68de51fb8712a01e904444ef40c742f5", "tree": "b552544c5c2d59b8e94199ccc75fd782c5a68ee8", "parents": [ "10c463a7a3b96285133c37e230781a1274abbd31" ], "author": { "name": "Myron Stowe", "email": "myron.stowe@redhat.com", "time": "Fri Jan 25 17:55:39 2013 -0700" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Wed Jan 30 21:24:05 2013 -0700" }, "message": "PCI: Introduce accessor to retrieve PCIe Capabilities Register\n\nProvide an accessor to retrieve the PCI Express device\u0027s Capabilities\nRegister.\n\nSigned-off-by: Myron Stowe \u003cmyron.stowe@redhat.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "939de1d69c5fb0da0cfe05a1a7c981421cf876f7", "tree": "3ca1c6457e1c1ae4c11adab60e94d666841983aa", "parents": [ "fb455792d91469fe556b68f1baa9ff5493432be8", "4f535093cf8f6da8cfda7c36c2c1ecd2e9586ee4" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Sat Jan 26 17:35:58 2013 -0700" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Sat Jan 26 17:35:58 2013 -0700" }, "message": "Merge branch \u0027pci/yinghai-root-bus-hotplug\u0027 into next\n\n* pci/yinghai-root-bus-hotplug:\n PCI: Put pci_dev in device tree as early as possible\n PCI: Skip attaching driver in device_add()\n PCI: acpiphp: Keep driver loaded even if no slots found\n PCI/ACPI: Print info if host bridge notify handler installation fails\n PCI: acpiphp: Move host bridge hotplug to pci_root.c\n PCI/ACPI: acpiphp: Rename alloc_acpiphp_hp_work() to alloc_acpi_hp_work()\n PCI: Make device create/destroy logic symmetric\n PCI: Fix reference count leak in pci_dev_present()\n PCI: Set pci_dev dev_node early so IOAPIC irq_descs are allocated locally\n PCI: Add root bus children dev\u0027s res to fail list\n PCI: acpiphp: Add is_hotplug_bridge detection\n\nConflicts:\n\tdrivers/pci/pci.h\n" }, { "commit": "58d9a38f6facb28e935ec2747f6d9e9bf4684118", "tree": "252899cd333ccc3c23c2435acd3f377512092aa0", "parents": [ "d59f53bc9bd80ee62072dea590fc623c67cb84a8" ], "author": { "name": "Yinghai Lu", "email": "yinghai@kernel.org", "time": "Mon Jan 21 13:20:51 2013 -0800" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Fri Jan 25 15:10:12 2013 -0700" }, "message": "PCI: Skip attaching driver in device_add()\n\nWe want to add PCI devices to the device tree as early as possible but\ndelay attaching drivers.\n\ndevice_add() adds a device to the device hierarchy and (via\ndevice_attach()) attaches a matching driver and calls its .probe() method.\nWe want to separate adding the device to the hierarchy from attaching the\ndriver.\n\nThis patch does that by adding \"match_driver\" in struct pci_dev. When\nfalse, we return failure from pci_bus_match(), which makes device_attach()\nbelieve there\u0027s no matching driver.\n\nLater, we set \"match_driver \u003d true\" and call device_attach() again, which\nnow attaches the driver and calls its .probe() method.\n\n[bhelgaas: changelog, explicitly init dev-\u003ematch_driver,\nfold device_attach() call into pci_bus_add_device()]\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\nAcked-by: Rafael J. Wysocki \u003crafael.j.wysocki@intel.com\u003e" }, { "commit": "08261d87f7d1b6253ab3223756625a5c74532293", "tree": "c0025a8e4593564bf356f1f185c21a137a96cb8a", "parents": [ "51906e779f2b13b38f8153774c4c7163d412ffd9" ], "author": { "name": "Alexander Gordeev", "email": "agordeev@redhat.com", "time": "Mon Nov 19 16:02:10 2012 +0100" }, "committer": { "name": "Ingo Molnar", "email": "mingo@kernel.org", "time": "Thu Jan 24 17:25:13 2013 +0100" }, "message": "PCI/MSI: Enable multiple MSIs with pci_enable_msi_block_auto()\n\nThe new function pci_enable_msi_block_auto() tries to allocate\nmaximum possible number of MSIs up to the number the device\nsupports. It generalizes a pattern when pci_enable_msi_block()\nis contiguously called until it succeeds or fails.\n\nOpposite to pci_enable_msi_block() which takes the number of\nMSIs to allocate as a input parameter,\npci_enable_msi_block_auto() could be used by device drivers to\nobtain the number of assigned MSIs and the number of MSIs the\ndevice supports.\n\nSigned-off-by: Alexander Gordeev \u003cagordeev@redhat.com\u003e\nAcked-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\nCc: Suresh Siddha \u003csuresh.b.siddha@intel.com\u003e\nCc: Yinghai Lu \u003cyinghai@kernel.org\u003e\nCc: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nCc: Jeff Garzik \u003cjgarzik@pobox.com\u003e\nCc: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\nCc: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nCc: Peter Zijlstra \u003ca.p.zijlstra@chello.nl\u003e\nCc: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nLink: http://lkml.kernel.org/r/c3de2419df94a0f95ca1a6f755afc421486455e6.1353324359.git.agordeev@redhat.com\nSigned-off-by: Ingo Molnar \u003cmingo@kernel.org\u003e\n" }, { "commit": "6c0cc950ae670403a362bdcbf3cde0df33744928", "tree": "45c438f12c5af1ea66aae56c03ac9e53f80899fa", "parents": [ "295a7f6235bfa21be3454aebc1bea1eaf0b74fb7" ], "author": { "name": "Rafael J. Wysocki", "email": "rafael.j.wysocki@intel.com", "time": "Wed Jan 09 22:33:37 2013 +0100" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Sun Jan 13 17:14:28 2013 -0700" }, "message": "ACPI / PCI: Set root bridge ACPI handle in advance\n\nThe ACPI handles of PCI root bridges need to be known to\nacpi_bind_one(), so that it can create the appropriate\n\"firmware_node\" and \"physical_node\" files for them, but currently\nthe way it gets to know those handles is not exactly straightforward\n(to put it lightly).\n\nThis is how it works, roughly:\n\n 1. acpi_bus_scan() finds the handle of a PCI root bridge,\n creates a struct acpi_device object for it and passes that\n object to acpi_pci_root_add().\n\n 2. acpi_pci_root_add() creates a struct acpi_pci_root object,\n populates its \"device\" field with its argument\u0027s address\n (device-\u003ehandle is the ACPI handle found in step 1).\n\n 3. The struct acpi_pci_root object created in step 2 is passed\n to pci_acpi_scan_root() and used to get resources that are\n passed to pci_create_root_bus().\n\n 4. pci_create_root_bus() creates a struct pci_host_bridge object\n and passes its \"dev\" member to device_register().\n\n 5. platform_notify(), which for systems with ACPI is set to\n acpi_platform_notify(), is called.\n\nSo far, so good. Now it starts to be \"interesting\".\n\n 6. acpi_find_bridge_device() is used to find the ACPI handle of\n the given device (which is the PCI root bridge) and executes\n acpi_pci_find_root_bridge(), among other things, for the\n given device object.\n\n 7. acpi_pci_find_root_bridge() uses the name (sic!) of the given\n device object to extract the segment and bus numbers of the PCI\n root bridge and passes them to acpi_get_pci_rootbridge_handle().\n\n 8. acpi_get_pci_rootbridge_handle() browses the list of ACPI PCI\n root bridges and finds the one that matches the given segment\n and bus numbers. Its handle is then used to initialize the\n ACPI handle of the PCI root bridge\u0027s device object by\n acpi_bind_one(). However, this is *exactly* the ACPI handle we\n started with in step 1.\n\nNeedless to say, this is quite embarassing, but it may be avoided\nthanks to commit f3fd0c8 (ACPI: Allow ACPI handles of devices to be\ninitialized in advance), which makes it possible to initialize the\nACPI handle of a device before passing it to device_register().\n\nAccordingly, add a new __weak routine, pcibios_root_bridge_prepare(),\ndefaulting to an empty implementation that can be replaced by the\ninterested architecutres (x86 and ia64 at the moment) with functions\nthat will set the root bridge\u0027s ACPI handle before its dev member is\npassed to device_register(). Make both x86 and ia64 provide such\nimplementations of pcibios_root_bridge_prepare() and remove\nacpi_pci_find_root_bridge() and acpi_get_pci_rootbridge_handle() that\naren\u0027t necessary any more.\n\nIncluded is a fix for breakage on systems with non-ACPI PCI host\nbridges from Bjorn Helgaas.\n\nSigned-off-by: Rafael J. Wysocki \u003crafael.j.wysocki@intel.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "3c449ed0075994b3f3371f8254560428ba787efc", "tree": "d4ed374d484cc1818c47b66fb71c1955ee277ae9", "parents": [ "b95168e010a405add13aa010d7c45b55dc4026c7" ], "author": { "name": "Yinghai Lu", "email": "yinghai@kernel.org", "time": "Sat Nov 03 21:39:31 2012 -0700" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Mon Jan 07 15:58:48 2013 -0700" }, "message": "PCI/ACPI: Reserve firmware-allocated resources for hot-added root buses\n\nFirmware may have assigned PCI BARs for hot-added devices, so reserve\nthose resources before trying to allocate more.\n\n[bhelgaas: move empty weak definition here]\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "193c0d682525987db59ac3a24531a77e4947aa95", "tree": "7b58346171c4d07e2c2ee6c3c469c325495149a4", "parents": [ "8b0cab14951fbf8126795ab301835a8f8126a988", "1cb73f8c479e66541fefd3f7fa547b1fa56cdc54" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Dec 13 12:14:47 2012 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Dec 13 12:14:47 2012 -0800" }, "message": "Merge tag \u0027for-3.8\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci\n\nPull PCI update from Bjorn Helgaas:\n \"Host bridge hotplug:\n - Untangle _PRT from struct pci_bus (Bjorn Helgaas)\n - Request _OSC control before scanning root bus (Taku Izumi)\n - Assign resources when adding host bridge (Yinghai Lu)\n - Remove root bus when removing host bridge (Yinghai Lu)\n - Remove _PRT during hot remove (Yinghai Lu)\n\n SRIOV\n - Add sysfs knobs to control numVFs (Don Dutile)\n\n Power management\n - Notify devices when power resource turned on (Huang Ying)\n\n Bug fixes\n - Work around broken _SEG on HP xw9300 (Bjorn Helgaas)\n - Keep runtime PM enabled for unbound PCI devices (Huang Ying)\n - Fix Optimus dual-GPU runtime D3 suspend issue (Dave Airlie)\n - Fix xen frontend shutdown issue (David Vrabel)\n - Work around PLX PCI 9050 BAR alignment erratum (Ian Abbott)\n\n Miscellaneous\n - Add GPL license for drivers/pci/ioapic (Andrew Cooks)\n - Add standard PCI-X, PCIe ASPM register #defines (Bjorn Helgaas)\n - NumaChip remote PCI support (Daniel Blueman)\n - Fix PCIe Link Capabilities Supported Link Speed definition (Jingoo\n Han)\n - Convert dev_printk() to dev_info(), etc (Joe Perches)\n - Add support for non PCI BAR ROM data (Matthew Garrett)\n - Add x86 support for host bridge translation offset (Mike Yoknis)\n - Report success only when every driver supports AER (Vijay\n Pandarathil)\"\n\nFix up trivial conflicts.\n\n* tag \u0027for-3.8\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (48 commits)\n PCI: Use phys_addr_t for physical ROM address\n x86/PCI: Add NumaChip remote PCI support\n ath9k: Use standard #defines for PCIe Capability ASPM fields\n iwlwifi: Use standard #defines for PCIe Capability ASPM fields\n iwlwifi: collapse wrapper for pcie_capability_read_word()\n iwlegacy: Use standard #defines for PCIe Capability ASPM fields\n iwlegacy: collapse wrapper for pcie_capability_read_word()\n cxgb3: Use standard #defines for PCIe Capability ASPM fields\n PCI: Add standard PCIe Capability Link ASPM field names\n PCI/portdrv: Use PCI Express Capability accessors\n PCI: Use standard PCIe Capability Link register field names\n x86: Use PCI setup data\n PCI: Add support for non-BAR ROMs\n PCI: Add pcibios_add_device\n EFI: Stash ROMs if they\u0027re not in the PCI BAR\n PCI: Add and use standard PCI-X Capability register names\n PCI/PM: Keep runtime PM enabled for unbound PCI devices\n xen-pcifront: Handle backend CLOSED without CLOSING\n PCI: SRIOV control and status via sysfs (documentation)\n PCI/AER: Report success only when every device has AER-aware driver\n ...\n" }, { "commit": "6be35c700f742e911ecedd07fcc43d4439922334", "tree": "ca9f37214d204465fcc2d79c82efd291e357c53c", "parents": [ "e37aa63e87bd581f9be5555ed0ba83f5295c92fc", "520dfe3a3645257bf83660f672c47f8558f3d4c4" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Dec 12 18:07:07 2012 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Dec 12 18:07:07 2012 -0800" }, "message": "Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next\n\nPull networking changes from David Miller:\n\n1) Allow to dump, monitor, and change the bridge multicast database\n using netlink. From Cong Wang.\n\n2) RFC 5961 TCP blind data injection attack mitigation, from Eric\n Dumazet.\n\n3) Networking user namespace support from Eric W. Biederman.\n\n4) tuntap/virtio-net multiqueue support by Jason Wang.\n\n5) Support for checksum offload of encapsulated packets (basically,\n tunneled traffic can still be checksummed by HW). From Joseph\n Gasparakis.\n\n6) Allow BPF filter access to VLAN tags, from Eric Dumazet and\n Daniel Borkmann.\n\n7) Bridge port parameters over netlink and BPDU blocking support\n from Stephen Hemminger.\n\n8) Improve data access patterns during inet socket demux by rearranging\n socket layout, from Eric Dumazet.\n\n9) TIPC protocol updates and cleanups from Ying Xue, Paul Gortmaker, and\n Jon Maloy.\n\n10) Update TCP socket hash sizing to be more in line with current day\n realities. The existing heurstics were choosen a decade ago.\n From Eric Dumazet.\n\n11) Fix races, queue bloat, and excessive wakeups in ATM and\n associated drivers, from Krzysztof Mazur and David Woodhouse.\n\n12) Support DOVE (Distributed Overlay Virtual Ethernet) extensions\n in VXLAN driver, from David Stevens.\n\n13) Add \"oops_only\" mode to netconsole, from Amerigo Wang.\n\n14) Support set and query of VEB/VEPA bridge mode via PF_BRIDGE, also\n allow DCB netlink to work on namespaces other than the initial\n namespace. From John Fastabend.\n\n15) Support PTP in the Tigon3 driver, from Matt Carlson.\n\n16) tun/vhost zero copy fixes and improvements, plus turn it on\n by default, from Michael S. Tsirkin.\n\n17) Support per-association statistics in SCTP, from Michele\n Baldessari.\n\nAnd many, many, driver updates, cleanups, and improvements. Too\nnumerous to mention individually.\n\n* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next: (1722 commits)\n net/mlx4_en: Add support for destination MAC in steering rules\n net/mlx4_en: Use generic etherdevice.h functions.\n net: ethtool: Add destination MAC address to flow steering API\n bridge: add support of adding and deleting mdb entries\n bridge: notify mdb changes via netlink\n ndisc: Unexport ndisc_{build,send}_skb().\n uapi: add missing netconf.h to export list\n pkt_sched: avoid requeues if possible\n solos-pci: fix double-free of TX skb in DMA mode\n bnx2: Fix accidental reversions.\n bna: Driver Version Updated to 3.1.2.1\n bna: Firmware update\n bna: Add RX State\n bna: Rx Page Based Allocation\n bna: TX Intr Coalescing Fix\n bna: Tx and Rx Optimizations\n bna: Code Cleanup and Enhancements\n ath9k: check pdata variable before dereferencing it\n ath5k: RX timestamp is reported at end of frame\n ath9k_htc: RX timestamp is reported at end of frame\n ...\n" }, { "commit": "1cb73f8c479e66541fefd3f7fa547b1fa56cdc54", "tree": "662259b3d602db1ba4fe203346cc73dff826b2fa", "parents": [ "3ced69f8bba1b766d6c1ea8f26c32a9b3e6fe75c", "dbd3fc3345390a989a033427aa915a0dfb62149f" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Mon Dec 10 16:20:12 2012 -0700" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Mon Dec 10 16:20:12 2012 -0700" }, "message": "Merge branch \u0027pci/mjg-pci-roms-from-efi\u0027 into next\n\n* pci/mjg-pci-roms-from-efi:\n PCI: Use phys_addr_t for physical ROM address\n" }, { "commit": "dbd3fc3345390a989a033427aa915a0dfb62149f", "tree": "ec8c03902652acc7d298a0bd51517d853fb86cde", "parents": [ "f9a37be0f02a943d63e3346b19f9c9d8d91826cb" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Mon Dec 10 11:24:42 2012 -0700" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Mon Dec 10 11:24:42 2012 -0700" }, "message": "PCI: Use phys_addr_t for physical ROM address\n\nUse phys_addr_t rather than \"void *\" for physical memory address.\nThis removes casts and fixes a \"cast from pointer to integer of different\nsize\" warning on ppc44x_defconfig.\n\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "72e1e868ca8f14ef34c95e0e8b73f64b6acf5934", "tree": "d3bc99f121693ab8f09c03ea555254c9314ff98d", "parents": [ "edb1daab8e91338b7e2a6c41faec695891ccda35", "f9a37be0f02a943d63e3346b19f9c9d8d91826cb" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Thu Dec 06 14:37:32 2012 -0700" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Thu Dec 06 14:37:32 2012 -0700" }, "message": "Merge branch \u0027pci/mjg-pci-roms-from-efi\u0027 into next\n\n* pci/mjg-pci-roms-from-efi:\n x86: Use PCI setup data\n PCI: Add support for non-BAR ROMs\n PCI: Add pcibios_add_device\n EFI: Stash ROMs if they\u0027re not in the PCI BAR\n" }, { "commit": "84c1b80e32638f881c17390dfe88143e5cd3f583", "tree": "64310c48ed0dce9d830bd60d280ac0fb59ee28a1", "parents": [ "eca0d4676d8e29c209ddce0c0c1755472ffc70a6" ], "author": { "name": "Matthew Garrett", "email": "mjg@redhat.com", "time": "Wed Dec 05 14:33:27 2012 -0700" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Wed Dec 05 14:38:26 2012 -0700" }, "message": "PCI: Add support for non-BAR ROMs\n\nPlatforms may provide their own mechanisms for obtaining ROMs. Add support\nfor using data provided by the platform in that case.\n\nSigned-off-by: Matthew Garrett \u003cmjg@redhat.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\nTested-by: Seth Forshee \u003cseth.forshee@canonical.com\u003e" }, { "commit": "eca0d4676d8e29c209ddce0c0c1755472ffc70a6", "tree": "0455ac26c96f0a383665fe353d28dbeaa3e1f14b", "parents": [ "dd5fc854de5fd37adfcef8a366cd21a55aa01d3d" ], "author": { "name": "Matthew Garrett", "email": "mjg@redhat.com", "time": "Wed Dec 05 14:33:27 2012 -0700" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Wed Dec 05 14:38:26 2012 -0700" }, "message": "PCI: Add pcibios_add_device\n\nPlatforms may want to provide architecture-specific functionality during\nPCI enumeration. Add a pcibios_add_device() call that architectures can\noverride to do so.\n\nSigned-off-by: Matthew Garrett \u003cmjg@redhat.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\nTested-by: Seth Forshee \u003cseth.forshee@canonical.com\u003e" }, { "commit": "15856ad50bf5ea02a5ee22399c036d49e7e1124d", "tree": "1b57e34523f94ed8b2e9f71dc17197ee2b8c7a4a", "parents": [ "7dc30303342562685392c8c7aa5194e98fd27625" ], "author": { "name": "Bill Pemberton", "email": "wfp5p@virginia.edu", "time": "Wed Nov 21 15:35:00 2012 -0500" }, "committer": { "name": "Greg Kroah-Hartman", "email": "gregkh@linuxfoundation.org", "time": "Wed Nov 28 13:16:47 2012 -0800" }, "message": "PCI: Remove __dev* markings\n\nCONFIG_HOTPLUG is going away as an option so __devexit_p, __devint,\n__devinitdata, __devinitconst, and _devexit are no longer needed.\n\nSigned-off-by: Bill Pemberton \u003cwfp5p@virginia.edu\u003e\nAcked-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@linuxfoundation.org\u003e\n" }, { "commit": "b40b97ae736cad3084b13d2969b10c474572de89", "tree": "dd2a4e0a95c1da764a3b17056b5be1a4d631c18d", "parents": [ "8c610c120fb6ea279e8d01ce7aa555da29e59374" ], "author": { "name": "Bill Pemberton", "email": "wfp5p@virginia.edu", "time": "Wed Nov 21 15:34:57 2012 -0500" }, "committer": { "name": "Greg Kroah-Hartman", "email": "gregkh@linuxfoundation.org", "time": "Wed Nov 28 12:53:46 2012 -0800" }, "message": "PCI: Remove CONFIG_HOTPLUG ifdefs\n\nRemove conditional code based on CONFIG_HOTPLUG being false. It\u0027s\nalways on now in preparation of it going away as an option.\n\nSigned-off-by: Bill Pemberton \u003cwfp5p@virginia.edu\u003e\nAcked-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@linuxfoundation.org\u003e\n" }, { "commit": "3c282db1656733c1267e6af4c22179bb04faf2ef", "tree": "141669ad06cfc2459ec93aeb9d86237328faa61d", "parents": [ "d3fe3988fb24e5ed13b2243b789a652882d3b26c", "918b4053184c0ca22236e70e299c5343eea35304" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Wed Nov 28 11:39:19 2012 -0700" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Wed Nov 28 11:39:19 2012 -0700" }, "message": "Merge branch \u0027pci/misc\u0027 into next\n\n* pci/misc:\n PCI/AER: Report success only when every device has AER-aware driver\n\nConflicts:\n\tdrivers/pci/pcie/aer/aerdrv_core.c\n" }, { "commit": "918b4053184c0ca22236e70e299c5343eea35304", "tree": "7597202f834b5e8c7a42c226894215cbeeb9ef91", "parents": [ "71fbad6c9a28629b6af40b0ff48f36c6610a1394" ], "author": { "name": "Vijay Mohan Pandarathil", "email": "vijaymohan.pandarathil@hp.com", "time": "Sat Nov 17 11:47:18 2012 +0000" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Mon Nov 26 14:46:28 2012 -0700" }, "message": "PCI/AER: Report success only when every device has AER-aware driver\n\nWhen an error is detected on a PCIe device which does not have an\nAER-aware driver, prevent AER infrastructure from reporting\nsuccessful error recovery.\n\nThis is because the report_error_detected() function that gets\ncalled in the first phase of recovery process allows forward\nprogress even when the driver for the device does not have AER\ncapabilities. It seems that all callbacks (in pci_error_handlers\nstructure) registered by drivers that gets called during error\nrecovery are not mandatory. So the intention of the infrastructure\ndesign seems to be to allow forward progress even when a specific\ncallback has not been registered by a driver. However, if error\nhandler structure itself has not been registered, it doesn\u0027t make\nsense to allow forward progress.\n\nAs a result of the current design, in the case of a single device\nhaving an AER-unaware driver or in the case of any function in a\nmulti-function card having an AER-unaware driver, a successful\nrecovery is reported.\n\nTypical scenario this happens is when a PCI device is detached\nfrom a KVM host and the pci-stub driver on the host claims the\ndevice. The pci-stub driver does not have error handling capabilities\nbut the AER infrastructure still reports that the device recovered\nsuccessfully.\n\nThe changes proposed here leaves the device(s)in an unrecovered state\nif the driver for the device or for any device in the subtree\ndoes not have error handler structure registered. This reflects\nthe true state of the device and prevents any partial recovery (or no\nrecovery at all) reported as successful.\n\n[bhelgaas: changelog]\nSigned-off-by: Vijay Mohan Pandarathil \u003cvijaymohan.pandarathil@hp.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\nReviewed-by: Linas Vepstas \u003clinasvepstas@gmail.com\u003e\nReviewed-by: Myron Stowe \u003cmyron.stowe@redhat.com\u003e" }, { "commit": "3d567e0e291c4ffd041cf653aea3c38a1d5f4620", "tree": "254bcf81a4d14eae666ea18f05f19458f81bb372", "parents": [ "f37234160233561f2a2e3332272ae5b3725b620b" ], "author": { "name": "Nithin Nayak Sujir", "email": "nsujir@broadcom.com", "time": "Wed Nov 14 14:44:26 2012 +0000" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Wed Nov 14 22:04:28 2012 -0500" }, "message": "tg3: Set 10_100_ONLY flag for additional 10/100 Mbps devices\n\n- Also refactor the conditional to use the existing tg3_pci_tbl array.\n- Set flags in the driver_data field of the pci_device_id structure to\nidentify these devices.\n- Add PCI_DEVICE_SUB() to pci.h to declare PCI 4-part IDs to match these\ndevices.\n\nSigned-off-by: Nithin Nayak Sujir \u003cnsujir@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "f9c15b429a5c82e613d59a32d4f49cea6e9d64eb", "tree": "b0862edccf51627ed70b6beaf06baaf2134844ea", "parents": [ "0dcccc5c53c55565a6b1061e1b15894495c7c9b9", "1452cd76a97bf7b93a015586dcabc73fd935e692" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Tue Nov 13 14:33:32 2012 -0700" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Tue Nov 13 14:33:32 2012 -0700" }, "message": "Merge branch \u0027pci/don-sriov\u0027 into next\n\n* pci/don-sriov:\n PCI: Remove useless \"!dev\" tests\n PCI: Use spec names for SR-IOV capability fields\n PCI: Provide method to reduce the number of total VFs supported\n PCI: SRIOV control and status via sysfs\n PCI: Use is_visible() with boot_vga attribute for pci_dev\n PCI: Add pci_device_type to pdev\u0027s device struct\n" }, { "commit": "bff73156d3ad661655e6d9ef04c2284cf3abb0f1", "tree": "a26dc79db184a6977919909c3cc2dd653efe83f3", "parents": [ "1789382a72a537447d65ea4131d8bcc1ad85ce7b" ], "author": { "name": "Donald Dutile", "email": "ddutile@redhat.com", "time": "Mon Nov 05 15:20:37 2012 -0500" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Fri Nov 09 21:37:39 2012 -0700" }, "message": "PCI: Provide method to reduce the number of total VFs supported\n\nSome implementations of SRIOV provide a capability structure\nvalue of TotalVFs that is greater than what the software can support.\nProvide a method to reduce the capability structure reported value\nto the value the driver can support.\nThis ensures sysfs reports the current capability of the system,\nhardware and software.\nExample for its use: igb \u0026 ixgbe -- report 8 \u0026 64 as TotalVFs,\nbut drivers only support 7 \u0026 63 maximum.\n\nSigned-off-by: Donald Dutile \u003cddutile@redhat.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "1789382a72a537447d65ea4131d8bcc1ad85ce7b", "tree": "a22142cf3882ccf95e9be73642d3738fb5a72af1", "parents": [ "625e1d59a89f50bace376f429d8cf50347af75f7" ], "author": { "name": "Donald Dutile", "email": "ddutile@redhat.com", "time": "Mon Nov 05 15:20:36 2012 -0500" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Fri Nov 09 20:10:39 2012 -0700" }, "message": "PCI: SRIOV control and status via sysfs\n\nProvide files under sysfs to determine the maximum number of VFs\nan SR-IOV-capable PCIe device supports, and methods to enable and\ndisable the VFs on a per-device basis.\n\nCurrently, VF enablement by SR-IOV-capable PCIe devices is done\nvia driver-specific module parameters. If not setup in modprobe files,\nit requires admin to unload \u0026 reload PF drivers with number of desired\nVFs to enable. Additionally, the enablement is system wide: all\ndevices controlled by the same driver have the same number of VFs\nenabled. Although the latter is probably desired, there are PCI\nconfigurations setup by system BIOS that may not enable that to occur.\n\nTwo files are created for the PF of PCIe devices with SR-IOV support:\n\n sriov_totalvfs\tContains the maximum number of VFs the device\n\t\t\tcould support as reported by the TotalVFs register\n\t\t\tin the SR-IOV extended capability.\n\n sriov_numvfs\tContains the number of VFs currently enabled on\n\t\t\tthis device as reported by the NumVFs register in\n\t\t\tthe SR-IOV extended capability.\n\n\t\t\tWriting zero to this file disables all VFs.\n\n\t\t\tWriting a positive number to this file enables that\n\t\t\tnumber of VFs.\n\nThese files are readable for all SR-IOV PF devices. Writes to the\nsriov_numvfs file are effective only if a driver that supports the\nsriov_configure() method is attached.\n\nSigned-off-by: Donald Dutile \u003cddutile@redhat.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "642c92da36ae0bed3c31fdd408411ab95f4e326b", "tree": "28519422f156133241851c29dac86ed451e00018", "parents": [ "d4761ba2d6adbe24c792ec6223a5884ae4e82430" ], "author": { "name": "Taku Izumi", "email": "izumi.taku@jp.fujitsu.com", "time": "Tue Oct 30 15:26:18 2012 +0900" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Wed Nov 07 09:43:28 2012 -0700" }, "message": "PCI: Don\u0027t pass pci_dev to pci_ext_cfg_avail()\n\npci_ext_cfg_avail() doesn\u0027t use the \"struct pci_dev *\" passed to\nit, and there\u0027s no requirement that a host bridge even be represented\nby a pci_dev. This drops the pci_ext_cfg_avail() parameter.\n\n[bhelgaas: changelog]\nSigned-off-by: Taku Izumi \u003cizumi.taku@jp.fujitsu.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "cdfcc572be0a8b423cecfb4ab5fd735fafe9c54a", "tree": "df188f735b592a2a359969d451ed3dc51ac6e55a", "parents": [ "62a08c5a3173c4462239804b959c0d29dc74493b" ], "author": { "name": "Yinghai Lu", "email": "yinghai@kernel.org", "time": "Tue Oct 30 14:31:38 2012 -0600" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Sat Nov 03 16:26:37 2012 -0600" }, "message": "PCI: Add pci_stop_and_remove_root_bus()\n\nIt supports both PCI root bus and PCI bus under PCI bridge.\n\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "1778794031aae75d4464904319d320edc3e77d39", "tree": "b5157865ab7a86f320ec7fc8128b62ddbb7d0a16", "parents": [ "8f0d8163b50e01f398b14bcd4dc039ac5ab18d64" ], "author": { "name": "Yinghai Lu", "email": "yinghai@kernel.org", "time": "Tue Oct 30 14:31:10 2012 -0600" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Tue Oct 30 14:31:10 2012 -0600" }, "message": "PCI: Separate out pci_assign_unassigned_bus_resources()\n\nIt is main portion of pci_rescan_bus().\n\nSeparate it out and prepare to use it for PCI root bus hot add later.\n\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "607ca46e97a1b6594b29647d98a32d545c24bdff", "tree": "30f4c0784bfddb57332cdc0678bd06d1e77fa185", "parents": [ "08cce05c5a91f5017f4edc9866cf026908c73f9f" ], "author": { "name": "David Howells", "email": "dhowells@redhat.com", "time": "Sat Oct 13 10:46:48 2012 +0100" }, "committer": { "name": "David Howells", "email": "dhowells@redhat.com", "time": "Sat Oct 13 10:46:48 2012 +0100" }, "message": "UAPI: (Scripted) Disintegrate include/linux\n\nSigned-off-by: David Howells \u003cdhowells@redhat.com\u003e\nAcked-by: Arnd Bergmann \u003carnd@arndb.de\u003e\nAcked-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nAcked-by: Michael Kerrisk \u003cmtk.manpages@gmail.com\u003e\nAcked-by: Paul E. McKenney \u003cpaulmck@linux.vnet.ibm.com\u003e\nAcked-by: Dave Jones \u003cdavej@redhat.com\u003e\n" }, { "commit": "6dabee73d46bfafb8c588b21b14606914de97ee6", "tree": "140f679ec718d022e9946d8534af5cd7646340c6", "parents": [ "78890b5989d96ddce989cde929c45ceeded0fcaf", "769ae543dc8d5745e1ade88cbcf1271a96276fd2" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Thu Sep 13 09:08:02 2012 -0600" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Thu Sep 13 09:08:02 2012 -0600" }, "message": "Merge branch \u0027pci/trivial\u0027 into next\n\n* pci/trivial:\n PCI: Drop duplicate const in DECLARE_PCI_FIXUP_SECTION\n PCI: Drop bogus default from ARCH_SUPPORTS_MSI\n PCI: cpqphp: Remove unreachable path\n PCI: Remove bus number resource debug messages\n PCI/AER: Print completion message at KERN_INFO to match starting message\n PCI: Fix drivers/pci/pci.c kernel-doc warnings\n" }, { "commit": "1959ec5f82acbdf91425b41600f119ebecb5f6a8", "tree": "b54bc758f10632e991a3a80a94b05f3940b6651c", "parents": [ "a63ab613ff48c593f4e9ace2d111978e35a202e4", "1d3520357df99baf4ad89f86268ac96cd38092d9" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Wed Sep 12 13:54:10 2012 -0600" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Wed Sep 12 13:54:10 2012 -0600" }, "message": "Merge branch \u0027pci/stephen-const\u0027 into next\n\n* pci/stephen-const:\n make drivers with pci error handlers const\n scsi: make pci error handlers const\n netdev: make pci_error_handlers const\n PCI: Make pci_error_handlers const\n" }, { "commit": "a63ab613ff48c593f4e9ace2d111978e35a202e4", "tree": "067f8172d1a72625458e31869bb587eae5279b80", "parents": [ "a690a4cbf09f70723f9721ca96ab8b2b472b3391", "271fd03a3013b106ccc178d54219c1be0c9759b7" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Tue Sep 11 17:01:54 2012 -0600" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Tue Sep 11 17:01:54 2012 -0600" }, "message": "Merge branch \u0027pci/gavin-window-alignment\u0027 into next\n\n* pci/gavin-window-alignment:\n powerpc/powernv: I/O and memory alignment for P2P bridges\n powerpc/PCI: Override pcibios_window_alignment()\n PCI: Refactor pbus_size_mem()\n PCI: Align P2P windows using pcibios_window_alignment()\n PCI: Add weak pcibios_window_alignment() interface\n" }, { "commit": "ac5ad93e92c3ffca4c7ba386aaa34244e27b7759", "tree": "53709126d79c3718c85fbca2ec5542aec88d4bd1", "parents": [ "479e0d485eaab452cf248cd1a9520015023b35b2" ], "author": { "name": "Gavin Shan", "email": "shangw@linux.vnet.ibm.com", "time": "Tue Sep 11 16:59:45 2012 -0600" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Tue Sep 11 16:59:45 2012 -0600" }, "message": "PCI: Add weak pcibios_window_alignment() interface\n\nThis patch implements a weak function to return the default I/O or memory\nwindow alignment for a P2P bridge. By default, I/O windows are aligned to\n4KiB or 1KiB and memory windows are aligned to 4MiB. Some platforms, e.g.,\npowernv, have special alignment requirements and can override\npcibios_window_alignment().\n\n[bhelgaas: changelog]\nSigned-off-by: Gavin Shan \u003cshangw@linux.vnet.ibm.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\n" }, { "commit": "769ae543dc8d5745e1ade88cbcf1271a96276fd2", "tree": "dfe49ee8a6064ad7effd4fdbcf2fc22cb1ebf71b", "parents": [ "67de07a77eed3970c39653a0e4d636b46ddfd83a" ], "author": { "name": "Mathias Krause", "email": "minipli@googlemail.com", "time": "Sun Sep 02 23:37:24 2012 +0200" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Mon Sep 10 18:06:30 2012 -0600" }, "message": "PCI: Drop duplicate const in DECLARE_PCI_FIXUP_SECTION\n\nIt\u0027s redundant and makes sparse complain about it.\n\nSigned-off-by: Mathias Krause \u003cminipli@googlemail.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "494530284f16298050ab99f54b7b12dd7d1418a1", "tree": "c9f89874141cb81f17e06113add2b1019c3df17d", "parents": [ "0d7614f09c1ebdbaa1599a5aba7593f147bf96ee" ], "author": { "name": "Stephen Hemminger", "email": "shemminger@vyatta.com", "time": "Fri Sep 07 09:33:14 2012 -0700" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Fri Sep 07 16:24:59 2012 -0600" }, "message": "PCI: Make pci_error_handlers const\n\nSince pci_error_handlers is just a function table make it const.\n\nSigned-off-by: Stephen Hemminger \u003cshemminger@vyatta.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\nAcked-by: Linas Vepstas \u003clinasvepstas@gmail.com\u003e" }, { "commit": "7bf79d8a9904ee1ed354e7e655f8045afda67fd6", "tree": "fde1ddd5e0743b9585bef508ff0baf7a8d90288f", "parents": [ "a28afda8cc6a45b2c5a4f98cf8fcddd877597701", "c29aabe22eafb4914aecebab6e99623894d81564" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Thu Aug 23 18:36:10 2012 -0600" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Thu Aug 23 18:36:10 2012 -0600" }, "message": "Merge branch \u0027pci/bjorn-cleanup-remove\u0027 into next\n\n* pci/bjorn-cleanup-remove:\n PCI: Remove unused pci_dev_b()\n sgi-agp: Use list_for_each_entry() for bus-\u003edevices traversal\n parisc/PCI: Use list_for_each_entry() for bus-\u003edevices traversal\n parisc/PCI: Enable PERR/SERR on all devices\n frv/PCI: Use list_for_each_entry() for bus-\u003edevices traversal\n PCI: Leave normal LIST_POISON in deleted list entries\n PCI: Rename local variables to conventional names\n PCI: Remove unused, commented-out, code\n PCI: Stop and remove devices in one pass\n PCI: Fold stop and remove helpers into their callers\n PCI: Use list_for_each_entry() for bus-\u003edevices traversal\n PCI: Remove pci_stop_and_remove_behind_bridge()\n PCI: Don\u0027t export stop_bus_device and remove_bus_device interfaces\n pcmcia: Use common pci_stop_and_remove_bus_device()\n PCI: acpiphp: Use common pci_stop_and_remove_bus_device()\n PCI: acpiphp: Stop disabling bridges on remove\n" }, { "commit": "a28afda8cc6a45b2c5a4f98cf8fcddd877597701", "tree": "2ad4d76e22ddb294fcf31d06b79e7464c70c653a", "parents": [ "e1c171b86baaccab983ded5dfa1663c0981d2520", "defb9446fe417f72855bc8bf97aa5d8af076bdf8" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Thu Aug 23 18:32:36 2012 -0600" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Thu Aug 23 18:32:36 2012 -0600" }, "message": "Merge branch \u0027pci/bjorn-find-next-ext-cap\u0027 into next\n\n* pci/bjorn-find-next-ext-cap:\n PCI: Add Vendor-Specific Extended Capability header info\n PCI: Add pci_find_next_ext_capability()\n\nConflicts:\n\tdrivers/pci/pci.c\n" }, { "commit": "8c0d3a02c1309eb6112d2e7c8172e8ceb26ecfca", "tree": "2fc4d3ef417623384d44b5feb9321dd483408186", "parents": [ "b2ef39be5744d4d3575474444345e71bd95013ba" ], "author": { "name": "Jiang Liu", "email": "jiang.liu@huawei.com", "time": "Tue Jul 24 17:20:05 2012 +0800" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Thu Aug 23 09:41:20 2012 -0600" }, "message": "PCI: Add accessors for PCI Express Capability\n\nThe PCI Express Capability (PCIe spec r3.0, sec 7.8) comes in two\nversions, v1 and v2. In v1 Capability structures (PCIe spec r1.0 and\nr1.1), some fields are optional, so the structure size depends on the\ndevice type.\n\nThis patch adds functions to access this capability so drivers don\u0027t\nhave to be aware of the differences between v1 and v2. Note that these\nnew functions apply only to the \"PCI Express Capability,\" not to any of\nthe other \"PCI Express Extended Capabilities\" (AER, VC, ACS, MFVC, etc.)\n\nFunction pcie_capability_read_word/dword() reads the PCIe Capabilities\nregister and returns the value in the reference parameter \"val\". If\nthe PCIe Capabilities register is not implemented on the PCIe device,\n\"val\" is set to 0.\n\nFunction pcie_capability_write_word/dword() writes the value to the\nspecified PCIe Capability register.\n\nFunction pcie_capability_clear_and_set_word/dword() sets and/or clears bits\nof a PCIe Capability register.\n\n[bhelgaas: changelog, drop \"pci_\" prefixes, don\u0027t export\npcie_capability_reg_implemented()]\nSigned-off-by: Jiang Liu \u003cjiang.liu@huawei.com\u003e\nSigned-off-by: Yijing Wang \u003cwangyijing@huawei.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "b2ef39be5744d4d3575474444345e71bd95013ba", "tree": "1669c64868f78396da4f651d69da6afb43ce6052", "parents": [ "62f87c0e31d646d5501edf4f7feb07d0ad689d80" ], "author": { "name": "Yijing Wang", "email": "wangyijing@huawei.com", "time": "Tue Jul 24 17:20:04 2012 +0800" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Thu Aug 23 09:41:05 2012 -0600" }, "message": "PCI: Remove unused field pcie_type from struct pci_dev\n\nWith introduction of pci_pcie_type(), pci_dev-\u003epcie_type field becomes\nredundant, so remove it.\n\nSigned-off-by: Yijing Wang \u003cwangyijing@huawei.com\u003e\nSigned-off-by: Jiang Liu \u003cjiang.liu@huawei.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "44a9a36f6be43636ac2342c06d9feb60db77826a", "tree": "3ff1b3d23d6416454599aa5712a081fdbe5aaaa0", "parents": [ "0d7614f09c1ebdbaa1599a5aba7593f147bf96ee" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Fri Jul 13 14:24:59 2012 -0600" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Wed Aug 22 13:47:27 2012 -0600" }, "message": "PCI: Add pci_find_next_ext_capability()\n\nSome extended capabilities, e.g., the vendor-specific capability, can\noccur several times. The existing pci_find_ext_capability() only finds\nthe first occurrence. This adds pci_find_next_ext_capability(), which\ncan iterate through all of them.\n\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "c29aabe22eafb4914aecebab6e99623894d81564", "tree": "ca5f6b17942c97de40e073390ac5732454de9097", "parents": [ "0a4af1473a7d81fc90e195fb5b241ab5fcf933ca" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Thu Aug 16 17:13:00 2012 -0600" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Wed Aug 22 11:34:38 2012 -0600" }, "message": "PCI: Remove unused pci_dev_b()\n\nAll uses of pci_dev_b() have been replaced by list_for_each_entry(), so\nremove it.\n\nTested-by: Yijing Wang \u003cwangyijing@huawei.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\nAcked-by: Yinghai Lu \u003cyinghai@kernel.org\u003e" }, { "commit": "125e14bb35e65b1ddfb7252fa8f6e3c50dbb6db2", "tree": "98e1e0489b613fc0b2a1bb4871609ed189c5c4b1", "parents": [ "657c2077a2dab228fcf28a708df1b1bcf4195803" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Fri Aug 17 11:07:49 2012 -0600" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Wed Aug 22 11:31:32 2012 -0600" }, "message": "PCI: Remove pci_stop_and_remove_behind_bridge()\n\nThe PCMCIA CardBus driver was the only user of\npci_stop_and_remove_behind_bridge(), and it now uses\npci_stop_and_remove_bus_device() instead, so remove this interface.\n\nThis removes exported symbol pci_stop_and_remove_behind_bridge.\n\nTested-by: Yijing Wang \u003cwangyijing@huawei.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\nAcked-by: Yinghai Lu \u003cyinghai@kernel.org\u003e" }, { "commit": "657c2077a2dab228fcf28a708df1b1bcf4195803", "tree": "61af7ec744b731078db943088a83b285be2d7845", "parents": [ "0a140577316268b3263fd169d339188ad1636af3" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Fri Aug 17 10:07:00 2012 -0600" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Wed Aug 22 11:31:26 2012 -0600" }, "message": "PCI: Don\u0027t export stop_bus_device and remove_bus_device interfaces\n\nThe acpiphp hotplug driver was the only user of pci_stop_bus_device() and\n__pci_remove_bus_device(), and it now uses pci_stop_and_remove_bus_device()\ninstead, so stop exposing these interfaces.\n\nThis removes these exported symbols:\n\n __pci_remove_bus_device\n pci_stop_bus_device\n\nTested-by: Yijing Wang \u003cwangyijing@huawei.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\nAcked-by: Yinghai Lu \u003cyinghai@kernel.org\u003e" }, { "commit": "786e22885d9959fda0473ace5a61cb11620fba9b", "tree": "bfd70885b7d52deaef338ee212bf66ac682f8e42", "parents": [ "0d7614f09c1ebdbaa1599a5aba7593f147bf96ee" ], "author": { "name": "Yijing Wang", "email": "wangyijing@huawei.com", "time": "Tue Jul 24 17:20:02 2012 +0800" }, "committer": { "name": "Jiang Liu", "email": "liuj97@gmail.com", "time": "Mon Aug 20 22:32:20 2012 +0800" }, "message": "PCI: Add pcie_flags_reg to cache PCIe capabilities register\n\nSince PCI Express Capabilities Register is read only, cache its value\ninto struct pci_dev to avoid repeatedly calling pci_read_config_*().\n\nSigned-off-by: Yijing Wang \u003cwangyijing@huawei.com\u003e\nSigned-off-by: Jiang Liu \u003cjiang.liu@huawei.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "6ee53f4c38e70ba34777ad38807a50c1812ff36f", "tree": "8a4eeef5923d28c2e4ab14f4559e686cc1fce455", "parents": [ "d68e70c6e59ad08feca291c2790164d3231c425e", "1c975931128c1128892981095a64fb8eabf240eb" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Tue Jul 10 08:36:09 2012 -0600" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Tue Jul 10 08:36:09 2012 -0600" }, "message": "Merge branch \u0027pci/bjorn-p2p-bridge-windows\u0027 into next\n\n* pci/bjorn-p2p-bridge-windows:\n sparc/PCI: replace pci_cfg_fake_ranges() with pci_read_bridge_bases()\n PCI: support sizing P2P bridge I/O windows with 1K granularity\n PCI: reimplement P2P bridge 1K I/O windows (Intel P64H2)\n PCI: allow P2P bridge windows starting at PCI bus address zero\n\nConflicts:\n\tdrivers/pci/probe.c\n\tinclude/linux/pci.h\n" }, { "commit": "2b28ae1912e5ce5bb0527e352ae6ff04e76183d1", "tree": "f8fb930ee1277c1e59c3db8bb802867e2c2d9a59", "parents": [ "5dde383e2ef5e22fe7db689dc38c1aabfb801449" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Mon Jul 09 13:38:57 2012 -0600" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Mon Jul 09 19:52:04 2012 -0600" }, "message": "PCI: reimplement P2P bridge 1K I/O windows (Intel P64H2)\n\n9d265124d051 and 15a260d53f7c added quirks for P2P bridges that support\nI/O windows that start/end at 1K boundaries, not just the 4K boundaries\ndefined by the PCI spec. For details, see the IOBL_ADR register and the\nEN1K bit in the CNF register in the Intel 82870P2 (P64H2).\n\nThese quirks complicate the code that reads P2P bridge windows\n(pci_read_bridge_io() and pci_cfg_fake_ranges()) because the bridge\nI/O resource is updated in the HEADER quirk, in pci_read_bridge_io(),\nin pci_setup_bridge(), and again in the FINAL quirk. This is confusing\nand makes it impossible to reassign the bridge windows after FINAL\nquirks are run.\n\nThis patch adds support for 1K windows in the generic paths, so the\nHEADER quirk only has to enable this support. The FINAL quirk, which\nused to undo damage done by pci_setup_bridge(), is no longer needed.\n\nThis removes \"if (!res-\u003estart) res-\u003estart \u003d ...\" from pci_read_bridge_io();\nthat was part of 9d265124d051 to avoid overwriting the resource filled in\nby the quirk. Since pci_read_bridge_io() itself now knows about\ngranularity, the quirk no longer updates the resource and this test is no\nlonger needed.\n\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "85a00dd391d2de1e177c5ad8db5672428934ac20", "tree": "1dbf69da98dd2e4f6d5dfc75f8dacc00d1664f89", "parents": [ "35e7f73c32ad44a931d918d04e317a7fb0c63e6e", "29e8d7bff2f52dd5464a9fb24ece608bbf8fd5ae" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Thu Jul 05 15:31:05 2012 -0600" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Thu Jul 05 15:31:05 2012 -0600" }, "message": "Merge branch \u0027pci/myron-pcibios_setup\u0027 into next\n\n* pci/myron-pcibios_setup:\n xtensa/PCI: factor out pcibios_setup()\n x86/PCI: adjust section annotations for pcibios_setup()\n unicore32/PCI: adjust section annotations for pcibios_setup()\n tile/PCI: factor out pcibios_setup()\n sparc/PCI: factor out pcibios_setup()\n sh/PCI: adjust section annotations for pcibios_setup()\n sh/PCI: factor out pcibios_setup()\n powerpc/PCI: factor out pcibios_setup()\n parisc/PCI: factor out pcibios_setup()\n MIPS/PCI: adjust section annotations for pcibios_setup()\n MIPS/PCI: factor out pcibios_setup()\n microblaze/PCI: factor out pcibios_setup()\n ia64/PCI: factor out pcibios_setup()\n cris/PCI: factor out pcibios_setup()\n alpha/PCI: factor out pcibios_setup()\n PCI: pull pcibios_setup() up into core\n" }, { "commit": "2b6f2c3520124e8bad4bffa71f5b98e602b9cf03", "tree": "f99110de830ffaa0e592d9d66294293ca0c3dd3e", "parents": [ "cfaf025112d3856637ff34a767ef785ef5cf2ca9" ], "author": { "name": "Myron Stowe", "email": "myron.stowe@redhat.com", "time": "Mon Jun 25 21:30:57 2012 -0600" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Tue Jun 26 06:22:31 2012 -0600" }, "message": "PCI: pull pcibios_setup() up into core\n\nCurrently, all of the architectures implement their own pcibios_setup()\nroutine. Most of the implementations do nothing so this patch introduces\na generic (__weak) routine in the core that can be used by all\narchitectures as a default. If necessary, it can be overridden by\narchitecture-specific code.\n\nSigned-off-by: Myron Stowe \u003cmyron.stowe@redhat.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "35e7f73c32ad44a931d918d04e317a7fb0c63e6e", "tree": "e3cb8c89c8230aaa45a0f1b101decdc3b9831938", "parents": [ "e5028b52e46eb1379d78d136bd0890705f331183", "448bd857d48e69b33ef323739dc6d8ca20d4cda7" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Sat Jun 23 11:59:43 2012 -0600" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Sat Jun 23 11:59:43 2012 -0600" }, "message": "Merge branch \u0027topic/huang-d3cold-v7\u0027 into next\n\n* topic/huang-d3cold-v7:\n PCI/PM: add PCIe runtime D3cold support\n PCI: do not call pci_set_power_state with PCI_D3cold\n PCI/PM: add runtime PM support to PCIe port\n ACPI/PM: specify lowest allowed state for device sleep state\n" }, { "commit": "448bd857d48e69b33ef323739dc6d8ca20d4cda7", "tree": "4c1178f9c7dd2d78af2ac1ed26b214b04be1554a", "parents": [ "8497f696686ae1ab3f01e5956046d59844b9f500" ], "author": { "name": "Huang Ying", "email": "ying.huang@intel.com", "time": "Sat Jun 23 10:23:51 2012 +0800" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Sat Jun 23 10:50:59 2012 -0600" }, "message": "PCI/PM: add PCIe runtime D3cold support\n\nThis patch adds runtime D3cold support and corresponding ACPI platform\nsupport. This patch only enables runtime D3cold support; it does not\nenable D3cold support during system suspend/hibernate.\n\nD3cold is the deepest power saving state for a PCIe device, where its main\npower is removed. While it is in D3cold, you can\u0027t access the device at\nall, not even its configuration space (which is still accessible in D3hot).\nTherefore the PCI PM registers can not be used to transition into/out of\nthe D3cold state; that must be done by platform logic such as ACPI _PR3.\n\nTo support wakeup from D3cold, a system may provide auxiliary power, which\nallows a device to request wakeup using a Beacon or the sideband WAKE#\nsignal. WAKE# is usually connected to platform logic such as ACPI GPE.\nThis is quite different from other power saving states, where devices\nrequest wakeup via a PME message on the PCIe link.\n\nSome devices, such as those in plug-in slots, have no direct platform\nlogic. For example, there is usually no ACPI _PR3 for them. D3cold\nsupport for these devices can be done via the PCIe Downstream Port leading\nto the device. When the PCIe port is powered on/off, the device is powered\non/off too. Wakeup events from the device will be notified to the\ncorresponding PCIe port.\n\nFor more information about PCIe D3cold and corresponding ACPI support,\nplease refer to:\n\n- PCI Express Base Specification Revision 2.0\n- Advanced Configuration and Power Interface Specification Revision 5.0\n\n[bhelgaas: changelog]\nReviewed-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nOriginally-by: Zheng Yan \u003czheng.z.yan@intel.com\u003e\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "140217ae3fbabc7b718b5595fd251ce2afcb3bc1", "tree": "1c3d1a367c04203a88b4677376cbd6c8e08d1c65", "parents": [ "e822a007047fb84cd068bfa35a682015e0fe19b9", "0bdb3b213ac64f9a16e59d57660174543eaa01f0" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Mon Jun 18 12:14:16 2012 -0600" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Mon Jun 18 12:14:16 2012 -0600" }, "message": "Merge branch \u0027topic/jan-intx-masking\u0027 into next\n\n* topic/jan-intx-masking:\n PCI: add Ralink RT2800 broken INTx masking quirk\n PCI: add Chelsio T310 10GbE NIC broken INTx masking quirk\n PCI: add infrastructure for devices with broken INTx masking\n" }, { "commit": "47fcb6da65e9e74f71f4ec68f1245fc600bec711", "tree": "6ef869c8f5768d8804ace7c36bbd6d493f995ad1", "parents": [ "cc2fa3fa320d5f40a12713c104bbe5d3da4636e4", "9cb604ed45a31419bab3877472691a5da15a3c47" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Mon Jun 18 12:10:39 2012 -0600" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Mon Jun 18 12:10:39 2012 -0600" }, "message": "Merge branch \u0027topic/stowe-cap-cleanup\u0027 into next\n\n* topic/stowe-cap-cleanup:\n PCI: remove redundant capabilities checking in pci_{save, restore}_pcie_state\n PCI: add pci_pcie_cap2() check for PCIe feature capabilities \u003e\u003d v2\n PCI: remove redundant checking in PCI Express capability routines\n PCI: make pci_ltr_supported() static\n" }, { "commit": "fbebb9fd22581b6422d60669c4ff86ce99d6cdba", "tree": "f7063ec22814ee7782d1ccdb6f8653404d6714c8", "parents": [ "cfaf025112d3856637ff34a767ef785ef5cf2ca9" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Sat Jun 16 14:40:22 2012 -0600" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Sat Jun 16 14:40:22 2012 -0600" }, "message": "PCI: add infrastructure for devices with broken INTx masking\n\npci_intx_mask_supported() assumes INTx masking is supported if the\nPCI_COMMAND_INTX_DISABLE bit is writable. But when that bit is set,\nsome devices don\u0027t actually mask INTx or update PCI_STATUS_INTERRUPT\nas we expect.\n\nThis patch adds a way for quirks to identify these broken devices.\n\n[bhelgaas: split out from Chelsio quirk addition]\nSigned-off-by: Jan Kiszka \u003cjan.kiszka@siemens.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "cc2fa3fa320d5f40a12713c104bbe5d3da4636e4", "tree": "342445a784c566116505ab8c9e7a24803a6e70c4", "parents": [ "10c480933d0ad2ea27630cbaa723a5d33dbece00", "a0dee2ed0cdc666b5622f1fc74979355a6b36850" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Wed Jun 13 17:04:54 2012 -0600" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Wed Jun 13 17:04:54 2012 -0600" }, "message": "Merge branch \u0027topic/alex-vfio-prep\u0027 into next\n\n* topic/alex-vfio-prep:\n PCI: misc pci_reg additions\n PCI: create common pcibios_err_to_errno\n PCI: export pci_user functions for use by other drivers\n PCI: add ACS validation utility\n PCI: add PCI DMA source ID quirk\n" }, { "commit": "10c480933d0ad2ea27630cbaa723a5d33dbece00", "tree": "6938c675ca99e1204d701b4fb60af89d381beeff", "parents": [ "a187177ae047e005a7b40229555837a529a9c2cc", "505cf30b7f4ef64c6db36f34adbe4a7ad9081fd3" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Wed Jun 13 17:04:51 2012 -0600" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Wed Jun 13 17:04:51 2012 -0600" }, "message": "Merge branch \u0027topic/bjorn-remove-unused\u0027 into next\n\n* topic/bjorn-remove-unused:\n PCI/AER: use pci_is_pcie() instead of obsolete pci_dev.is_pcie\n PCI: remove pci_max_busnr() (was already commented out)\n PCI: remove pci_bus_find_ext_capability() (unused)\n" }, { "commit": "67cdc827286366acb6c60c821013c1185ee00b36", "tree": "4d485a56df676726a40f4b9913a9f5362f2c1f2a", "parents": [ "4d99f524234c2e772eea68ad019ec9c805991f23" ], "author": { "name": "Yinghai Lu", "email": "yinghai@kernel.org", "time": "Thu May 17 18:51:12 2012 -0700" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Wed Jun 13 15:42:23 2012 -0600" }, "message": "PCI: add default busn_resource\n\nWe need to put into the resources list for legacy system.\n\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "98a3583107ed587ed3cfe2a1d8e5347421de5a80", "tree": "402af5b2aee4af6f6ffaefb0f856b33f70e4a9b5", "parents": [ "82ec90eac304e81b1389175b4dded7abecc678ef" ], "author": { "name": "Yinghai Lu", "email": "yinghai@kernel.org", "time": "Fri May 18 11:35:50 2012 -0600" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Wed Jun 13 15:42:22 2012 -0600" }, "message": "PCI: add busn_res operation functions\n\nWill use them insert/update busn res in pci_bus struct.\n\n[bhelgaas: print conflicting entry if insertion fails]\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "3527ed81ca01bbaf09df952e68528377a9cd092f", "tree": "1d1665facc89962f6b5454bedec3b296c05b344d", "parents": [ "b918c62e086b2130a7bae44110ca516ef10bfe5a" ], "author": { "name": "Yinghai Lu", "email": "yinghai@kernel.org", "time": "Thu May 17 18:51:11 2012 -0700" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Wed Jun 13 15:42:22 2012 -0600" }, "message": "PCI: remove secondary/subordinate in struct pci_bus\n\nThe pci_bus secondary/subordinate members are now unused, so remove them.\n\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "92f02430934ca1c1e991a1ab3541880575042697", "tree": "03cf0dd66d4d9108f7ea54ebaf10eb2810b0c6b0", "parents": [ "cfaf025112d3856637ff34a767ef785ef5cf2ca9" ], "author": { "name": "Yinghai Lu", "email": "yinghai@kernel.org", "time": "Thu May 17 18:51:11 2012 -0700" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Wed Jun 13 15:42:21 2012 -0600" }, "message": "PCI: add busn_res in struct pci_bus\n\nThis adds a busn_res resource in struct pci_bus. This will replace the\nsecondary/subordinate members and will be used to build a bus number\nresource tree to help with bus number allocation.\n\n[bhelgaas: changelog]\nCC: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "a6961651408afa9387d6df43c4a1dc4fd35dcb1b", "tree": "3ee93b9316123567ebfc65804cb8cc1be95be1e2", "parents": [ "c63587d7f5b9db84e71daf5962dc0394eb657da2" ], "author": { "name": "Alex Williamson", "email": "alex.williamson@redhat.com", "time": "Mon Jun 11 05:27:33 2012 +0000" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Tue Jun 12 09:21:42 2012 -0600" }, "message": "PCI: create common pcibios_err_to_errno\n\nFor returning errors out to non-PCI code. Re-name xen\u0027s version.\n\nAcked-by: Konrad Rzeszutek Wilk \u003ckonrad.wilk@oracle.com\u003e\nSigned-off-by: Alex Williamson \u003calex.williamson@redhat.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "c63587d7f5b9db84e71daf5962dc0394eb657da2", "tree": "215aace1e4365938c497e2329b5c48614e01188d", "parents": [ "ad805758c0eb25bce7b2e3b298d63dc62a1bc71c" ], "author": { "name": "Alex Williamson", "email": "alex.williamson@redhat.com", "time": "Mon Jun 11 05:27:19 2012 +0000" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Tue Jun 12 09:21:42 2012 -0600" }, "message": "PCI: export pci_user functions for use by other drivers\n\nVFIO PCI support will make use of these for user-initiated\nPCI config accesses.\n\nSigned-off-by: Alex Williamson \u003calex.williamson@redhat.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "ad805758c0eb25bce7b2e3b298d63dc62a1bc71c", "tree": "031c42d1537e9ee25b7392a652a7799c3914c972", "parents": [ "12ea6cad1c7d046e21decc18b0e2170c6794dc51" ], "author": { "name": "Alex Williamson", "email": "alex.williamson@redhat.com", "time": "Mon Jun 11 05:27:07 2012 +0000" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Tue Jun 12 09:21:42 2012 -0600" }, "message": "PCI: add ACS validation utility\n\nIn a PCI environment, transactions aren\u0027t always required to reach\nthe root bus before being re-routed. Intermediate switches between\nan endpoint and the root bus can redirect DMA back downstream before\nthings like IOMMUs have a chance to intervene. Legacy PCI is always\nsusceptible to this as it operates on a shared bus. PCIe added a\nnew capability to describe and control this behavior, Access Control\nServices, or ACS.\n\nThe utility function pci_acs_enabled() allows us to test the ACS\ncapabilities of an individual devices against a set of flags while\npci_acs_path_enabled() tests a complete path from a given downstream\ndevice up to the specified upstream device. We also include the\nability to add device specific tests as it\u0027s likely we\u0027ll see\ndevices that do not implement ACS, but want to indicate support\nfor various capabilities in this space.\n\nSigned-off-by: Alex Williamson \u003calex.williamson@redhat.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "c32823f82b42abc1f08b365085862fd1d57c0b61", "tree": "16b70021da6ad1fbf60cede873ed3a4b96525577", "parents": [ "cfaf025112d3856637ff34a767ef785ef5cf2ca9" ], "author": { "name": "Myron Stowe", "email": "myron.stowe@redhat.com", "time": "Fri Jun 01 15:16:25 2012 -0600" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Mon Jun 11 19:33:03 2012 -0600" }, "message": "PCI: make pci_ltr_supported() static\n\nThe PCI Express Latency Tolerance Reporting (LTR) feature\u0027s\npci_ltr_supported() routine is currently only used within\ndrivers/pci/pci.c so make it static.\n\nAcked-by: Donald Dutile \u003cddutile@redhat.com\u003e\nSigned-off-by: Myron Stowe \u003cmyron.stowe@redhat.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "12ea6cad1c7d046e21decc18b0e2170c6794dc51", "tree": "d72a1034cd7436c4b705e86f3cfc83dad03b3574", "parents": [ "cfaf025112d3856637ff34a767ef785ef5cf2ca9" ], "author": { "name": "Alex Williamson", "email": "alex.williamson@redhat.com", "time": "Mon Jun 11 05:26:55 2012 +0000" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Mon Jun 11 18:37:43 2012 -0600" }, "message": "PCI: add PCI DMA source ID quirk\n\nDMA transactions are tagged with the source ID of the device making\nthe request. Occasionally hardware screws this up and uses the\nsource ID of a different device (often the wrong function number of\na multifunction device). A specific Ricoh multifunction device is\na prime example of this problem and included in this patch.\n\nGiven a pci_dev, this function returns the pci_dev to use as the\nsource ID for DMA. When hardware works correctly, this returns\nthe input device. For the components of the Ricoh multifunction\ndevice, it returns the pci_dev for function 0.\n\nThis will be used by IOMMU drivers for determining the boundaries\nof IOMMU groups as multiple devices using the same source ID must\nbe contained within the same group. This can also be used by\nexisting streaming DMA paths for the same purpose.\n\n[bhelgaas: fold in pci_dev_get() for !CONFIG_PCI]\nSigned-off-by: Alex Williamson \u003calex.williamson@redhat.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "109cdbc223f6e2d6c80f8371f22415b50c18a366", "tree": "e27b74808a648a1f98b07a0d93fee9e17e5c5471", "parents": [ "cfaf025112d3856637ff34a767ef785ef5cf2ca9" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Fri May 18 16:52:19 2012 -0600" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Mon Jun 11 11:23:23 2012 -0600" }, "message": "PCI: remove pci_bus_find_ext_capability() (unused)\n\npci_bus_find_ext_capability() is unused, and this patch removes it.\n\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\n" }, { "commit": "7e5b2db77b05746613516599c916a8cc2e321077", "tree": "c3ec333ff7b77bcc8e456a3a3d19bf20f5c651b8", "parents": [ "227d1e4319ffd8729781941d92f4ae4d85beecd9", "c819baf31f5f91fbb06b2c93de2d5b8c8d096f3f" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue May 29 18:27:19 2012 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue May 29 18:27:19 2012 -0700" }, "message": "Merge branch \u0027upstream\u0027 of git://git.linux-mips.org/pub/scm/ralf/upstream-linus\n\nPull MIPS updates from Ralf Baechle:\n \"The whole series has been sitting in -next for quite a while with no\n complaints. The last change to the series was before the weekend the\n removal of an SPI patch which Grant - even though previously acked by\n himself - appeared to raise objections. So I removed it until the\n situation is clarified. Other than that all the patches have the acks\n from their respective maintainers, all MIPS and x86 defconfigs are\n building fine and I\u0027m not aware of any problems introduced by this\n series.\n\n Among the key features for this patch series is a sizable patchset for\n Lantiq which among other things introduces support for Lantiq\u0027s\n flagship product, the FALCON SOC. It also means that the opensource\n developers behind this patchset have overtaken Lantiq\u0027s competing\n inhouse development team that was working behind closed doors.\n\n Less noteworthy the ath79 patchset which adds support for a few more\n chip variants, cleanups and fixes. Finally the usual dose of tweaking\n of generic code.\"\n\nFix up trivial conflicts in arch/mips/lantiq/xway/gpio_{ebu,stp}.c where\nprintk spelling fixes clashed with file move and eventual removal of the\nprintk.\n\n* \u0027upstream\u0027 of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (81 commits)\n MIPS: lantiq: remove orphaned code\n MIPS: Remove all -Wall and almost all -Werror usage from arch/mips.\n MIPS: lantiq: implement support for FALCON soc\n MTD: MIPS: lantiq: verify that the NOR interface is available on falcon soc\n MTD: MIPS: lantiq: implement OF support\n watchdog: MIPS: lantiq: implement OF support and minor fixes\n SERIAL: MIPS: lantiq: implement OF support\n GPIO: MIPS: lantiq: convert gpio-stp-xway to OF\n GPIO: MIPS: lantiq: convert gpio-mm-lantiq to OF and of_mm_gpio\n GPIO: MIPS: lantiq: move gpio-stp and gpio-ebu to the subsystem folder\n MIPS: pci: convert lantiq driver to OF\n MIPS: lantiq: convert dma to platform driver\n MIPS: lantiq: implement support for clkdev api\n MIPS: lantiq: drop ltq_gpio_request() and gpio_to_irq()\n OF: MIPS: lantiq: implement irq_domain support\n OF: MIPS: lantiq: implement OF support\n MIPS: lantiq: drop mips_machine support\n OF: PCI: const usage needed by MIPS\n MIPS: Cavium: Remove smp_reserve_lock.\n MIPS: Move cache setup to setup_arch().\n ...\n" } ], "next": "3df425f316fb5c5e90236ff22b6e6616b3516af0" }