)]}'
{
  "commit": "f12a9473283e68ae708e9ada37cb352ea2652397",
  "tree": "d0886b69596a6031ac705352daa38a13fa0dcc06",
  "parents": [
    "6e0cb135b3f3713b95ea41a11155e83a8c70f5f8"
  ],
  "author": {
    "name": "Sneha Narnakaje",
    "email": "nsnehaprabha@ti.com",
    "time": "Fri Sep 18 12:51:48 2009 -0700"
  },
  "committer": {
    "name": "David Woodhouse",
    "email": "David.Woodhouse@intel.com",
    "time": "Sat Sep 19 11:16:57 2009 -0700"
  },
  "message": "mtd: nand: DaVinci: Add 4-bit ECC support for large page NAND chips\n\nThis patch adds 4-bit ECC support for large page NAND chips using the new\nECC mode NAND_ECC_HW_OOB_FIRST.  The platform data from board-dm355-evm\nhas been adjusted to use this mode.\n\nThe patches have been verified on DM355 device with 2KiB-page Micron\ndevices using mtd-tests and JFFS2.  Error correction up to 4 bits has\nalso been verified using nandwrite/nanddump utilities.\n\nReviewed-by: David Brownell \u003cdbrownell@users.sourceforge.net\u003e\nSigned-off-by: Sneha Narnakaje \u003cnsnehaprabha@ti.com\u003e\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\nCc: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nCc: Troy Kisky \u003ctroy.kisky@boundarydevices.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "0fad6487e6f4bcb062334ae082126d73ad41cd59",
      "old_mode": 33188,
      "old_path": "drivers/mtd/nand/davinci_nand.c",
      "new_id": "f13f5b9afaf744f0ef6e234bf45115c01a83b219",
      "new_mode": 33188,
      "new_path": "drivers/mtd/nand/davinci_nand.c"
    }
  ]
}